Architecture Mid-term question pool
192. VMs hide the real TLB from the guest operating systems (111) A. T B. F
A
46. CPUs designed for desktop machines perform equally well in the server environment (15) A. F B. T
A
89. Mean Time to Fail is a measure of (34) A. How reliable a system is B. Availability C. Quality D. Acceptability E. Reliability F. Dependability G. Maintainability
A, E
87. The reciprocal of Mean Time To Fail is (34) A. Failures in Time B. Average Time To Fail C. Reliability D. Mean Time To Repair E. Mean Time between Failures F. FIT G. Failure Space
A, F
205. The Intel Core i7 processor uses set-associative cache. (120) A. F B. T
B
41. Which is not a class of MIPS instruction (13) A. Arithmetic B. R-Type. C. Logical D. Exception Handling. E. Branch / Jump F. Data Transfer G. Floating Point.
B, D
91. A power supply and its fan both have an MTTF of 200,000 hours. What is the MTTF of the unit if both devices are needed for service? (35) A. Indefinite B. Zero C. 400,000 hours D. 4M Hours E. 100K hours F. 200,000 hours G. 100,000 hours
E, G
241. A commit is when (175) A. A program is terminated. B. Data values are placed in a speculative state. C. An exception occurs. D. Results are written to registers or memory. E. A mispredicted branch is taken. F. An instruction is allowed to write its result G. A branch target is correctly guessed.
D, F
151. Increasing the number of pipeline stages when accessing memory (82) A. Slows down memory access B. Allows more to be done in a clock cycle. C. Requires slower clock cycles D. Decreases access time E. Uses less power F. Increases memory throughput G. Allows multiple requests to be handled at once
F, G
175. The primary motivation for the resurgence of virtual machines is (105) A. Power reduction B. User convenience C. Size D. Speed E. Performance F. Protection G. Security
F, G
219. A common source of parallelism is (157) A. Dependent on multiple cores B. Difficult to find C. Available when arithmetic is performed D. Found in the MIPS instruction set E. Present in large programs F. Found in loops G. Found by unrolling loops
F, G
11. The dramatic increase in processor performance has enabled all but which of the following (4) A. Warehouse scale computing. B. Higher-level languages. C. Computing clouds. D. New classes of applications such as speech-to-text. E. More bug-free applications. F. Longer-lived software products G. Great programmer productivity.
E, F
115. DDR and ECC refer to what kind of component (52) A. Power consumption B. Machine efficiency C. CPU design D. Cumerical accuracy. E. Dynamic RAM F. Main memory G. Power efficiency
E, F
286. Amdahl's Law (230) A. Keeps cache latency from becoming a problem B. Is why we have moved to multi-core processors. C. Prescribes an upper limit to the amount of power a processor can use D. Describes why the effectiveness of SMT is limited E. Explains why some application don't benefit from multithreading. F. Explains why superscalar processors are better than multithreading processors. G. Allows superscalar processors to be smaller each year
D, E
294. Putting out-of-order completions into their correct order is the job of a(n) (238) A. Reverse buffer. B. Backorder buffer. C. Side order buffer. D. Reorder buffer E. Set of extra registers which commit results in the original execution order. F. Branch target predictor. G. In-order buffer.
D, E
56. Reduction in circuit (transistor) size has recently resulted in (21) A. higher memory speeds B. More processor stages per processor C. Supply voltage increases D. More complex architecture on chips E. Multiple cores per chip F. Fewer transistors per core G. CPUs with larger registers
D, E
60. One of the biggest challenges facing computer designers is (21) A. Instruction size B. Arithmetic instructions C. Clock speed D. Power E. Heat dissipation F. Memory speed G. Data flow
D, E
83. Failures in time is the number of failures that occur in (34) A. 1 million hours B. The lifetime of the product C. One year D. 10^9 hours E. One billion hours F. 100,000 hours G. One thousand hours
D, E
90. MTTF / (MTTF + MTTR) is a measure of (34) A. Reliability B. Maintainability C. Quality D. the fraction of time a system is available. E. Availability F. Acceptability G. Dependability
D, E
157. A cache strategy to get the needed information to the processor faster is (86) A. Slick B. Inverse pipeline C. Random Read D. Early restart E. Low-latency cache F. Critical word first G. Accelerated reads
D, F
166. Which concept is invalid? (92) A. Early restart. B. hardware prefetching C. Instruction prefetching D. Operator prefetching E. Compiler prefetching F. Caching-in and caching-out. G. Critical word first
D, F
210. Which of the following statements is not true? (149) A. Loop unrolling remedies control hazards B. Speculative execution can remedy control hazards C. Compilers require some knowledge of the target hardware. D. Cache must have three levels to be effective. E. Efficient code execution requires a good processor and a good compiler. F. Cache memory remedies data hazards G. Forwarding remedies data hazards
D, F
181. The problem with operating systems and security is that (107) A. They are too slow when making security-related decisions B. They were produced by programmers who have little interest in security C. OS-level privileges don't always work. D. They're too big to be bug-free E. Operating systems were conceived of before security was an issue. F. They have a lot of lines of code and hence a lot of vulnerabilities. G. Too many people have access to the source code
D, F
22. price-performance is a key value indicator for (6) A. Servers B. Tablet computers C. Personal Mobile Devices D. Desktop computers E. Automotive applications F. Laptop and desktop computers G. Household appliances
D, F
276. The amount of parallelism available in a program is measured by (217) A. The number of instructions in the program B. The ratio of loads to stores C. How fast the program completes D. How many instructions can be issued in a cycle E. The number of times loops are executed F. The maximum number of instructions that can be issued per cycle G. The ratio of taken branches to branches not taken
D, F
71. What is a significant tradeoff against performance? (27) A. Functionality B. Security C. Portability D. Cost E. Speed F. Price G. Accuracy
D, F
78. Once the dies are etched, how many testing cycles occur before the final package is shipped? (33) A. 3 B. 4 C. 1 D. One before packaging and one after.0 E. 5 F. 2 G. None.
D, F
145. Which needs the most power-efficient memory system (78) A. Personal Mobile Devices B. Cell phones. C. Laptops D. Appliances such as coffee pots. E. Servers F. Automotive computers. G. Desktops
A, B
159. Which cache optimization gets data to the CPU sooner by changing the order in which cache performs its tasks (86) A. Critical word first B. Early restart C. Value prediction D. Hardware prefetch E. Pipelining F. Folding G. Interleaving
A, B
171. Flash memory has a write limitation, but can be written at least _____ times (102) A. 100K B. 100,000 C. 500K D. 1,000,000 E. 100 F. 10,000 G. 1000
A, B
271. Aggressive speculation (213) A. Is not cost-effective B. Isn't worth the cost C. Is the key to processor speed D. Is the key to efficient processors E. Is ineffective in code with a lot of branching F. Works for jumps as well as branches G. Is in common use today
A, B
275. In general, which kind of application has greater available parallelism? (215) A. Ones with loop-intensive arithmetic B. Floating point C. Benchmarks where branch decisions are data dependent D. Integer programs E. Schedulers F. Long running programs G. Compilers
A, B
126. What describes the characteristic that main memory is a superset of cache and that disk is a superset of main memory? (72) A. The inclusive property B. Exclusive memory C. Inclusion D. Locality E. Latency F. The memory hierarchy G. Virtual subsets
A, C
236. Tomasulo scheduling was first implemented (171) A. With the IBM 360 computer. B. In the mid-1990s when the first streaming audio and video processors came out. C. In the 1960s. D. After the powerwall was hit in 2007. E. In 1985 when the MIPS processor was first produced. F. In the past few years. G. In the mid-2000s with the surge in graphics capbility.
A, C
254. VLIW instructions typically require (193) A. Longer execution time than RISC instructions B. Larger memory for program storage C. Multiple, independent functional units D. Complex, interdependent functional units E. A single, long cycle in which to execute F. A five-stage integer pipeline G. Shorter execution time than RISC instructions
A, C
263. Return address predictors are useful because (206) A. Subroutines can be called from many different locations B. Return addresses are difficult to calculate. C. It may save jump address calculation time. D. They are exceptionally accurate E. Subroutines don't always have return addresses F. Subroutines always return to the same location G. Inlining code is a common optimization.
A, C
265. Which task is performed by an Integrated Instruction Fetch Unit? (207) A. Branch Prediction B. Value prediction C. Instruction Prefetch D. Return address prediction E. Exception handling F. Issuing instructions G. Mapping instructions
A, C
273. Which is not a characteristics of a "perfect processor"? (214) A. Unlimited power B. Infinite register renaming C. Unlimited cooling D. Infinite cache E. Perfect memory address alias analysis F. Unlimited instruction issue per cycle G. Perfect branch prediction
A, C
258. Which step in the handling of multiple issue instructions is often the bottleneck? (198) A. The process of issuing instructions B. The functional units C. The reorder buffer D. The Common Data Bus E. The load/store buffers F. The step where multiple instructions are issued G. The reservation stations
A, F
269. Predicting whether two store locations or the location of a read and a store are the same is part of (213) A. Deciding whether instructions can be interchanged. B. Instruction biasing. C. Code size optimization D. Branch prediction. E. Tournament predictors. F. Address aliasing. G. Address alienation.
A, F
284. The Sun T1 processor can best be described as (227) A. A multi-threading processor B. A vector processor C. A single-cycle processor D. A single-core processor with multi-layer cache. E. A superscalar processor F. A fine-grained mutlithreading processor G. A CISC processor.
A, F
34. Which MIPS register has a constant value? (12) A. $zero B. $31 C. $ra D. $fp E. $1 F. $0 G. $29
A, F
149. High associativity results in parallel memory operations and (81) A. Increases power requirements B. Requires less chip hardware C. Reduces clock cycle time D. Decreases power requirements E. Results in slower hit time. F. Increases clock cycle time G. Increases chip area requirements
A, G
239. Robert Tomasulo's scheduling technique was first developed for (172) A. The Commodore 64 B. The IBM 360/91 floating point processor C. Floating point instructions on the IBM 360/91 D. A hand-held calculator E. The IBM personal computer F. The Intel 8080 processor G. The Control Data 3000
B, C
245. Combining branch prediction with multiple issue, we get (183) A. Better exception handling B. Better performance C. Hardware-based speculation D. Better hazard handling E. Lower CPI F. Greater energy efficiency G. More accurate results
B, C
290. Because it is a dual issue processor, the CPI limit of the Cortex A-8 is (233) A. 2.0 B. Two instructions per clock cycle. C. 0.5 D. 1.0 E. Very high. F. 1.5 G. Half an instruction per clock.
B, C
209. Which is not a contributor to CPI? (148) A. Cache miss rates. B. Exception handling. C. structural stalls D. Data hazard stalls. E. Cache miss penalties. F. Processor operating voltage. G. Ideal pipeline CPI.
B, F
47. Besides Instruction Set Architecture, which is also an element of CPU Architecture? (15) A. Power regulation B. L4 Flash Cache C. Memory Bandwidth D. Cache
D
139. If a memory block which was read into cache is subsequently overwritten (because there weren't enough blocks in the set) but then needed again, what kind of miss results? (75) A. Configuration B. Optional C. Capacity D. Conflict miss E. Conflict F. Correlational miss G. Compulsory
D, E
23. Availability, scalability and throughput are selling points for (7) A. Servers B. Server systems C. Automotive applications D. Desktop computers E. Laptop computers F. Personal Mobile Devices G. Tablet computers
A, B
7. After 2003, annual processor performance grew at a rate of (3) A. 22%. B. Over 90%. C. Around 20%. D. 52% E. 37% F. 81% G. A negative rate.
A, C
99. Which is likely to be a good floating-point benchmark? (39) A. XML parsing B. Fluid air flow C. Discrete event simulation D. Image ray tracing E. Zip file compression F. gnu C compiler G. Chess game move predictor
B, D
12. To increase productivity, traditional compile-link-load schemes are being replaced by (4) A. Mobile-based applications. B. Just-in-time compiling and byte-code interpreters. C. Standards-based computing. D. Software as a service. E. Languages like Ruby and Python. F. Agile software development practices. G. A return to languages like C and FORTRAN.
B, E
33. Which is not an architectural characteristic of a processor? (11) A. Addressing modes B. Nature of control flow instructions C. Power consumption D. Memory address alignment E. Clock speed F. Types and sizes of operands G. Class of Instruction Set Architecture
C, E
45. CPU manufacturers never copy instruction sets from another manufacturer (15) A. T B. F
B
17. Which is not a major class of computer? (5) A. Embedded systems. B. Personal mobile devices. C. Virtual computers. D. Desktops. E. Supercomputers. F. Warehouse scale computers. G. Servers.
C, E
36. Which is not an addressing mode used by MIPS processors? (12) A. Displacement addressing. B. Register addressing. C. Data-Indirect. D. Immediate addressing. E. Branch Addressing F. PC-relative addressing.
C, E
77. Which factor most significantly affects yield? (32) A. Testing defects B. The number of tests performed C. Structural anomalies in the silicon ingot D. Packaging defects E. Wafer defects F. Width of the wafer saw G. Design defects
C, E
79. With the advent of warehouse-scale computing, which cost factor has risen in importance (33) A. Cost of replacement B. Cost of maintenance C. Energy efficiency D. Cost of procurement E. Cost of operation F. Fault detection. G. Network security.
C, E
63. Dynamic processor power consumption is proportional to (23) A. Frequency switched * voltage^2 B. Volts * Amps C. Capacitive load * voltage^2 * Frequency switched D. Capacitive load * voltage * Frequency switched E. Volts * Amps * Switching speed F. Frequency switched * voltage^2 * Capacitive load G. Capacitive load * voltage^2
C, F
25. Which is not a critical characteristic of warehouse-scale computing? (8) A. Soft failures and failovers. B. Use of many inexpensive systems to build a larger system. C. Power and cooling management. D. Rack size. E. Extreme testing of components to assure reliability F. Power Utilization Efficiency (PUE). G. Communication and control schemes enabling many machines to act as one.
D, E
27. A key characteristic of an embedded computer is that it (9) A. Is mass produced B. Must perform very quickly C. Has a strict power budget D. Costs very little E. Does not run third-party software F. Is not used by the average consumer G. Is installed in small spaces
D, E
9. Moore's Law (3) A. Has made computers consume less power B. Limits performance increases to the proportion of the problem that can be parallelized C. Allows machines to run cooler. D. Has made computers smaller and smaller E. Continues to wreak havoc in the market. F. Allows more sophisticated circuitry in the CPU. G. Does not apply to parallel processors.
D, F
66. Overclocking is allowed when (26) A. The power supply voltage drops B. Speeds above 2 GHz are required C. More work must be done D. The turbo button is pushed E. The heat can be dissipated F. There is thermal headroom G. The program is running slowly
E, F
93. The relationship between execution time and performance is (36) A. Indirect B. Quadratic C. Direct D. A factor of 1 billion E. Inversely proportional F. Inverse G. Variable
E, F
1. The rapid improvement in computing capability in from 1985-2003 were due to (2) A. The Apollo program which spent billions of dollars to put a man on the moon. B. Cheaper electricity. C. The increased availability of computing devices. D. A drop in the market price for silicon. E. Advances in technology and innovations in computer design. F. The competitiveness of off-shore manufacturing. G. Moore's Law.
E, G
14. Which of the following is not an exploitable parallelism? (4) A. Instruction-level parallelism B. Loop unrolling. C. Request-level parallelism D. Data-Level parallelism. E. Keyboard device drivers. F. Thread-level parallelism G. Ground-level parallelism.
E, G
32. Which of the following is not a major characteristic of an Instruction Set Architecture (ISA)? (11) A. Use of multiple, generic registers B. Addressing modes. C. Required byte alignment D. Instruction length. E. The address to which the processor jumps to handle interrupts. F. Whether or not arithmetic operations can be performed on operands in memory G. use of a hard-wired register whose value is always 0.
E, G
37. Which is a valid MIPS data transfer instruction? (13) A. RM (read memory) B. WM (Write memory) C. LDM (Load Multiple) D. MOV (move) E. STM(store Multiple) F. LW (load word). G. Store Word (SW).
F, G
18. Real-time performance is most important in which class of computers (6) A. Embedded systems. B. Servers. C. Warehouse scale computers. D. Warehouse systems. E. Cloud-based systems. F. Desktops. G. Personal Mobile Devices
A, G
291. The primary addition to CPI above the theoretical base for the A-8 processor is (235) A. Instruction cache misses. B. Floating point delays C. Pipeline stalls D. L1 cache misses E. L2 cache misses F. Pipeline CPI G. Page faults
C, F
105. What kind of locality can be leveraged to improve performance? (45) A. Temporal B. Spatial C. Logical D. Emergent E. Physical F. Temporary G. Special
A, B
112. If half of a current program solving a problem relies on floating point calculations and an enhancement is provided which can drive the time it takes to do floating point calculations to nearly zero. What is the speedup we can expect? (50) A. A factor of two B. 100% C. A factor of 3 D. The problem cannot be sped up E. Can't be calculated from the information given F. A factor of 1 G. One half
A, B
130. Cache power consumption is particularly critical in (74) A. Personal Mobile Devices B. Smartphones and tablets C. Desktops D. Servers E. Data warehouses F. Embedded applications G. Laptops
A, B
143. Cache access time increases as (77) A. Cache size increases B. Associativity increases C. CPU clock period decreases D. Locality decreases E. Longer data words are read F. Coherence increases G. Power requirements increase
A, B
21. Computational energy efficiency is a primary concern in (6) A. Personal Mobile Devices B. Tablet computers C. Household appliances D. Servers E. Automotive applications F. Laptop computers G. Desktop computers
A, B
3. Instruction level parallelism focuses on (2) A. Pipelining and multiple instruction issue. B. Patterns in instruction execution. C. Making programs look the same. D. Increasingly clever designs to cache memory. E. Increasing thermal headroom to allow more threads to execute. F. Branch prediction. G. Advanced cache methods.
A, B
44. The implementation of a computer has two components: (15) A. Organization and hardware. B. Hardware and organization. C. Jumps and branches. D. Input and output. E. Requirements and Design. F. Indexes and pointers. G. Abstract and concrete.
A, B
50. What force threatens the stability of an Instruction Set Architecture? (17) A. Rapid changes is computer technology B. Technology Change C. Investor distraction D. Environmental concerns E. Academic turbulence F. Programmer ability G. The increasing price of silicon
A, B
53. The difference between which pair of performance indicators is of concern? (19) A. Bandwidth and latency B. Latency and bandwidth C. Instruction size and data size D. Power consumption and heat dissipation E. Instruction length and execution speed F. Memory size and memory speed G. Instruction set size and execution speed
A, B
58. Which of the following is not a concern about power (21) A. Lightning strikes B. Surge protection. C. Ability to shut down cores D. What can be done to dissipate the heat E. How much is required at idle F. How much is required at peak activity G. Ability to change processor clock rates
A, B
113. Which statement is true about processing efficiency? (52) A. Design innovations often start with software simulations. B. Power consumption varies linearly with the number of cores executing instructions. C. In general, performance and energy efficiency are correlated. D. A machine running at 10% CPU utilization uses only 10% of its max power consumption. E. Because they are contentious, SPEC benchmarks are rarely used in performance comparisons. F. The slower the clock speed, the greater the efficiency. G. Power supplies are particularly robust and are rarely the cause of system failure.
A, C
147. First-level (L1) cache needs to be small so that it (79) A. Minimizes hit time B. Can use the width of the memory bus C. Requires less power D. Can be a proper subset of L2 cache E. Doesn't store too much extra data F. Doesn't take up so much chip real estate G. Can be flexible
A, C
161. Checking the write buffer to see if a write miss is contained in an outgoing memory block is called (87) A. Merging the write buffer. B. Read-write optimization. C. Write merging D. Buffer checking. E. Snooping. F. Block lookup. G. Backup lookup.
A, C
162. Memory optimizations can be achieved via (88) A. The compiler. B. The VM hypervisor. C. The programmer. D. The disk subsystem E. The memory manager. F. The power supply G. The operating system
A, C
172. Chipkill (105) A. Is like RAID in memory B. is Samsung's 22nm process. C. Distributes data so that failure of a single chip can be tolerated. D. Is Intel's latest processor (code name) E. Is produced by a virus which reads the same memory location over and over. F. IS practiced by buffalo hunters. G. Is when flash memory burns out
A, C
180. The translation lookaside buffer is essentially (106) A. A cache for the page table index B. A place to store unused data. C. A way to exploit temporal locality of memory pages. D. is a way to find bytes of memory the operating system has lost. E. A way to hide sensitive information from a user process F. A way to map physical memory to virtual memory G. How the operating manages different processes
A, C
52. What can be said about Latency and Throughput? (19) A. Throughput grows with the square of latency B. Improving latency is the easy way to improve performance. C. Latency is more expensive to improve than throughput D. Throughput improvement is more difficult to achieve than latency improvement E. Users only care about latency. F. Throughput improvement is rarely cost effective G. It is difficult to measure the effects of improved throughput
A, C
82. Module availability is defined as (34) A. MTTF / (MTTF + MTTR) B. MTTF / (MTTR + MTBF) C. MTTF / MTBF D. (MTTF + MTTR) / MTTF E. MTTF / (MTBR - MTTR) F. MTBF / (MTTF + MTTR) G. MTBF / MTTF
A, C
101. What method is used to summarize benchmark results? (42) A. Geometric mean B. Standard distribution C. Arithmetic mean D. The n-th root of the product of n factors E. Pearson rho F. Exponential distribution G. Covariance
A, D
124. The fastest to memory from the CPU is (72) A. The registers B. L2 Cache C. Flash cache D. L1 Cache E. Disk storage F. Main memory G. L3 Cache
A, D
131. Where blocks can be placed in cache or found in cache is determined by (74) A. Set associativity B. Cache size C. Cache tags D. Associativity E. Inclusiveness F. Locality G. Block size
A, D
152. Which is not an effective way to increase cache performance (82) A. Having one cache block per level. B. Pipelined cache C. Way prediction D. Increased operating voltage E. Critical word first. F. Early restart G. Non-blocking Cache
A, D
160. What does write merging do? (87) A. It checks the cache write-buffer for data no longer in cache B. It reads data into cache even though the first operation on a block is a write C. It reads blocks back from memory immediately after they are written D. It extends temporal locality by looking for missed data in the write buffer E. It waits until data must be read before writing it to main memory F. Waiting to write data until the CPU is sure the data will not be subsequently referenced G. It interleaves cache reads and writes
A, D
173. Early Virtual Machines were implemented in the (105) A. 1970s B. 2000s C. period of time when most programs would fit into main memory. D. era of the first large business computers.00 E. 1980s F. Timei when software cost much more than hardware. G. 1990s
A, D
176. Virtual memory is used to isolate (105) A. Processes B. Users C. Instruction streams D. Programs in memory E. Output devices F. Data files G. Disk files
A, D
19. Price-performance is key to which computer market? (6) A. Gaming machines. B. Cell phones. C. Embedded systems. D. Desktops. E. Personal Mobile Devices. F. The down-clocked market. G. Medical.
A, D
194. I/O is a problem for Virtual Machine Monitors. How is I/O typically managed? (111) A. A separate VM is assigned to each I/O device B. All I/O is routed through disk cache C. An I/O card for each device is used. D. Each I/O device is run by its own VM. E. I/O interactions are optimized and minimized F. I/O is not performed G. High-speed PCI buses are used
A, D
2. A performance-enhancing Instruction Set Architecture was represented by (2) A. The MIPS and ARM designs. B. Accumulator-based instructions. C. CISC (Complex Instruction Set Computer) instructions. D. RISC (Reduced Instruction Set Computer. E. Octal coded instructions. F. VLIW (Very Large Instruction Word) instruction sets. G. VLI (Variable Length Instructions).
A, D
211. ILP is typically exploited within a construct known as a(n) (149) A. Basic block B. do-while loop. C. Interrupt routine. D. Code block. E. for loop. F. if-then statement. G. switch statement.
A, D
24. Scalability, availability and efficient throughput is characteristic of which computer type? (7) A. Servers B. Personal Mobile Devices C. Desktop machines D. Warehouse-scale systems. E. Laptops. F. Embedded devices G. Cell phones.
A, D
268. Aggressive speculation can lead to (211) A. More complex exception handling. B. Simpler processors. C. Lower instruction latency. D. Greater power consumption. E. Efficient code. F. More efficient energy use. G. A more profitable pipeline.
A, D
272. One of the main problems with aggressive speculation is (213) A. Increased circuit complexity. B. Running out of register space C. The difficulties of out-of-order execution D. Increased power consumption E. The time it takes to undo mispredictions. F. Bandwidth demands on main memory G. Demands on cache memory.
A, D
285. Multithreaded processors are better than superscalar processors at (229) A. Finding things to do while the cache services a miss. B. memory I/O rates. C. Branch prediction. D. Hiding cache latency E. Precise exception handling. F. Managing virtual environments. G. Branch folding.
A, D
287. In addition to executing code faster than superscalar processors, multi threaded processors (230) A. Require less energy to execute a given program. B. Tend to run warmer C. Can handle more memory address lines D. Are more energy efficient E. Are less error prone F. Have fewer maintenance needs. G. Crash less often.
A, D
129. Memory efficiency is important in personal mobile devices (PMDs) because (74) A. The power budget is tighter B. Processors are faster C. Clock speeds are higher D. The available address lines are limited. E. Battery life is a big selling point. F. More memory is required. G. Processors are slower
A, E
134. To calculate average memory access time, you need to know (75) A. Miss penalty B. Number of blocks in cache C. Size of main memory D. Cache block size E. Hit time F. Size of cache G. Number of blocks in main memory
A, E
148. What is way prediction? (81) A. Guessing which cache block in a set may contain the desired data B. Getting data from the block most recently accessed C. Guessing which branch a program will take D. Guessing which set the desired block is in E. A method of speeding cache-tag matching if all tags can't be matched at once F. Guessing where the desired block is located in main memory G. Determining how many cache blocks are in a set
A, E
165. Hardware prefetching works by (91) A. Fetching more data than requested B. Fetching instructions and data only when necessary. C. Inserting extra read commands in the program code D. Using narrower, faster memory busses. E. Taking greater advantage of spatial locality. F. Pipelining memory access G. Combining blocks of data more efficiently
A, E
237. WAR and WAW hazards are eliminated by (171) A. Register renaming. B. Faster clock speed. C. More cache. D. Slower clock speed. E. Having enough registers so that storage does not have to be shared. F. More main memory. G. Precise exception handling.
A, E
242. Write-after-Write and Write-after-read hazards are eliminated in Tomasulo scheduling via (177) A. Use of registers to buffer results of instruction execution B. Executing the instruction at the last possible moment C. Executing an instruction only if its result is needed D. the compiler E. Register renaming F. Better interrupt handling G. A slower clock
A, E
252. One way in which multiple micro instructions are "packaged" to perform a larger task is by using (193) A. Consolidate instructions into issue packets. B. Loop unrolling. C. Macro layout design. D. Simple reduced-sized instructions which are decoded into more complex instructions. E. Very long instruction words (VLIW). F. Dynamic scheduling. G. Hardware prefetch.
A, E
255. Loop unrolling to allow rescheduling typically requires (195) A. Register renaming B. More memory C. Smaller code size D. More instructions E. More registers than executing the loop as written F. Larger cache G. More time
A, E
270. What is the main challenge in Instruction Level Parallelism? (213) A. Identifying sections of code which can benefit from it B. Power consumption C. Exception handling D. Finding programmers who understand it E. Finding ways to exploit it F. Transitioning code from single-cycle architectures to multi-stage ones G. Hardware engineering
A, E
72. Which is a significant factor in the cost of computer chips? (27) A. The learning curve B. Age of the design C. Cost of silicon D. Quality of the ingot E. Yield F. The number of transistors on the chip G. Size
A, E
133. Which is a category of cache miss? (75) A. Compulsory B. Consistency C. Constructive D. Collaborative E. Correlated F. Conflict G. Comprehensive
A, F
141. Checking the write buffer on a cache read miss (76) A. May reduce the miss penalty B. Keeps cache incoherency from happening C. Can be prohibitively expensive in some applications. D. Avoids duplicate data E. Requires SRAM cache F. May prevent an access to main memory. G. Makes more efficicent use of cache memory.
A, F
158. If cache blocks can be accessed simultaneously and independently, what kind of cache architecture is being used? (86) A. Multiple banks B. Blocking C. Critical word first D. Way prediction E. Data driven F. Multibanked G. Non-blocking
A, F
196. Why do processors have I and D cache? (113) A. Because of its more sequential nature, instruction cache can be handled better with simpler circuitry. B. Write-through works better for instruction cache than for data cache. C. A program typically accesses more instructions than it does data. D. Data access patterns are more regular. E. Instructions and data are not of equal size. F. Instructions and data behave differently. G. More cache can be fit into the CPU that way.
A, F
199. The Cortex A-8 uses a 16K page size and a 32-bit virtual address. What is therefore the case? (115) A. Each process can think it has up to 4GB of memory available. B. Page faults are more common than with a smaller page. C. The L1 cache index and the L1 cache tags are the same size. D. The virtual page number is 20 bits. E. The page offset is 16 bits. F. The page offset is 14 bites. G. Each process has 16G of memory available.
A, F
232. Dynamic scheduling is done for performance, but what also must happen? (168) A. Completion must be in order B. Cache misses must be handled in order C. Page faults must be disabled D. The compiler must schedule the instructions optimally E. Branch prediction will not work correctly F. Exception handling has to be done as if instructions were executed in order G. Hardware pre-fetching must be enabled
A, F
249. The downsides of optimization techniques covered in Chapter 3 do not include (187) A. Need for larger cache memory. B. Difficulties associated with precise exception handling. C. more complicated roll-back schemes. D. AN increase in the circuitry required on a CPU chip. E. Use of 50-year-old scheduling algorithms. F. Handling CPIs less than 1.0. G. Excessive energy use.
A, F
28. A key characteristic of an embedded computer is that (9) A. It runs pre-loaded or infrequently updated software. B. It must be able to interact with other embedded computers. C. It is small. D. It has no security flaws. E. It is inexpensive. F. It cannot run third-party software G. It can be accessed over the internet.
A, F
5. Significant new computer architectures in the last 40 years do not include (2) A. Wireless charging stations B. Pipelining C. Parallel processors D. Multiple issue processors E. RISC instruction sets F. Better battery technology G. cache
A, F
153. A cache which can service requests while accepting more requests is (82) A. Pipelined B. Leveraging latency to provide bandwidth C. Streamlined D. Less susceptible to blocking on a miss E. Inlined F. Impractical because of prediction complexities G. Using a pipelined architecture
A, G
156. Multi-banked caches (85) A. Spread addresses in a block across the banks B. Require less on-chip logic C. Are too expensive to implement D. Have given way to monolithic caches. E. Suffer from performance issues because the data must be spread across banks. F. Use less power G. Provide faster memory look-up
A, G
16. Industry uses what method to guide improvement in computing? (5) A. A quantitative approach to performance and design B. Statistical analysis of user surveys and polls C. Eliminating competition between companies like AMD and Intel. D. Avoid products made by Microsoft and Intel. E. Finding markets which Microsoft and Intel aren't in. F. Quantitative analysis of web clicks. G. Design based on performance on benchmark suites.
A, G
207. Exploiting Instruction Level Parallelism can be done by ____ and ____. (148) A. the CPU, the compiler B. The linker and the loader. C. main memory, cache memory D. The compiler and the assembler. E. instruction memory, data memory F. the CPU, the ALU G. The compuler and the CPU.
A, G
208. Aggressive software implementations of ILP exploitation (148) A. Are not energy efficient. B. Distinguish ARM processors from the others. C. Have revolutionized the industry. D. require much more complex processors. E. Are necessary in mobile devices. F. make hardware improvements unnecessary. G. Have not succeeded very well.
A, G
224. A correlating branch predictor (162) A. Looks at branching tendencies from more than one branch B. Focuses on a particular branch instruction C. Avoids using local history D. Does not use global history E. Requires at least two mispredictions to change state F. Compares the accuracy of multiple predictors G. Combines a local and a global predictor
A, G
231. When the hardware rearranges the execution order of instructions, this is called (168) A. Dynamic scheduling B. Open source execution C. Compiler-scheduling D. Credible execution E. Control hazard mitigation F. Static scheduling G. Out-of-order execution
A, G
251. A multiple issue processor (192) A. Can schedule more than one instruction for execution in a clock cycle. B. Places limits on virtual memory page size. C. Requires use of unified cache. D. Can write several values in the same cycle E. Is simpler than a superscalar processor F. Has more than one thing wrong with it G. can have a CPI less then 1
A, G
54. Which performance measure has made the greatest progress in the last 30 years? (20) A. Processor bandwidth (instructions/sec) B. Number of processor pins C. Processor surface area D. Latency E. Data bus width F. Clock rate G. Number of transistors
A, G
67. For single-threaded code, performance increases may be had by (26) A. Overclocking B. Running one program at a time. C. Running the program on multiple cores D. Limiting the software to integer operations E. Starting multiple cores at slightly reduced speed F. Increasing the cold air supply G. Shutting down cores and increasing clock speed
A, G
70. Which of the following is not a commodity (27) A. Surface tablets B. Memory chips C. Power supplies D. Desktop computers E. cell phones F. designer iPhone cases. G. iPads
A, G
75. A wafer produces 1000 dies. The yield is 85%. How many dies failed test? (31) A. 150 B. 425 C. 75 D. 333 E. 850 F. 167 G. One hundred fifty
A, G
206. Program parallelism can be found (148) A. Semantically by the processor B. Statically by the compiler C. Dynamically by the processor D. Deliberately by the processor E. In the precompiled header F. Statistically by the compiler G. By the computer architect
B, C
117. Future performance increases are more than ever in the hands of programmers (55) A. F B. T
B
118. Hardware enhancements that increase performance improve energy efficiency or are at worst energy neutral. (56) A. T B. F
B
182. Virtual Machines can imitate other processors' instruction sets (107) A. F B. T
B
197. Because of its limited power budget, the ARM Cortex A8 has more complex cache management than the Intel Core i7 (114) A. T B. F
B
204. The Cortex A-8 can address more physical memory than the Core i7. (118) A. T B. F
B
213. A BEQ instruction immediately followed by an instruction that should not be executed if the BEQ condition is true is an example of what kind of hazard? (150) A. Interrupt hazard. B. Control hazard C. Structural hazard D. Water hazard E. Load-use hazard. F. Data hazard
B
277. Floating point programs have inherently less exploitable parallelism than integer programs (217) A. T B. F
B
68. Increasing the number of transistors increases power consumption even if the transistors are idle (26) A. F B. T
B
10. During the rapid increase in processor performance from 1985-2003, performance was 7-1/2 times greater than it otherwise would have been because of (4) A. better circuit performance. B. Hardware architectural innovations. C. Innovations in pipelining, branch prediction, speculation and multiple issue. D. More efficient cooling fans. E. Byte-code interpreters. F. Better programmers. G. Better compilers.
B, C
103. N performance measurement numbers can be summarized by (42) A. Taking the arithmetic mean of the numbers B. The nth root of the product of the numbers C. Taking the geometric mean of the numbers D. The weighted mean of the numbers E. The average of the numbers F. The standard deviation of the numbers G. The root-mean-square of the numbers
B, C
185. Another name for the Virtual Machine Monitor (VMM) is the (108) A. Guest operating system B. Virtual Machine Manager C. Hypervisor D. User application. E. Surveyor F. Core manager G. Supervisor
B, C
212. A load word (lw) instruction immediately followed by an add instruction which uses a loaded value is an example of what kind of hazard (150) A. Structural hazard B. Load-use hazard. C. Data hazard D. Water hazard E. Control hazard F. Page fault. G. Branch hazard.
B, C
214. One of the difficulties in implementing instruction-level parallelism is (150) A. Memory response time B. Data dependencies C. Control dependencies D. Branch prediction E. Address dependencies F. Clock speed G. Cache collisions
B, C
226. Which is not a branch predictor type? (164) A. One-bit B. Stochastic C. Statistical D. Two-bit E. Local F. Tournament G. Global
B, C
230. The Intel Core i7 branch predictor (166) A. Can predict whether or not a program will crash. B. Synthesizes the best outcome from diverse individual predictors. C. Details are considered proprietary. D. Does not predict at all but rather optimizes branch delay-slot instructions. E. Employs techniques widely published and well understood in the architecture community. F. Is only useful with the right compiler. G. Uses a single, highly optimized and accurate predictor
B, C
234. Complex instructions in a pipeline can lead to (169) A. Inaccurate exception handling. B. Challenges in exception handling. C. Imprecise exception handling. D. Abnormal termation. E. Uncertain exception handling. F. Speculative execution. G. Unwieldy exception handling.
B, C
69. In chip manufacturing, "Yield" refers to (26) A. Stopping a production line when it becomes inefficient B. The number of chips that can be shipped vs the number originally created C. The percentage of dies that actually work D. The number of dies which work vs the number which don't. E. The amount of physical deformation a chip can have before it breaks. F. The wasted area on a wafer due to the fact that the dies are rectangular and the wafer is round G. Waiting for future technology changes to make chip production more cost-effective
B, C
80. With good system design, component failure will result in (33) A. Lower power consumption B. Graceful fail-over. C. Slight performance degradation D. Desensitized customers E. Short entries in the operations log. F. An exception being thrown G. System shutdown
B, C
136. Which write strategy simultaneously updates cache and its lower level store? (75) A. Write back B. Write through C. Write allocate D. Write-through E. Write around F. Write out G. Write left
B, D
155. A Cache which continues to service requests while processing a miss is called (83) A. Cache La Poudre B. Non-blocking cache C. Read-through cache D. Lockup-free cache E. Blocking cache F. Locking cache G. Read-write cache
B, D
168. Which is organized by memory speed from fastest to slowest? (98) A. Flash, DRAM, SDRAM B. SRAM, SDRAM, DRAM, Flash C. SRAM, DRAM, SDRAM, Flash D. SDRAM, DRAM, Flash E. Flash, SRAM, SDRAM F. SDRAM, DRAM, Flash, SRAM G. SRAM, SDRAM, Flash, DRAM
B, D
228. A tournament predictor (164) A. Establishes point spreads for branch instructions. B. Assesses the accuracy of multiple predictors. C. looks at local and global branch history. D. Chooses the predictor which is currently the most accurate E. Tries to out-guess other predictors. F. Is the central element of a chess-playing program. G. Is used in bull-fight games.
B, D
246. If a block of code contains no branches (185) A. The compiler cannot provide optimizations B. Speculative execution is not needed C. The processor cannot provide optimizations D. There are no control hazards E. Multiple issue is inconsequential F. Loop unrolling is the only way to obtain parallelism G. Tomasulo scheduling is not needed
B, D
248. In Tomasulo's scheduling method, writing out the result of an instruction also involves (186) A. Writing to cache B. Supplying that value to any waiting instruction which needs it C. Translating the physical address into virtual format D. Checking the reservation stations to see if that value is needed E. Handling any exceptions that may have occurred F. Encoding the result into floating point format G. Writing to main memory
B, D
256. Original Tomasulo scheduling does not support (197) A. Multiple issue B. Speculation C. Multiple floating point units D. Branching E. Register renaming F. Instruction-level parallelism G. Loop unrolling
B, D
264. Besides predicting branches and branch targets, what other kind of technique can be done for better jump performance? (206) A. Predicting what kind of jump instruction it is B. Predicting the return jump C. Predicting whether the jump will be forwards or backwards D. Return address prediction E. Not performing jumps at all F. Automatically pushing and popping the $ra register without explicit instructions G. Using the stack to store return addresses rather than a register
B, D
48. Which is an element of (overall) computer architecture? (15) A. Power B. Organization C. Layout D. Hardware E. Design F. Structure G. Speed
B, D
59. A linear decrease in feature size on a silicon chip results in (21) A. linear increase in power consumption B. An increase in density proportional to the square of the size reduction. C. An exponential difference in latency D. Quadratic increase in transistor density E. a geometric reduction in reliability. F. quadratic increase in speed G. linear decrease in performance
B, D
61. Thermal design power is (22) A. Heat level at which the CPU fan comes on B. Sustained processor operating power C. Heat level at which transistors fail D. Average power consumed by the processor during computation E. The power level below which a cooling system is not needed F. Peak power that a processor can safely manage G. Power level at which the processor shuts down to protect itself
B, D
64. Which of the following does not affect CPU power consumption (23) A. capacitive load B. Source code language C. Clock speed D. Velocity factor E. Supply voltage F. Switching frequency G. Static power
B, D
65. What method is used to help processors run cooler? (25) A. Slow down the video frame rate if videos are playing while calls are being made B. Reduce the processor supply voltage C. Shut down the processor when it's not in use D. Lower the display intensity of the LCD screen E. Disable the clock to idle units F. Reduce the clock frequency when the processor runs hot G. Schedule jobs that consume a lot of power at night when it is cooler
B, D
116. When electrical power consumption is factored into the price-performance calculations for servers, what happens? (55) A. The fastest processors are also the most efficient. B. Speed is not the goal. C. Power supply voltages are unimportant. D. Electrical power consumption is small enough that it does not change the results. E. The slowest processors can become the most efficient. F. Efficiency is not the question. G. Idle power is a more important determinant of performance than dynamic power.
B, E
189. Virtualizing I/O is difficult because of (110) A. Variations in operating systems B. New types of I/O hardware C. Small page size D. The speeds required E. The number of different I/O devices F. CPU instruction privilege levels G. Memory bandwidth
B, E
191. Virtual Machines require processors to have special instructions for all the following reasons except (110) A. It must trap hardware interaction attempts from Operating Systems B. VMs would be hopelessly inefficient without them C. Multiple privilege levels are required when running VMs D. VMs need to "fool" OSs into thinking they're in charge. E. No one would buy the VM software if it didn't use special instructions. F. Special instructions are required for process isolation. G. The VM must be closer to the processor than a guest OS
B, E
238. In general. RAW hazards can be eliminated by (172) A. Limiting the number of registers available. B. Scheduling which uses reservation stations. C. Slower clock speed. D. Better exception handling. E. Tomasulo scheduling. F. Pipelining instructions. G. Using separate instruction and data cache.
B, E
262. In order to keep multiple-issue processors operating effectively (203) A. Code blocks should be as long as possible. B. The processor must cache at least as many instructions as are issued each cycle. C. Processors should use unified cache. D. Structural hazards should be avoided. E. Methods of predicting which instructions will be executed are useful F. Exception handling should be minimized G. Loop unrolling is used.
B, E
280. What does multithreading allow? (223) A. Quicker operation of functional units B. More intensive use of functional units C. More efficient cache utilization D. More instructions to be executed in a certain time E. Multiple threads to share functional units F. Less traffic on the data bus G. Fewer page faults
B, E
283. The threading concept which wastes the fewest cycles is (225) A. Coarse-grained multi threading B. Threading which can execute instructions from different threads in the same cycle. C. Superscalar D. Fine-grained multi threading E. Simultaneous multi threading. F. Threading which can execute instructions from one thread in a clock cycle. G. Threading which must execute instructions from the same thread across multiple cycles.
B, E
30. Which instruction scheme has not been developed commercially? (10) A. Single Instruction Single Data (SISD) B. Single-instruction, no data (SIND) C. Multiple Instruction Multiple Data (MIMD) D. Single Instruction Multiple Data (SIMD) E. Multiple Instruction Single Data (MISD)
B, E
31. The Instruction Set Architecture (11) A. Should be mandated by industry standards. B. Should reflect the needs of the applications. C. Is all you generally need to understand about computer architecture. D. Must be focused on a small set of problems or applications to be efficient. E. Is the boundary between hardware and software. F. Has little to do with performance. G. Is uniquely responsible for machine performance.
B, E
43. Which is not a major distinguishing feature of an Instruction Set Architecture (14) A. Instruction byte alignment. B. Support for integer and floating point data types C. Use of instruction conditions. D. Memory addressing modes. E. Whether or not instructions can contain data. F. Data byte alignment. G. Fixed or variable instruction length.
B, E
76. Order the objects from smallest to largest (31) A. core, register, chip B. die, package, wafer, ingot C. package, wafer, ingot, die D. ingot, wafer, die, package E. Transistor, core, processor F. die, wafer, package, ingot G. core, die, processor
B, E
85. A "contract" or specification which decides whether a device works or not is called a(n) (34) A. Acceptability and Accountability Report B. Service Level Agreement C. Service Proposal D. Software Requirements Specification E. Service Level Objective F. End User License Agreement G. Work Order
B, E
98. Which is essentially an integer processing benchmark? (39) A. Weather prediction B. The gnu C compiler C. Image ray tracing D. Fluid air flow E. Zip file compression F. Molecular dynamics G. Speech recognition
B, E
102. Which is most likely to be used to measure a machine's performance (42) A. Wattmeter B. Benchmark suite C. Stopwatch D. Very complicated programs E. Analytical balance F. A set of real programs G. Logic analyzer
B, F
106. Which is not a quantitative principle of computer performance design (45) A. Take advantage of parallelism B. Avoid the unavoidable C. Focus on the common case D. Principle of Locality E. Amdahl's Law F. Implement redundancy G. The processor performance equation
B, F
109. Diminishing returns characterizes (47) A. the speedup of infinitely parallelizable problems B. the effects of processor speedup C. Moore's Law D. Ohm's Law E. Newton's Laws F. Amdahl's Law G. Henry's Law
B, F
125. Cache leverages __________ locality (72) A. Permanent B. Temporal C. Parallel D. Special E. Temporary F. Spatial G. Uniform
B, F
140. The simplest way to decrease cache miss rate is to take advantage of spatial locality and (76) A. Use wider data paths to the CPU B. Increase cache size C. Look up data faster D. Have larger main memory. E. Speed up the system clock F. Use larger cache blocks G. Increase virtual memory.
B, F
150. Way prediction is a cache optimization which (81) A. Costs nothing if it is wrong. B. Guesses which block the data is in C. Is equivalent to branch prediction. D. Uses the same data as last time E. Guesses what the data is F. Predicts the block in the set in which the tag will match G. Works even if it's wrong most of the time
B, F
92. MTTR and MTTF are both needed to calculate (35) A. Performance B. MTTF of parallel components C. Responsiveness D. Failures in time E. Efficiency F. MTTF of serial components G. Availability
B, G
154. How does non-blocking cache work? (83) A. It reads more than one block of data from main memory at once B. It can provide data even though it is also handling a miss C. It uses a pipeline, but services one request at a time D. It can handle accesses to long data types which span block boundaries E. It has only one level which contains a lot of memory F. It continues to service hits while servicing one or more misses G. Data are organized as single bytes
B, F
20. Which is not considered a personal mobile device? (6) A. A iPhone. B. A stopwatch. C. An iPod. D. An iPad. E. A fitbit activity tracker. F. A hearing aid. G. An Android phone.
B, F
240. In Tomasulo's scheduling method, instructions are delayed if (174) A. Their execution would interfere with other instructions B. Data are not ready C. Preceding instructions have not finished D. Preceding instructions have not started E. The result is not needed F. The instruction lacks data G. They would take too long to execute
B, F
244. Effective use of speculation requires (183) A. Instructions are always executed in the order the compiler specified. B. Being right most of the time. C. Use of very large branch prediction tables. D. Very quick branch prediction. E. Writes always occur in execution order. F. The ability to roll back or undo instructions. G. Making the programmer responsible for accurate branch prediction.
B, F
38. The "I" suffix on a MIPS instruction typically means (13) A. The instruction creates an interrup.t B. The instruction contains immediate data C. The instruction is imperative and will always execute. D. The instruction contains no data. E. The instruction requires three registers. F. It is an I-type instruction. G. The instruction services an interrupt.
B, F
40. The ".D" and ".S" suffixes may follow which instructions (13) A. Exceptions. B. Single- or double-precision instructions. C. Integer arithmetic. D. Logicals (OR, AND, etc). E. Instruction which operate on 8-byte integers. F. Floating point arithmetic G. Branches.
B, F
51. Which technology has the least impact on processor design? (17) A. Transistor density B. Available colors for plastic cases C. Cache logic design D. Memory architecture E. Integrated circuit technology F. Power supply design G. Memory bandwidth
B, F
6. Between 1985 and 2003, processor performance grew at an annual rate of (3) A. 22%. B. 52%. C. 0ver 80%. D. 37%. E. Around 10%. F. over 50% G. 81%
B, F
73. Which does not impact the cost of a commodity integrated circuit? (28) A. Cost of raw materials. B. Labor required to produce the photo mask. C. Cost of testing D. Cost of packaging E. Demand. F. Cost of design G. Yield
B, F
8. Dramatic increases in computer performance led to (3) A. Loss of jobs B. New classes of computers C. Simpler computer designs. D. A reduction in power consumption. E. The dot-com stock market bust in 2001 F. Larger instruction sets. G. More people entering the field of Law Enforcement
B, F
84. The concept "Failures in time" is based on a time span of _____ hours. (34) A. Ten Billion B. 1,000,000,000 C. One Million D. 1E6 E. 1E10 F. One Billion G. Ten Million
B, F
127. Since 1980, processor performance and memory performance (73) A. Have gotten better B. Have grown increasingly farther apart C. Are increasingly unrelated D. Reflect the rise in personal mobile devices E. Have kept pace with each other F. Have started to converge G. Have diverged
B, G
128. With the increase in number of cores on a processor, (73) A. Larger disk systems are necessary B. Supplying data becomes a challenge C. Each core has less work to do D. The chip uses less power E. Pin voltage drops F. Cache design becomes simpler. G. Demands on memory increase
B, G
169. GPU data requirements are met best by (99) A. SDRAM B. GSDRAM C. SRAM D. DRAM E. Flash memory F. DDR3 G. GDRAM
B, G
170. DDR1 DRAM operates at 2.5v. DDR3 DRAM operates at 1.5v. Approximately how many times more power does DDR1 RAM consume vs DDR3 RAM? (101) A. About 2 times B. About 3 times C. Need clock frequency to determine the answer. D. About 4 times E. 2.5 / 1.5 or 1.33. F. The same. Power does not depend on voltage. G. 6.25 / 2.25 or about 3.
B, G
177. To be effective, a CPU executing a virtual memory system must have separate instruction privileges for user and _______ processes (106) A. Cache B. Kernel C. Disk D. Input/Output E. Memory F. Virtual G. Supervisor
B, G
221. Loop unrolling (159) A. Requires less data storage space B. Performs multiple iterations in one block of code C. Can be performed on any sequence of instructions D. Improves program bandwidth E. Requires fewer registers F. Reduces the number of instructions in a program G. Eliminates significant numbers of branch instructions
B, G
259. Branch speculation works particularly well in (201) A. Multiple issue processors B. Loops C. Processors with many reservation stations D. Large reorder buffers E. Deep floating point pipelines F. Straight-line (non-looping) code containing branches G. Long loops
B, G
260. The branch delay stall can be eliminated (203) A. Using a branch history table B. Predicting the PC after a branch instruction C. Predicting whether an instruction will branch D. Using the reorder buffer E. Assuming the branch instruction is not taken F. Assuming the branch instruction is taken G. Using a branch target buffer
B, G
35. Which is not an area concerned with Instruction Set Architecture? (12) A. Byte alignment. B. Reliability. C. Multiple issue and hazard detection. D. Register number and size. E. Instruction length. F. Addressing modes. G. Mnemonics.
B, G
49. Which technology trend are we not particularly concerned about in computer architecture (17) A. Bandwidth and Latency B. Size of the instruction set C. Feature size (size of "wires" on the chip) D. Power consumption E. Magnetic disk storage density F. Integrated circuit logic G. Physical chip size
B, G
55. State of the art chip technology produces "wires" of what size? (20) A. 10 microns now B. 14 nm in 2015 C. 45nm when the book was published D. 32 nm E. 001 mm in 2015 F. 7 nm currently G. 22nm when the book was published
B, G
94. The best choice of programs to evaluate performance is (37) A. to use synthetic benchmarks. B. to use real applications under realistic conditions C. to use standard simulations. D. The most popular program run by users. E. to use toy programs F. to use no user programs at all. G. to use programs that are actually run.
B, G
200. Cache simulations rather than actual processor runs are used to analyze Cortex A-8 performance. (115) A. * B. F C. T
C
253. Which is not a type of multiple-issue processing (193) A. Dynamic scheduled superscalar B. Very Long Instruction Word (VLIW) C. Reduced Instruction Set Computer (RISC) D. Statically scheduled superscalar
C
100. Which of the following is not a server for which a specific benchmark has been developed? (40) A. Web B. Email C. Firewall D. Network login E. Database F. File G. Transaction Processing
C, D
138. If a cache set is completely full (all blocks used), which kind of miss is possible? (75) A. Conflict B. Compulsory C. Capacity D. Capacity miss E. Correlational miss F. Optional G. Configuration
C, D
222. The key to effective rescheduling is (161) A. Avoid branch instructions B. Execute as many instructions as quickly as possible C. Producing the correct result D. Reading and committing values in the original order E. Memory alignment F. Effective branch prediction G. The instruction set architecture
C, D
250. Instruction results are written to registers or memory when (190) A. When the reorder buffer is full B. Another instruction need them C. They are committed D. The reorder buffer decides it's time E. Page faults occur F. They are put on the common data bus G. There is a cache miss
C, D
279. A grave danger in speculative execution is (222) A. Obtaining a result before it can be committed B. Guessing an incorrect value C. Predicting a jump or branch to an invalid address D. Generating a page fault that otherwise wouldn't occur E. Executing the wrong instruction F. Not having data ready for an instruction to execute G. Having to wait until the branch outcome is obtained
C, D
107. According to Amdahl's law (46) A. AMD keeps Intel honest. B. Speedup is linear C. If half of a problem is subject to speed up, the maximum speedup factor is two. D. Speedup is proportional to the number of processors used. E. speedup depends on the fraction of the problem that can be sped up F. Every process can be sped up G. Every 18 months, processors go twice as fast
C, E
108. Amdahl's Law says (46) A. The number of transistors on an integrated circuit doubles every 18-24 months B. Redundancy is better than reliability C. Performance gain due to an enhancement is limited by the fraction of the problem that can use the enhancement. D. Higher performance means higher power E. The proportion of a problem that can use the enhancement limits the possible speedup F. Speedups caused by an enhancement cannot be measured directly G. Execution time is inversely proportional to performance
C, E
114. What non-standard configuration would be inconsequential in the benchmarking context (52) A. Running atmospheric modeling benchmarks on a system with a small ATA data disk B. Using redundant video cards on a database server benchmark. C. Using redundant power supplies. D. Having more physical than virtual memory. E. Running server bench marks on a system with a tiny 50GB system disk F. Running integer benchmarks on a water-cooled, overclock CPU G. Running floating point benchmarks on a system with a lot of graphics processing hardware
C, E
120. To be effective, fault detection must be combined with (57) A. Redundancy. B. Data buffering. C. A way of fixing the fault. D. Jump instructions. E. Error correction. F. The operating system. G. Parallel processes.
C, E
121. Which is not a CPU? (62) A. Intel Atom. B. AMD Opteron C. Commodore 64. D. Intel Core i7 E. Apple Macintosh. F. IBM Power7. G. Cortex A9
C, E
123. The inclusion property (applied to cache) says that (72) A. Everything must be in memory at one time B. Each level of cache must be the same size, although blocking can be different. C. The lowest level of memory (e..g L3)is a superset of the next higher level (e.g., L2) D. L1 and L2 cache must contain the same data E. Everything in L1 cache is also in L2 and L3 Cache F. L1 cache must be consistent with L2 cache at all times G. Everything in L3 must be in L2
C, E
132. A block can be placed in only one location in ____________ cache (74) A. n-way set associative B. Fully associative C. Direct mapped D. Two-way set associative E. One-way set associative F. Three-way set associative
C, E
137. The access to the first instruction when a program runs causes which kind of cache miss: (75) A. Optional B. Configuration C. Compulsory miss D. Conflict E. Compulsory F. Capacity G. Correlational miss
C, E
144. Which type of machine puts the heaviest demand on the memory subsystem? (78) A. Embedded machines. B. Personal Mobile Devices C. Servers D. Low-power devices. E. Machines running more user processes. F. Desktops G. Laptops
C, E
146. Keeping the first level cache small (79) A. Decreases the miss rate B. Is not recommended C. Reduces hit time and power D. Makes it more likely data will be found in cache E. Can raise the miss rate F. Depends on the size of main memory G. Reduces clock cycle time
C, E
195. Which Architecture is most compatible with Virtual Machine Management (112) A. Control Data 3800 B. Cray array processing C. IBM System 370 D. ARM Cortex A8 E. IBM 370 F. Sun Sparc G. Intel Core i7
C, E
233. How do dynamically scheduled processors handle exceptions? (169) A. They are handled in the order they are raised B. Exceptions are handled at the end of the cycle in which they are raised C. The exception is buffered until the instruction would normally be completed in order D. The earliest stage in which an instruction is raised is handled first E. The processor waits until all instructions previous to the excepted one have completed before raising the exception F. The latest stage in which an instruction is raised is handled first G. Exceptions are handled the cycle after the cycle in which they are raised
C, E
235. The use of reservation stations is a key feature of (170) A. Moore's Law B. Box-office scheduling C. The Tomasulo scheduling algorithm D. Pipeline delays. E. The scheduling system developed by Robert Tomasulo. F. Heisenberg uncertainty G. Conservative scheduling approaches.
C, E
243. Tomasulo's algorithm is basically (178) A. managing large arrays of data in disk. B. Executing instructions until an interrupt occurs, then switch processes. C. Executing an instruction when its data is available. D. Guessing data values, executing instructions as soon as possible, and rolling back results if the input values were determined to be incorrect. E. Issuing multiple instructions and holding them until their data requirements are met. F. Prioritizing instructions for execution. G. Executing instructions and determining after the fact whether or not they were correct.
C, E
292. The Intel Core i7 processor has ___ pipeline stages (237) A. Twelve B. Ten C. Fourteen D. 1 E. 14 F. 8 G. 5
C, E
39. After which instruction is the "U" suffix inappropriate? (13) A. SUB B. ADD C. BEQ D. SLT E. JAL F. ADDI G. LB
C, E
110. A certain problem is 50% floating point, 50% integer in nature, half the execution time is taken up by each portion. If an improvement sped up the floating point infinitely (taking no time at all), how much faster could the problem be solved? (48) A. Can't be solved B. Four times C. Two times D. Half as fast E. Infinitely faster F. Twice G. Three times
C, F
135. Writing to lower-level cache on block eviction is characteristic of ____ cache. (75) A. Write allocate B. Write-through C. Write-back D. Read-Write E. Read-back F. Write back G. Write around
C, F
202. Data hungry programs (117) A. Also have high instruction cache miss rates B. Are common in the integer benchmark suites. C. Show higher cache miss rates than other programs. D. Are characteristic of programs run on portable mobile devices E. Put heavy demand on L1 cache, but no on L2 or L3. F. Can still have low instruction cache miss rates. G. Don't show higher cache miss rates than other programs.
C, F
289. The Cortex A8 processor has ____ pipeline stages (233) A. 20 B. 8 C. Thirteen D. Seven E. 4 F. 13 G. Five
C, F
111. A disk system is composed of a power supply and an array of disks. The more reliable the power supply (49) A. The cheaper the system becomes to operate. B. The less the reliability depends on the disks C. The more the reliability depends on the disks D. The higher its output voltage E. The less reliable the disks F. The more reliability becomes an issue. G. The less improvement it deserves
C, G
119. Fault Detection (57) A. Is usually not implemented in hardware. B. Relies on complicated logic and circuitry. C. Must be coupled with error correction to maintain reliability. D. Can lower clock frequency. E. Ultimately consumes less power. F. Raises reliability. G. Can lower availability.
C, G
167. Prefetching can be done by (92) A. Both the CPU and the cache controller B. Only one cache bank at a time C. Both the compiler and the cache controller D. The programmer and the compiler E. Both instructions and data F. The hardware architect and the programmer G. Both the cache controller and the compiler
C, G
183. As a cache for the page table, the Translation Lookaside Buffer leverages (107) A. Special CPU instructions B. DRAM density C. Temporal locality D. Optimum data layout E. Disk buffers F. SRAM speed G. Spatial locality
C, G
186. Besides improving memory and process protection, Virtual Machines can (108) A. Keep power costs down B. Help programmers use less memory C. Manage software and hardware D. Optimize program execution E. Help programs run faster F. Nearly triple the speed of user programs. G. Efficiently manage large numbers of hardware peripherals
C, G
187. When a virtual machine is running, hardware is under direct control of (109) A. The user B. The operating system C. The Virtual Machine Monitor D. The operating system's kernel E. The I/O subsystem F. The disk manager G. The hypervisor
C, G
193. At what privilege level does a guest OS run on a Virtual Machine? (111) A. Level 2 B. The bottom level C. Level One D. Level 3 E. Level 0 F. The top level G. Level 1
C, G
201. What is true of L1 I-cache and D-cache miss rates for the Cortex A-8? (116) A. SPEC2000 is a fair representation of the demands placed on I- and D-cache. B. L1 and L2 miss rates are nearly the same for all applications. C. Data miss rates are much larger than instruction miss rates. D. The miss rates are nearly equal. E. In general, a unified cache scheme would be better F. The instruction miss rate varies by aplication, the data miss rate does not. G. Instruction miss rates are near zero.
C, G
225. A 4096 entry branch prediction table could be indexed by (163) A. The state of a 2-bit predictor and 10 branch instruction bits B. A 10-bit predictor and a 2-bit predictor C. The bottom 6 bits of an instruction address and the results of the last six program branches D. The bottom 12 bits of the branch target address E. The state of a 1-bit predictor and 13 branch instruction bits F. A 12-bit predictor G. The bottom 12 bits of an instruction address
C, G
29. Task-level and request-level parallelism are similar in that they (9) A. The programs cannot contain branches. B. Involve programs whose instructions can be pipelined C. Do the same task with different data. D. Data require,emts are large. E. Perform different instructions on similar data F. Require interaction at the thread level G. Describe tasks which can be done in isolation from each other
C, G
293. The Intel Core i7 instruction handling architecture features (238) A. Unified L1 cache B. No exception handling. C. Reservation stations and reorder buffers D. A shallow integer pipeline E. Integer arithmetic only F. Fixed-length instructions. G. Tomasulo-like scheduling
C, G
74. Which can significantly affect chip yield? (30) A. Size of the photo mask B. Thoroughness of the testing C. Die size D. The number of manufacturing steps E. feature size F. Age of the silicon G. Imperfections in the wafer
C, G
96. To overcome the danger of placing too many eggs in one benchmark basket, what is used instead? (38) A. Independent validation and verification B. Uniform test protocol C. Benchmark suites D. A single universal application E. Standardized tests F. Performance based on the idle operating system. G. A combination of representative programs
C, G
188. If a virtual machine is running on a processor with only user and kernel modes, an operating system runs as a(n) (109) A. Privileged process B. Virtual Machine monitor C. Hypervisor D. Supervisor E. User F. Kernel process G. Normal user process
E, G
163. Reordering instructions and memory references to leverage cache parameters is the job of (88) A. The instruction set architecture B. Branch prediction C. The hardware architect D. Compiler optimizations E. The compiler F. Multiple issue architectures G. The CPU
D, E
174. Memory space and management was the reason for the first virtual memory systems. Recently, virtual memory has become important because of (105) A. The need for greener server farms B. Significant increases is memory capacity. C. The dot-com crash of 2000 D. Secure computing efforts. E. Security F. Hitting the power wall G. The rise of virtual reality.
D, E
184. Virtual Machines are managed via a(n) (108) A. Page table B. Supervisor C. Display monitor D. Virtual Machine Monitor E. Hypervisor F. Operating system kernel G. Translation Lookaside Buffer
D, E
190. The VMM's challenge is (110) A. Managing I/O B. Performance C. Isolating user processes D. Intercepting OS calls to hardware E. Making the operating system think it's in charge F. Keeping its memory footprint small G. Keeping users happy
D, E
220. Which best describes loop unrolling? (157) A. Set the loop variable explicitly for each iteration rather than incrementing it. B. Manually determine the outcome of the loop and code that rather than the method to obtain the outcome. C. Only execute instructions that make a difference in the outcome. D. Exposing parallelism in a series of repeated instructions. E. Write out the successive instructions for a loop, avoiding loop controls and index increments. F. Use vector instructions rather than scalar instructions to perform iterative tasks. G. Remove branches from groups of instructions.
D, E
203. The Intel Core i7 processor typically (118) A. Uses a low clock rate to keep the processor cool. B. Has a unified cache. C. Uses only two levels of cache, L1 and L2. D. Has separate data and instruction cache. E. Has more physical address bits than virtual address bits. F. Has four cores. G. Executes one instruction at a time.
D, F
274. Which of the following is not a property of a perfect processor? (214) A. Infinite main memory. B. Infinitely large cache. C. Inerrant branch prediction. D. Infinite power. E. perfect return prediction. F. Supply voltage < 1.0 volts. G. Perfect hazard detection.
D, F
13. Which of the following is not a new class of application enabled by high-performing processors? (4) A. Google Earth. B. Streaming video. C. Software as a Service. D. Financial management and payroll software. E. Speech-to-text applications. F. Cloud-based document storage. G. Office suites like Microsoft Office.
D, G
178. What is a page size in use today? (106) A. 256 bytes B. One megabyte C. 256 kilobytes D. Eight kilobytes E. One kilobyte F. Two kilobyes G. Four kilobytes
D, G
229. A branch prediction table has 4096 entries. How many lower address bits form the index into the branch prediction table? (165) A. 8 if there are also 8 global bistory bits. B. 4 if there are no global history bites. C. 24 D. 12 if there are no global history bits. E. 20 F. 16 G. 6 if there are 6 global history bits.
D, G
261. What does a branch target buffer do? (203) A. Predicts the next branch. B. Keeps branch targets from being affected by running code. C. Holds data that tells whether a branch will be taken or not. D. Provides a speculative jump-to location for branch instructions E. Tracks the global branch history. F. Allows speculation to occur across multiple branches. G. Contains a pre-calculated target address.
D, G
267. Having more physical registers than architecturally visible registers is useful in (209) A. Static branch prediction. B. Branch prediction C. Cache control D. Register renaming E. Virtual memory address transation. F. Floating point exception handling G. Use of reservation stations.
D, G
282. Which is a type of threading used in today's processors (225) A. Warp driven threading. B. Medium-grained multi threading. C. Woven multithreading. D. Simultaneous multi threading. E. Cross-thread multithreading. F. Coarse-grained multi threading. G. Fine-grained multi threading.
D, G
288. Experiments on multithreaded processors showed (230) A. Multithreaded applications showed performance gains similar to single-threaded applications B. Energy efficiency was markedly higher C. Multithreading was not a good idea D. That performance gains were modest because of the lack of parallelism in applications E. Cache performance was not a problem F. There was a significant boost to performance G. Some applications showed almost no increase in performance under multithreading
D, G
179. What two things must a processor do to allow virtualization? (106) A. Ensure disk accesses don't take too long, and guard against page faults. B. Have special VM instructions and do not allow the guest operating system to interact with the virtual machine manager. C. Hide the translation look aside buffer and do not allow the user to write to memory D. Have a protected operating mode, have secure logins for the system administrator E. Have a protected operating mode, allow some read-only access to OS-level data F. Have privileged instructions used only by the VM manager. have a way to isolate memory of different processes. G. Keep different processors from accessing the same data, do not allow the user to make operating system calls
E, F
198. Which best describes the Cortex A-8 cache scheme? (115) A. Data lookup is actually faster in L2 than L1. B. The number of virtual address lines in L1 and L2 are different. C. It uses the standard 4KB page size. D. More data is stored in L2 than L2. E. L1 is virtually indexed and L2 is physically indexed. F. The L1 index is based on the virtual address rather than the physical. G. THe L1 cache tag is larger than the L2 cache tag.
E, F
217. A name dependency can be efficiently resolved by (152) A. Inserting a stall. B. Swapping out the process. C. Exception handling. D. Not using names. E. Register renaming F. Having extra registers available. G. Forwarding.
E, F
218. Data hazards can exist when (153) A. The memory clock is too slow B. A processor executes only one instruction at a time C. A process cannot be parallelized D. The memory clock is too fast E. An instruction writes over a value which a subsequent instruction needs F. Instructions write values to memory in a different order than intended G. There are not enough registers to store data needed by the CPU
E, F
247. In order to allow multiple completions per clock cycle (185) A. The reorder buffer must have more entries B. The clock must run more slowly C. More instructions must be awaiting execution D. The clock must run faster E. There must be room for the results on the common data bus F. The common data bus must be wider G. More reservation stations are required
E, F
104. A key to high performance is (44) A. Memory speed B. A fast computer C. Availability D. Clock speed E. Parallelism F. Reliability G. Doing multiple tasks at the same time
E, G
122. Which is a correct ordering of memory hierarchy? (72) A. L2, L1, Main Memory, Disk B. Disk, L1, L2, L3 C. CPU, L3, L2, Main Memory D. CPU, L3, L2, L1 E. Registers, L1, L2, L3 F. Registers, CPU, L1, L2 G. CPU, L1, L2, Main Memory
E, G
142. Access times generally increase as (77) A. programs run faster. B. Main memory size increases C. cache size decreases D. programs more optimally use cache. E. cache size increases. F. block size decreases G. cache associativity increases.
E, G
164. In hardware prefetching (91) A. The requested data is sent to the CPU as soon as it is read into cache B. The cache controller guesses which data will be read next C. The write buffer is checked for recently evicted data D. The requested data word is read first, followed by the rest of the block E. Cache reads two blocks of main memory instead of one F. Multiple blocks in a set can be accessed at once G. Spatial locality is expanded by reading a subsequent block
E, G
215. Which of the following is a disadvantage of the use of instruction level parallelism (ILP? (150) A. The need for very low memory latency to feed the processor B. Power efficiency. C. The difference in minimum execution time of various stages in the pipeline D. The fact that most of the consumer market has no understanding of how ILP operates. E. The possibility of data hazards in multiple instructions in the CPU at the same time F. Branch predictors aren't very accurate. G. Not all programs have available parallelism.
E, G
223. Branch prediction works if (162) A. Branch decisions depend on data B. Loop unrolling is used C. Branch targets are in the same area of memory D. There are a lot of branches in a program E. It is right most of the time F. There are few branches in a program G. Penalties for being wrong are small
E, G
266. If register renaming is used in place of a reorder buffer, how are values committed? (209) A. Register renaming cannot replace the reorder buffer B. They are written directly from the Common Data Bus to the register C. The processor writes the value, but then overwrites it if it turns out to be incorrect D. The processor waits until all preceding instructions have executed, then writes the value to the appropriate register E. The register "receiving" the value is mapped to the physical register F. Use of register renaming only works if commit order is the same as execution order G. The register is mapped to an architecturally visible register
E, G
42. MIPS uses 32-bit registers. In the R-type instruction format, there is a shamt field representing the shift amount for shift instructions. How many bits wide is this field? (14) A. 32 B. Four C. Two D. 6 E. Five F. 16 G. 5
E, G
57. The biggest challenge facing computer designers today is (21) A. Size B. Speed C. Security breaches D. Memory E. Power F. Market volatility G. Heat dissipation
E, G
216. If an instruction should not write a value into a register before a preceding instruction uses a value in that register, what describes the situation? (152) A. Timing hazard B. Register hazard. C. Data fault. D. Data hazard E. Cache coherency F. Antidependence
F
15. The 52%-per-year performance increase from 1984 to 2003 was largely due to (4) A. Changes in benchmark tests B. Increasing power requirements C. The number of potential users D. Multiple cores E. Increasing clock rate F. Moore's Law G. Advances in technology
F, G
227. What is true of a two-bit branch predictor? (164) A. It combines results of two one-bit predictors. B. It selects the most accurate of two predictors. C. It takes less space compared to a 1-bit predictor. D. It takes one wrong guess to change the guess of the predictor. E. It contains a "don't know" state. F. It has four possible states. G. It takes two wrong guesses to change the guess of the predictor
F, G
257. Which is an effective way of achieving a CPI of 1/2? (197) A. Doubling the clock fequency B. Slowing the clock down so that more instructions may be executed in a cycle. C. Using a VLIW instruction set. D. Doubling the number of stages in the pipeline. E. Have two reservation stations per functional unit. F. Issuing two instructions at the beginning of each clock cycle. G. Issuing one instruction every half clock cycle.
F, G
26. A primary requirement for warehouse scale computing installations are (8) A. Weight B. Reliability C. Availability D. Size E. Consistency F. Power consumption G. Price-performance
F, G
278. The strength of hardware speculation is that it (221) A. Doesn't require as much power as software speculation B. Can accurately use history to predict the future C. Has visibility into what the programmer intends D. Uses logic which cannot be changed E. Is much faster than software speculation F. is aware of what currently is happening in the processor G. is based on the actual run-time conditions
F, G
281. What happens in Simultaneous multhithreading? (225) A. Instructions from a thread a re executed as a block until the next thread is scheduled B. Multiple instructions can be issued in a single clock cycle C. Multiple threads make superscalar design unnecessary D. The processor can switch threads every cycle E. Power consumption is lowest F. Instructions from multiple threads are executed in the same cycle G. Processor functional units are more effectively used than with other forms of multithreading
F, G
4. What factor hasn't contributed to the predominant role of computers today? (2) A. Progress in technology B. Use of embedded processors in cars and phones C. The world-wide web D. Exponentially increasing market E. Competitive edge resulting from uses of computation F. Sharp rise in enrollment at colleges and universities G. Use of exotic manufacturing materials
F, G
62. Which is a factor in computing the energy use of a processor? (23) A. Active silicon area B. Current C. Clock speed D. Number of power/ground pins E. Wattage F. Capacitive load G. Voltage
F, G
81. In order to determine if a device is operating correctly, we need (33) A. A user's manual B. A logic analyzer C. A qualified technician D. A parts book E. Two machines F. Service level objectives G. A service level agreement
F, G
86. If you run 1000 disks at the same time until one of them fails, the total time all the disks ran until the first failure is called (34) A. Service Time B. Failures in Time (FIT) C. Mean Time To Repair (MTTR) D. Mean Time Before Repair E. Mean Time between Failures (MTBF) F. MTTF G. Mean Time To Fail
F, G
88. Which statement is true? (34) A. MTTF = MTBF - MTTR B. FIT = 1 / MTTR C. MTTF = 1 - MTTR D. MTTR = 1/MTTF E. MTTR = MTTF + MTBR F. Availability = MTTF/MTBF G. MTBF = MTTR + MTTF
F, G
95. The best choice of benchmarks to measure performance is (37) A. Synthetic benchmarks B. Toy programs C. Kernels (key pieces of real applications) D. Simulations E. Manufacturers' test programs F. Real applications G. Programs you would actually run
F, G
97. What are the two broad classes of desktop benchmarks? (38) A. normalized and denormalized B. Internal and external C. Capacitive and inductive D. Accurate and not-accurate E. representative and non-representative F. processor-intensive and graphics-intensive G. Graphics- and processor-oriented
F, G