CEA Chapter 12, CEA - UNIT 10, CEA, CEA Chapter 1, CEA Chapter 2, CEA Chapter 3, CEA Chapter 4, CEA Chapter 5, CEA Chapter 6, CEA Chapter 7, CEA Chapter 8, CEA Chapter 9, CEA Chapter 13, CEA Chapter 11, CEA Chapter 14, CEA Chapter 15, CEA Chapter 16

¡Supera tus tareas y exámenes ahora con Quizwiz!

12 Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained. a. TRUE b. FALSE

12 Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time. a. lane b. path c. line d. bus

11 With multithreading the instruction stream is divided into several smaller streams, known as threads, such that the threads can be executed in parallel. a. TRUE b. FALSE

11 _________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on. a. Chaining b. Rollover c. Passive standby d. Pipelining

11 __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. a. DDR2 b. RDRAM c. CDRAM d. DDR3

11 __________ is the standardized scheme for multiple-disk database design. a. RAID b. CAV c. CLV d. SSD

12 A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache. a. TRUE b. FALSE

12 Actual floating-point representations include a special bit pattern to designate zero. a. TRUE b. FALSE

6 A(n) _________ is generated by some condition that occurs as a result of an instruction execution. a. timer interrupt b. I/O interrupt c. program interrupt d. hardware failure interrupt

6 Hardware-based solutions are generally referred to as cache coherence _______. a. clusters b. streams c. protocols d. vectors

6 Numbers in the binary system are represented to the _________. a. base 0 b. base 1 c. base 2 d. base 10

6 The ________ is connected to the data lines of the system bus. a. MAR b. PC c. MBR d. IR

6 The _________ contains a word of data to be written to memory or the word most recently read. a. MAR b. PC c. MBR d. IR

6 __________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the final product. a. Addition b. Subtraction c. Multiplication d. Division

7 Indexing performed after the indirection is __________. a. relative addressing b. autoindexing c. postindexing d. preindexing

7 Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses. a. in-order issue b. resource conflict c. antidependency d. out-of-order completion

7 The terms __________ relate to the relative width of microinstructions. a. packed/unpacked b. hard/soft c. horizontal/vertical d. direct/indirect

7 The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________. a. general b. ordinal c. integer d. packed BCD

7 _______ applications that can benefit directly from multicore resources include application servers such as Sun's Java Application Server, BEA's Weblogic, IBM's Websphere, and the open-source Tomcat application server. a. Multi-instance b. Multi-process c. Java d. Threaded

8 A ________ is a dispatchable unit of work within a process that includes a processor context and its own data area for a stack. a. process b. process switch c. thread d. thread switch

8 The instruction location immediately following the delayed branch is referred to as the ________. a. delay load b. delay file c. delay slot d. delay register

8 When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________. a. multiple sided b. substrate c. double sided d. all of the above

8 ________ is implemented with combinational circuits. a. Nano memory b. Random access memory c. Read only memory d. No memory

8 ________ is when the DMA module must force the processor to suspend operation temporarily. a. Interrupt b. Thunderbolt c. Cycle stealing d. Lock down

9 A line includes a _________ that identifies which particular block is currently being stored. a. cache b. hit c. tag d. locality

9 The ________ scheduler is also known as the dispatcher. a. long-term b. medium-term c. short-term d. I/O

9 The groupings of micro-operations must follow which rule? a. a sequence of events does not need to be followed b. use read to and write from the same register in one time unit c. conflicts must be avoided d. all of the above

12 For the control unit to perform its function it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system. a. TRUE b. FALSE

12 In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture. a. TRUE b. FALSE

12 Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip. a. TRUE b. FALSE

12 Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed. a. TRUE b. FALSE

12 It is extremely easy to convert between binary and hexadecimal notation. a. TRUE b. FALSE

12 It is important to design compact, time-efficient techniques for microinstruction branching. a. TRUE b. FALSE

12 Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide. a. TRUE b. FALSE

12 The _________ allows multiple levels of nested calls or interrupts and it can be used to support branching and looping. a. stack b. register c. counter d. firmware

12 The hierarchical nature of complex systems is essential to both their design and their description. a. TRUE b. FALSE

12 The memory transfer rate has not kept up with increases in processor speed. a. TRUE b. FALSE

12 Virtual memory schemes make use of a special cache called a ________ for page table entries. a. TLB b. HLL c. VMC d. SPB

12 When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA). a. TRUE b. FALSE

12 Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions? a. data-processing instructions b. branch instructions c. load and store instructions d. extend instructions

12 With simple, one cycle instructions, there is little or no need for microcode. a. TRUE b. FALSE

12 With write back updates are made only in the cache. a. TRUE b. FALSE

13 A branch can be either forward or backward. a. TRUE b. FALSE

13 Almost all RISC instructions use simple register addressing. a. TRUE b. FALSE

13 An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations. a. TRUE b. FALSE

13 Another term for "base" is __________. a. radix b. integer c. position d. digit

13 Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. a. TRUE b. FALSE

13 Both clusters and symmetric multiprocessors provide a configuration with multiple processors to support high-demand applications. a. TRUE b. FALSE

13 Both the structure and functioning of a computer are, in essence, simple. a. TRUE b. FALSE

13 CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time. a. synchronous b. asynchronous c. clocked S-R d. timed ripple

13 Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components. a. TRUE b. FALSE

13 Hexadecimal notation is more compact than binary notation. a. TRUE b. FALSE

13 It has become possible to have a cache on the same chip as the processor. a. TRUE b. FALSE

13 The Pentium II includes hardware for both segmentation and paging. a. TRUE b. FALSE

13 The R4000 can have as many as _______ instructions in the pipeline at the same time. a. 8 b. 10 c. 5 d. 3

13 The SSDs now on the market use a type of semiconductor memory referred to as flash memory. a. TRUE b. FALSE

13 The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. a. transaction layer b. root layer c. configuration layer d. transport layer

13 The __________ byte consists of three fields: the Scale field, the Index field and the Base field. a. SIB b. VAX c. PDP-11 d. ModR/M

13 The control unit is the engine that runs the entire computer. a. TRUE b. FALSE

13 The degree of packing relates to the degree of identification between a given control task and specific microinstruction bits. a. TRUE b. FALSE

13 The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers. a. TRUE b. FALSE

13 The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution. a. TRUE b. FALSE

13 The thermal management unit monitors digital sensors for high-accuracy die temperature measurements. a. TRUE b. FALSE

13 Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz. a. 200 to 600 b. 400 to 1066 c. 600 to 1400 d. 800 to 1600

13 With _________ the virtual address is the same as the physical address. a. unsegmented unpaged memory b. unsegmented paged memory c. segmented unpaged memory d. segmented paged memory

13 _________ are included in IEEE 754 to handle cases of exponent underflow. a. Subnormal numbers b. Guard bits c. Normal numbers d. Radix points

14 A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. a. target channel adapter b. InfiniBand switch c. host channel adapter d. subnet

14 A computer must be able to process, store, move, and control data. a. TRUE b. FALSE

14 ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer. a. TRUE b. FALSE

14 All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions. a. TRUE b. FALSE

14 Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs. a. TRUE b. FALSE

14 In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory. a. miss b. hit c. line d. tag

14 RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations. a. TRUE b. FALSE

14 The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory. a. migratory lines b. DDI c. VFP unit d. IPIs

14 The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit. a. excitation b. Kenough c. J-K flip-flop d. FPGA

14 The objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system. a. TRUE b. FALSE

14 The prefetch buffer is a memory cache located on the RAM chip. a. TRUE b. FALSE

14 The principal price to pay for variable-length instructions is an increase in the complexity of the processor. a. TRUE b. FALSE

14 The use of common data paths simplifies the interconnection layout and the control of the processor. a. TRUE b. FALSE

14 While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur. a. TRUE b. FALSE

14 _________ is a subfield that is used to indicate a conditional branch. a. ZERION b. S2-S0 c. SELDR d. OSEL

15 A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet. a. TRUE b. FALSE

15 A multicore computer combines two or more processors on a single piece of silicon. a. TRUE b. FALSE

15 A register is a digital circuit used within the CPU to store one or more bits of data. a. TRUE b. FALSE

15 Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes. a. TRUE b. FALSE

15 Flash memory becomes unusable after a certain number of writes. a. TRUE b. FALSE

15 One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode. a. TRUE b. FALSE

15 One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent. a. TRUE b. FALSE

15 The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems. a. TRUE b. FALSE

15 The OS usually runs in ________. a. supervisor mode b. abort mode c. undefined mode d. fast interrupt mode

15 The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage. a. write back b. tag check c. data cache d. instruction execute

15 The TI 8800 Software Development Board is a microprogrammable 32-bit computer card that fits into an IBM PC-compatible host computer. a. TRUE b. FALSE

15 The __________ module handles multiple levels of interrupt signals. a. interrupt control b. incrementer address latch c. serial I/O control d. decrementer address latch

15 The areas between pits are called _________. a. lands b. sectors c. cylinders d. strips

15 The exception modes have full access to system resources and can change modes freely. a. TRUE b. FALSE

15 The focus of MMX technology is multimedia programming. a. TRUE b. FALSE

15 The key to the design of a supercomputer or array processor is to recognize that the main task is to perform arithmetic operations on arrays or vectors of floating-point numbers. a. TRUE b. FALSE

15 Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance. a. TRUE b. FALSE

15 With ________ instructions are simultaneously issued from multiple threads to the execution units of a superscalar processor. a. SMT b. single-threaded scalar c. coarse-grained multithreading d. chip multiprocessing

18 Architectural attributes include __________ . a. I/O mechanisms b. control signals c. interfaces d. memory technology used

18 The ENIAC used __________. a. vacuum tubes b. integrated circuits c. IAS d. transistors

19 The ENIAC is an example of a _________ generation computer. a. first b. second c. third d. fourth

2 A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external. a. TRUE b. FALSE

2 An I/O module must recognize one unique address for each peripheral it controls. a. TRUE b. FALSE

2 Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit. a. TRUE b. FALSE

2 Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS. a. utility b. multitasking c. JCL d. logical address

2 In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations. a. TRUE b. FALSE

2 John Mauchly and John Eckert designed the ENIAC. a. TRUE b. FALSE

2 One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly. a. RAM b. ROM c. EPROM d. EEPROM

2 One technique for implementing a control unit is referred to as hardwired implementation, in which the control unit is a combinatorial circuit. a. TRUE b. FALSE

2 Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program. a. TRUE b. FALSE

2 The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture. a. HLL b. RISC c. CISC d. all of the above

2 The ________ controls the movement of data and instructions into and out of the processor. a. control unit b. ALU c. shifter d. branch

2 The basic function of a computer is to execute programs. a. TRUE b. FALSE

2 The most common means of computer/user interaction is a __________. a. keyboard/monitor b. mouse/printer c. modem/printer d. monitor/printer

2 The operation to be performed is specified by a binary code known as the operation code. a. TRUE b. FALSE

2 The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture. a. TRUE b. FALSE

2 With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines. a. TRUE b. FALSE

20 It is a(n) _________ design issue whether a computer will have a multiply instruction. a. architectural b. memory c. elementary d. organizational

24 When data are moved over longer distances, to or from a remote device, the process is known as __________. a. data communications b. registering c. structuring d. data transport

25 The __________ defines the third generation of computers. a. integrated circuit b. vacuum tube c. transistor d. VLSI

26 The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. a. multicore b. GPU c. data channels d. MPC

28 A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. a. system interconnection b. CPU interconnection c. peripheral d. processor

3 A sequence of codes or instructions is called __________. a. software b. memory c. an interconnect d. a register

3 An attractive feature of an SMP is that the existence of multiple processors is transparent to the user. a. TRUE b. FALSE

3 In the absence of parentheses, the AND operation takes precedence over the OR operation. a. TRUE b. FALSE

3 Microprogramming became a popular technique for implementing the control unit of CISC processors. a. TRUE b. FALSE

3 Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________. a. sign extension b. range extension c. bit extension d. partial extension

3 Negative powers of 10 are used to represent the positions of the numbers for decimal fractions. a. TRUE b. FALSE

3 Program execution consists of repeating the process of instruction fetch and instruction execution. a. TRUE b. FALSE

3 RAM must be provided with a constant power supply. a. TRUE b. FALSE

3 The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field. a. TRUE b. FALSE

3 The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic. a. TRUE b. FALSE

3 The most important system program is the OS. a. TRUE b. FALSE

3 Vector and array processors fall into the ________ category of computer systems. a. SIMD b. SISD c. MISD d. MIMD

3 Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy. a. TRUE b. FALSE

3 __________ are the functional, or atomic, operations of a processor. a. Micro-operations b. Interrupts c. Subcycles d. All of the above

3 __________ has the advantage of large address space, however it has the disadvantage of multiple memory references. a. Indirect addressing b. Direct addressing c. Immediate addressing d. Stack addressing

30 One increment, or pulse, of the system clock is referred to as a _________. a. clock tick b. cycle time c. clock rate d. cycle speed

4 "Memory is organized into records and access must be made in a specific linear sequence" is a description of __________. a. sequential access b. direct access c. random access d. associative

4 A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals. a. gate b. decoder c. counter d. flip-flop

4 A number with both an integer and fractional part has digits raised to both positive and negative powers of 10. a. TRUE b. FALSE

6 Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity. a. TRUE b. FALSE

6 One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction. a. TRUE b. FALSE

6 Resources include: memories, caches, buses, and register-file ports. a. TRUE b. FALSE

6 Software cache coherence schemes attempt to avoid the need for additional hardware circuitry and logic by relying on the compiler and operating system to deal with the problem. a. TRUE b. FALSE

6 The execution of a program consists of the sequential execution of instructions. a. TRUE b. FALSE

6 The number of bits used to represent various data types is an example of an architectural attribute. a. TRUE b. FALSE

6 The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application. a. TRUE b. FALSE

6 The register file is on the same chip as the ALU and control unit. a. TRUE b. FALSE

6 There are 50 tens in the number 509. a. TRUE b. FALSE

6 With _________ the microchip is organized so that a section of memory cells are erased in a single action. a. flash memory b. SDRAM c. DRAM d. EEPROM

6 With a batch operating system the user does not have direct access to the processor. a. TRUE b. FALSE

6 _______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user. a. I/O b. Transfer c. Control d. Branch

6 ________ refers to the process of initiating instruction execution in the processor's functional units. a. Instruction issue b. In-order issue c. Out-of-order issue d. Procedural issue

7 A _________ is a special type of programming language used to provide instructions to the monitor. a. job control language b. multiprogram c. kernel d. utility

7 A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer. a. nonremovable b. movable-head c. double sided d. removable

7 A __________ is an instance of a program running on a computer. a. process b. process switch c. thread d. thread switch

7 A removable disk can be removed and replaced with another disk. a. TRUE b. FALSE

7 Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers. a. TRUE b. FALSE

7 Any Boolean function can be implemented in electronic form as a network of gates. a. TRUE b. FALSE

7 Both sequential access and direct access involve a shared read-write mechanism. a. TRUE b. FALSE

7 Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. a. TRUE b. FALSE

7 Database management systems and database applications are one area in which multicore systems can be used effectively. a. TRUE b. FALSE

7 Interfaces between the computer and peripherals is an example of an organizational attribute. a. TRUE b. FALSE

7 It is more difficult to write a firmware program than a software program. a. TRUE b. FALSE

7 Privileged instructions are certain instructions that are designated special and can be executed only by the monitor. a. TRUE b. FALSE

7 The ________ command is used to activate a peripheral and tell it what to do. a. control b. test c. read d. write

7 The ________ determines the opcode and the operand specifiers. a. decode instruction b. fetch operands c. calculate operands d. execute instruction

7 The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline. a. TRUE b. FALSE

7 The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9. a. TRUE b. FALSE

7 The disadvantage of the software poll is that it is time consuming. a. TRUE b. FALSE

7 The register file employs much shorter addresses than addresses for cache and memory. a. TRUE b. FALSE

7 ________ are used in digital circuits to control signal and data routing. a. Multiplexers b. Program counters c. Flip-flops d. Gates

8 A bus that connects major computer components (processor, memory, I/O) is called a __________. a. system bus b. address bus c. data bus d. control bus

8 A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________. a. disk cache b. latency c. virtual address d. miss

8 Computers are classified into generations based on the fundamental hardware technology employed. a. TRUE b. FALSE

8 Each micro-operation of the fetch cycle involves the movement of data into or out of a register. a. TRUE b. FALSE

8 Even if an individual application does not scale to take advantage of a large number of threads, it is still possible to gain from multicore architecture by running multiple instances of the application in parallel. a. TRUE b. FALSE

8 For the _________ mode, the operand is included in the instruction. a. immediate b. base c. register d. displacement

8 In a volatile memory, information decays naturally or is lost when electrical power is switched off. a. TRUE b. FALSE

8 In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. a. TRUE b. FALSE

8 Putting rendering on one processor, AI on another, and physics on another is an example of _________ threading. a. coarse b. multi-instance c. fine-grained d. hybrid

8 Reading a microinstruction from the control memory is the same as executing that microinstruction. a. TRUE b. FALSE

8 Semiconductor memory comes in packaged chips. a. TRUE b. FALSE

8 The _________ scheduler determines which programs are admitted to the system for processing. a. long-term b. medium-term c. short-term d. I/O

8 The binary string 110111100001 is equivalent to __________. a. DE116 b. C7816 c. FF6416 d. B8F16

8 The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly. a. TRUE b. FALSE

8 The instruction set is the programmer's means of controlling the processor. a. TRUE b. FALSE

8 The method of calculating the EA is the same for both base-register addressing and indexing. a. TRUE b. FALSE

8 The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion). a. TRUE b. FALSE

ROM

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. a. RAM b. SRAM c. ROM d. flash memory

nonremovable

A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer. a. nonremovable b. movable-head c. double sided d. removable

protocol

A __________ is the high-level set of rules for exchanging packets of data between devices. a. bus b. protocol c. packet d. QPI

hierarchical

A __________ system is a set of interrelated subsystems. a. secondary b. hierarchical c. complex d. functional

True

A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside. a. True b. False

True

A branch can be either forward or backward. a. True b. False

unconditional branch

A branch instruction in which the branch is always taken is _________. a. conditional branch b. unconditional branch c. jump d. bi-endian

system bus

A bus that connects major computer components (processor, memory, I/O) is called a __________. a. system bus b. address bus c. data bus d. control bus

False

A characteristic of ROM is that it is volatile. a. True b. False

True

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external. a. True b. False

False

A vacuum tube is a solid-state device made from silicon. a. True b. False

True

A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points. a. True b. False

high-level language

A(n) _________ expresses operations in a concise algebraic form using variables. a. opcode b. high-level language c. machine language d. register

hardware failure interrupt

A(n) _________ is generated by a failure such as power failure or memory parity error. a. I/O interrupt b. hardware failure interrupt c. timer interrupt d. program interrupt

program interrupt

A(n) _________ is generated by some condition that occurs as a result of an instruction execution. a. timer interrupt b. I/O interrupt c. program interrupt d. hardware failure interrupt

False

ARM architecture has yet to implement superscalar techniques in the instruction pipeline. a. True b. False

all of the above

ARM processors are designed to meet the needs of _________. a. embedded real-time systems b. application platforms c. secure applications d. all of the above

True

ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length. a. True b. False

True

ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer. a. True b. False

Actual floating-point representations include a special bit pattern to designate zero.

Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.

True

Addresses are a form of data. a. True b. False

gaps

Adjacent tracks are separated by _________. a. sectors b. gaps c. pits d. heads

True

All DRAMs require a refresh operation. a. True b. False

32-bit

All MIPS R series processor instructions are encoded in a single ________ word format. a. 4-bit b. 8-bit c. 16-bit d. 32-bit

All instructions in the ARM architecture are __________ bits long and follow a regular format. a. 8 b. 16 c. 32 d. 64

True

All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions. a. True b. False

True

Almost all RISC instructions use simple register addressing. a. True b. False

True

Although convenient for computers, the binary system is exceedingly cumbersome for human beings. a. True b. False

True

An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations. a. True b. False

peripheral

An I/O device is referred to as a __________. a. CPU b. control device c. peripheral d. register

False

An I/O module cannot exchange data directly with the processor. a. True b. False

True

An I/O module must recognize one unique address for each peripheral it controls. a. True b. False

I/O controller

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. a. I/O command b. I/O controller c. I/O channel d. I/O processor

I/O channel

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. a. I/O channel b. I/O command c. I/O controller d. device controller

An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes.

True

An error-correcting code enhances the reliability of the memory at the cost of added complexity. a. True b. False

True

An interrupt is a hardware-generated signal to the processor. a. True b. False

False

An interrupt is generated from software and it is provoked by the execution of an instruction. a. True b. False

13 The _________ is a 32-bit ALU with 64 registers that can be configured to operate as four 8-bit ALUs, two 16-bit ALUs, or a single 32-bit ALU. a. PDP-11 b. 8832 c. 3033 d. 8818

14 A DDR3 module transfers data at a clock rate of __________ MHz. a. 600 to 1200 b. 800 to 1600 c. 1000 to 2000 d. 1500 to 3000

14 A multipoint external interface provides a dedicated line between the I/O module and the external device. a. TRUE b. FALSE

14 A sequence of hexadecimal digits can be thought of as representing an integer in base 10. a. TRUE b. FALSE

14 ARM architecture has yet to implement superscalar techniques in the instruction pipeline. a. TRUE b. FALSE

22 A __________ system is a set of interrelated subsystems. a. secondary b. hierarchical c. complex d. functional

23 During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. a. execute cycle b. fetch cycle c. instruction cycle d. clock cycle

24 Second generation computers used __________. a. integrated circuits b. ransistors c. vacuum tubes d. large-scale integration

26 The __________ moves data between the computer and its external environment. a. data transport b. I/O c. register d. CPU interconnection

27 A common example of system interconnection is by means of a __________. a. register b. system bus c. data transport d. control device

28 The __________ measures the ability of a computer to complete a single task. a. clock speed b. speed metric c. execute cycle d. cycle time

3 Computer organization refers to attributes of a system visible to the programmer. a. TRUE b. FALSE

3 External memory is often equated with main memory. a. TRUE b. FALSE

3 For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module. a. access time b. unit of transfer c. capacity d. memory ratio

3 I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes. a. TRUE b. FALSE

3 In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure. a. TRUE b. FALSE

3 It is not necessary for the ALU to signal when overflow occurs. a. TRUE b. FALSE

3 Knowing the machine instruction set does not play a part in knowing the functions that the processor must perform. a. TRUE b. FALSE

3 The _________ contains the address of the next microinstruction to be read. a. control memory b. control address register c. control word d. control buffer register

3 The address of the next instruction to be fetched must be a real address, not a virtual address. a. TRUE b. FALSE

3 The major cost in the life cycle of a system is hardware. a. TRUE b. FALSE

3 The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables. a. TRUE b. FALSE

3 The unary operation _________ inverts the value of its operand. a. OR b. NOT c. NAND d. XOR

3 The width of a track is double that of the head. a. TRUE b. FALSE

3 ________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. a. General purpose b. Data c. Address d. Condition code

3 _________ is when multiple pipelines are constructed by replicating execution resources, enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided. a. Vectoring b. Superscalar c. Hybrid multithreading d. Pipelining

4 Changes in computer technology are finally slowing down. a. TRUE b. FALSE

4 In a _________, binary values are stored using traditional flip-flop logic-gate configurations. a. ROM b. SRAM c. DRAM d. RAM

4 Interrupts do not improve processing efficiency. a. TRUE b. FALSE

4 Logical functions are implemented by the interconnection of decoders. a. TRUE b. FALSE

4 One way to control power density is to use more of the chip area for ________. a. multicore b. cache memory c. silicon d. resistors

4 Overflow can only occur if there is a carry. a. TRUE b. FALSE

4 SMPs, clusters, and NUMA systems fit into the ________ category of computer systems. a. SISD b. MIMD c. SIMD d. MISD

4 The ABI is the boundary between hardware and software. a. TRUE b. FALSE

4 The demand on power requirements has not grown as chip density and clock frequency have risen. a. TRUE b. FALSE

4 The main drawback of the bus organization is reliability. a. TRUE b. FALSE

4 To implement a control unit as an interconnection of basic logic elements is a very simple task. a. TRUE b. FALSE

4 __________ are bits set by the processor hardware as the result of operations. a. MIPS b. Condition codes c. Stacks d. PSWs

5 A high-level language expresses operations in a basic form involving the movement of data to or from registers. a. TRUE b. FALSE

5 A(n) _________ is generated by a failure such as power failure or memory parity error. a. I/O interrupt b. hardware failure interrupt c. timer interrupt d. program interrupt

5 An I/O module cannot exchange data directly with the processor. a. TRUE b. FALSE

5 An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. a. I/O command b. I/O controller c. I/O channel d. I/O processor

5 As chip transistor density has increased, the percentage of chip area devoted to memory has decreased. a. TRUE b. FALSE

5 Cache is not a form of internal memory. a. TRUE b. FALSE

5 In any number, the rightmost digit is referred to as the most significant digit. a. TRUE b. FALSE

5 In the number 3109, the 9 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

5 Procedure calls and returns are not important aspects of HLL programs. a. TRUE b. FALSE

5 The _________ is connected to the address lines of the system bus. a. MBR b. MAR c. PC d. IR

5 The allocation of control information between registers and memory are not considered to be a key design issue. a. TRUE b. FALSE

5 The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed. a. resource dependency b. procedural dependency c. output dependency d. true data dependency

5 The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program. a. TRUE b. FALSE

5 With isolated I/O there is a single address space for memory locations and I/O devices. a. TRUE b. FALSE

5 __________ has the advantage of flexibility, but the disadvantage of complexity. a. Stack addressing b. Displacement addressing c. Direct addressing d. Register addressing

6 A _________ system works only one program at a time. a. batch b. uniprogramming c. kernel d. privileged instruction

6 A key characteristic of a bus is that it is not a shared transmission medium. a. TRUE b. FALSE

6 For more than four variables an alternative approach is a tabular technique referred to as the _________ method. a. DeMorgan b. Quine-McCluskey c. Karnaugh map d. Boole-Shannon

6 It is easier to design in hardware than in firmware. a. TRUE b. FALSE

6 Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values. a. TRUE b. FALSE

6 Register indirect addressing uses the same number of memory references as indirect addressing. a. TRUE b. FALSE

6 The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks. a. SSD b. CAV c. ROM d. CLV

6 The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector. a. TRUE b. FALSE

6 The unit of transfer must equal a word or an addressable unit. a. TRUE b. FALSE

7 A ________ instruction can be used to account for data and branch delays. a. SUB b. NOOP c. JUMP d. all of the above

7 A vacuum tube is a solid-state device made from silicon. a. TRUE b. FALSE

7 Although considered obsolete, the term _________ is sometimes used instead of significand. a. minuend b. mantissa c. base d. subtrahend

7 Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. a. TRUE b. FALSE

7 Memory references are faster than register references. a. TRUE b. FALSE

7 Snoopy protocols are not suitable for a bus-based multiprocessor. a. TRUE b. FALSE

7 The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other. a. TRUE b. FALSE

7 The ________ consists of the access time plus any additional time required before a second access can commence. a. latency b. memory cycle time c. direct access d. transfer rate

7 The ________ holds the address of the next instruction to be fetched. a. IR b. PC c. MAR d. MBR

7 The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device. a. TRUE b. FALSE

7 Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing. a. TRUE b. FALSE

7 __________ can be caused by harsh environmental abuse, manufacturing defects, and wear. a. SEC errors b. Hard errors c. Syndrome errors d. Soft errors

8 A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form. a. TRUE b. FALSE

8 A control hazard occurs when two or more instructions that are already in the pipeline need the same resource. a. TRUE b. FALSE

8 A number cannot be converted from binary notation to decimal notation. a. TRUE b. FALSE

8 Booth's algorithm performs more additions and subtractions than a straightforward algorithm. a. TRUE b. FALSE

8 Historically the distinction between architecture and organization has not been an important one. a. TRUE b. FALSE

8 The most fundamental type of machine instruction is the _________ instruction. a. conversion b. data transfer c. arithmetic d. logical

8 Uniprogramming is the central theme of modern operating systems. a. TRUE b. FALSE

8 With a daisy chain the processor just picks the interrupt line with the highest priority. a. TRUE b. FALSE

8 With a write-update protocol there can be multiple readers but only one writer at a time. a. TRUE b. FALSE

9 A ________ hazard occurs when there is a conflict in the access of an operand location. a. resource b. data c. structural d. control

Binary 0101 is hexadecimal _________. a. 0 b. 5 c. A d. 10

False

Binary addition is exactly the same as Boolean algebra. a. True b. False

Booth's algorithm performs more additions and subtractions than a straightforward algorithm.

True

Both batch multiprogramming and time sharing use multiprogramming. a. True b. False

True

Both sequential access and direct access involve a shared read-write mechanism. a. True b. False

Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit.

True

Both the structure and functioning of a computer are, in essence, simple. a. True b. False

True

Bus arbitration makes use of vectored interrupts. a. True b. False

1 Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________. a. magnetic read and write mechanisms b. platters c. the glass substrate d. a solid state drive

1 The most common scheme in implementing the integer portion of the ALU is: a. sign-magnitude representation b. biased representation c. twos complement representation d. ones complement representation

1 The operand ________ yields true if and only if both of its operands are true. a. XOR b. OR c. AND d. NOT

1 __________ are a set of storage locations. a. Processors b. PSWs c. Registers d. Control units

10 Decimal "10" is __________ in binary. a. 1000 b. 10 c. 1010 d. 1

10 The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU. a. 16 b. 32 c. 64 d. 128

10 The data lines provide a path for moving data among system modules and are collectively called the _________. a. control bus b. address bus c. data bus d. system bus

10 ________ can send data to the processor twice per clock cycle. a. CDRAM b. SDRAM c. DDR-DRAM d. RDRAM

11 The ________ connects to the external bus, known as the Front Side Bus, which connects to main memory, I/O controllers, and other processor chips. a. L2 b. APIC c. bus interface d. all of the above

11 The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. a. cable b. application c. common transport d. physical

11 The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. a. dynamic branch b. loop table c. branch history table d. flag

11 The standard IBM 3033 control memory consists of ________ words. a. 2K b. 8K c. 4K d. 16K

11 When using the __________ technique all write operations made to main memory are made to the cache as well. a. write back b. LRU c. write through d. unified cache

12 Counters can be designated as _________. a. asynchronous b. synchronous c. both asynchronous and synchronous d. neither asynchronous or synchronous

12 Four bits is called a _________. a. radix point b. byte c. nibble d. binary digit

12 The ________ contains control fields, such as the vector count, that determine how many elements in the vector registers are to be processed. a. vector-mask register b. vector-activity count c. vector-status register d. vector-instruction register

12 The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer. a. PDP-1 b. PDP-8 c. PDP-11 d. PDP-10

12 ________ increases the prefetch buffer size to 8 bits. a. CDRAM b. RDRAM c. DDR3 d. all of the above

12 ________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles. a. In-order completion b. In-order issue c. Out-of-order completion d. Out-of-order issue

12 _________ formats extend a supported basic format by providing additional bits in the exponent and in the significand. a. Arithmetic b. Basic c. Extended precision d. Interchange

13 In the ARM architecture only _________ instructions access memory locations. a. data processing b. status register access c. load and store d. branch

5 individual blocks or records have a unique address based on physical location with __________. a. associative b. physical access c. direct access d. sequential access

True

Flash memory becomes unusable after a certain number of writes. a. True b. False

most significant digit

In the number 3109, the 3 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

least significant digit

In the number 3109, the 9 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

none of the above

In the number 472.156 the 2 is the _________. a. most significant digit b. radix point c. least significant digit d. none of the above

False

In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure. a. True b. False

True

One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode. a. True b. False

True

One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set. a. True b. False

RAM

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly. a. RAM b. ROM c. EPROM d. EEPROM

One drawback of sign-magnitude representation is that there are two representations of 0.

clock tick

One increment, or pulse, of the system clock is referred to as a _________. a. clock tick b. cycle time c. clock rate d. cycle speed

True

One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline. a. True b. False

One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.

True

One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction. a. True b. False

False

Our primary counting system is based on binary digits to represent numbers. a. True b. False

Overflow can only occur if there is a carry.

Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.

True

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program. a. True b. False

True

Privileged instructions are certain instructions that are designated special and can be executed only by the monitor. a. True b. False

False

Procedure calls and returns are not important aspects of HLL programs. a. True b. False

False

Procedures do not allow programming tasks to be subdivided into smaller units. a. True b. False

True

Program execution consists of repeating the process of instruction fetch and instruction execution. a. True b. False

QN=1 The most common scheme in implementing the integer portion of the ALU is: a. sign-magnitude representation b. biased representation c. twos complement representation d. ones complement representation

QN=10 Positive numbers less than 2-127 are called ________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow

QN=11 Positive numbers greater than (2 - 2-23) x 2-128 are called _________. a. negative underflow b. positive overflow c. positive underflow d. negative overflow

QN=12 _________ formats extend a supported basic format by providing additional bits in the exponent and in the significand. a. Arithmetic b. Basic c. Extended precision d. Interchange

QN=13 _________ are included in IEEE 754 to handle cases of exponent underflow. a. Subnormal numbers b. Guard bits c. Normal numbers d. Radix points

QN=14 __________ is when a positive exponent exceeds the maximum possible exponent value. a. Significand underflow b. Significand overflow c. Exponent overflow d. Exponent underflow

QN=15 __________ means that the number is too small to be represented and it may be reported as 0. a. Negative underflow b. Exponent underflow c. Positive underflow d. Significand underflow

QN=2 __________ representation is almost universally used as the processor representation for integers. a. Biased b. Twos compliment c. Sign-magnitude d. Decimal

QN=3 Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________. a. sign extension b. range extension c. bit extension d. partial extension

QN=4 In ________ representation the rule for forming the negation of an integer is to invert the sign bit. a. ones complement b. twos complement c. biased d. sign-magnitude

QN=5 ________ is when the result may be larger than can be held in the word size being used. a. Overflow b. Arithmetic shift c. Underflow d. Partial product

QN=6 __________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the final product. a. Addition b. Subtraction c. Multiplication d. Division

QN=7 Although considered obsolete, the term _________ is sometimes used instead of significand. a. minuend b. mantissa c. base d. subtrahend

QN=8 Negative numbers less than -(2 - 2-23) x 2 128 are called _________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow

QN=9 Negative numbers greater than 2-127 are called _________. a. negative overflow b. negative underflow c. positive overflow d. positive underflow

True

RAID is a set of physical disk drives viewed by the operating system as a single logical drive. a. True b. False

True

RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance. a. True b. False

RAID level ________ has the highest disk overhead of all RAID types. a. 0 b. 1 c. 3 d. 5

True

RAM must be provided with a constant power supply. a. True b. False

False

RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle. a. True b. False

fly-by

The 8237 DMA is known as a _________ DMA controller. a. command b. cycle stealing c. interrupt d. fly-by

False

The ABI is the boundary between hardware and software. a. True b. False

The ARM architecture supports _______ execution modes. a. 2 b. 8 c. 11 d. 7

decode instruction

The ________ determines the opcode and the operand specifiers. a. decode instruction b. fetch operands c. calculate operands d. execute instruction

buffer

The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible. a. flash memory b. Hamming code c. RamBus d. buffer

flip-flop

The ________ exists in one of two states and, in the absence of input, remains in that state. a. assert b. complex PLD c. decoder d. flip-flop

J-K

The ________ flip-flop has two inputs and all possible combinations of input values are valid. a. J-K b. D c. S-R d. clocked S-R

all of the above

The interconnection structure must support which transfer? a. memory to processor b. processor to memory c. I/O to or from memory d. all of the above

True

True data dependency is also called flow dependency or read after write (RAW) dependency. a. True b. False

False

Typically an instruction set will include both preindexing and postindexing. a. True b. False

architecture

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. a. organization b. specifics c. design d. architecture

False

Computer organization refers to attributes of a system visible to the programmer. a. True b. False

True

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. a. True b. False

rapid

Computer technology is changing at a __________ pace. a. slow b. slow to medium c. rapid d. non-existent

True

Computers are classified into generations based on the fundamental hardware technology employed. a. True b. False

True

Condition codes facilitate multiway branches. a. True b. False

15 __________ is a design principle employed in designing the PDP-10 instruction set. a. Orthogonality b. Completeness c. Direct addressing d. All of the above

17 Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. a. organization b. specifics c. design d. architecture

17 The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________. a. the Civil War b. the French-American War c. World War I d. World War II

2 The operation _________ yields true if either or both of its operands are true. a. NOT b. AND c. NAND d. OR

2 The principal advantage of ___________ addressing is that it is a very simple form of addressing. a. displacement b. register c. stack d. direct

2 The von Neumann architecture is based on which concept? a. data and instructions are stored in a single read-write memory b. the contents of this memory are addressable by location c. execution occurs in a sequential fashion d. all of the above

21 It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. a. architectural b. memory c. mechanical d. organizational

21 The memory of the IAS consists of 1000 storage locations called __________. a. opcodes b. wafers c. VLSIs d. words

27 With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel. a. Core b. 8080 c. 80486 d. Pentium

29 ARM processors are designed to meet the needs of _________. a. embedded real-time systems b. application platforms c. secure applications d. all of the above

29 _________ provide storage internal to the CPU. a. Control units b. ALUs c. Main memory d. Registers

3 The _________ defines the repertoire of machine language instructions that a computer can follow. a. ABI b. API c. HLL d. ISA

3 Which of the following is a fundamental limitation to parallelism with which the system must cope? a. procedural dependency b. resource conflicts c. antidependency d. all of the above

3 Which of the following memory types are nonvolatile? a. erasable PROM b. programmable ROM c. flash memory d. all of the above

4 In ________ representation the rule for forming the negation of an integer is to invert the sign bit. a. ones complement b. twos complement c. biased d. sign-magnitude

4 In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size. a. 64 b. 128 c. 256 d. 512

4 The first commercial RISC product was _________. a. SPARC b. CISC c. VAX d. the Pyramid

5 The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls. a. JCL b. ISA c. ABI d. API

5 The _________ contains the address of an instruction to be fetched. a. instruction register b. memory address register c. memory buffer register d. program counter

5 Which of the following is a control unit input? a. IR b. ALU flags c. clock d. all of the above

5 Which of the following is a functionally complete set? a. AND, NOT b. NOR c. AND, OR, NOT d. all of the above

5 _________ instructions provide computational capabilities for processing number data. a. Boolean b. Logic c. Memory d. Arithmetic

6 For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. a. memory cycle time b. direct access c. transfer rate d. access time

6 In executing a microprogram the address of the next microinstruction to be executed is in which of the following categories? a. determined by instruction register b. branch c. next sequential address d. all of the above

6 Oracle database, SAP, and PeopleSoft are examples of ________ applications. a. Java b. multithreaded native c. multi-instance d. multi-process

6 The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. a. control b. test c. read d. write

6 Which stage is required for load and store operations? a. I b. E c. D d. all of the above

7 Hexadecimal has a base of _________. a. 2 b. 8 c. 10 d. 16

7 The interconnection structure must support which transfer? a. memory to processor b. processor to memory c. I/O to or from memory d. all of the above

8 Negative numbers less than -(2 - 2-23) x 2 128 are called _________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow

8 The _________ holds the last instruction fetched. a. PC b. MBR c. MAR d. IR

8 _________ is a pipeline hazard. a. Control b. Resource c. Data d. All of the above

9 Replicating the entire processor on a single chip with each processor handling separate threads is _________. a. interleaved multithreading b. blocked multithreading c. simultaneous multithreading d. chip multiprocessing

9 The 8237 DMA is known as a _________ DMA controller. a. command b. cycle stealing c. interrupt d. fly-by

9 The ________ exists in one of two states and, in the absence of input, remains in that state. a. assert b. complex PLD c. decoder d. flip-flop

9 The __________ are used to designate the source or destination of the data on the data bus. a. system lines b. data lines c. control lines d. address lines

9 The only form of addressing for branch instructions is _________ addressing. a. register b. relative c. base d. immediate

9 The set of all the tracks in the same relative position on the platter is referred to as a _________. a. floppy disk b. single-sided disk c. sector d. cylinder

False

DRAM is much costlier than SRAM. a. True b. False

sectors

Data are transferred to and from the disk in __________. a. tracks b. gaps c. sectors d. pits

Decimal "10" is _________ in hexadecimal. a. 1 b. A c. 0 d. FF

1010

Decimal "10" is __________ in binary. a. 1000 b. 0010 c. 1010 d. 0001

True

Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components. a. True b. False

direct access

individual blocks or records have a unique address based on physical location with __________. a. associative b. physical access c. direct access d. sequential access

True

With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. a. True b. False

False

With isolated I/O there is a single address space for memory locations and I/O devices. a. True b. False

True

With simple, one cycle instructions, there is little or no need for microcode. a. True b. False

Pentium

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel. a. Core b. 8080 c. 80486 d. Pentium

True

With write back updates are made only in the cache. a. True b. False

True

Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy. a. True b. False

I/O

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user. a. I/O b. Transfer c. Control d. Branch

Multiplexers

________ are used in digital circuits to control signal and data routing. a. Multiplexers b. Program counters c. Flip-flops d. Gates

DDR-DRAM

________ can send data to the processor twice per clock cycle. a. CDRAM b. SDRAM c. DDR-DRAM d. RDRAM

DDR3

________ increases the prefetch buffer size to 8 bits. a. CDRAM b. RDRAM c. DDR3 d. all of the above

RAID

__________ is the standardized scheme for multiple-disk database design. a. RAID b. CAV c. CLV d. SSD

Location

__________ refers to whether memory is internal or external to the computer. a. Location b. Access c. Hierarchy d. Tag

Hexadecimal has a base of _________. a. 2 b. 8 c. 10 d. 16

True

Hexadecimal notation is more compact than binary notation. a. True b. False

False

Hexadecimal notation is only used for representing integers. a. True b. False

False

Historically the distinction between architecture and organization has not been an important one. a. True b. False

False

I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes. a. True b. False

True

IBM's System/360 was the industry's first planned family of computers. a. True b. False

SRAM

In a _________, binary values are stored using traditional flip-flop logic-gate configurations. a. ROM b. SRAM c. DRAM d. RAM

False

In a system without virtual memory, the effective address is a virtual address or a register. a. True b. False

True

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations. a. True b. False

True

In a volatile memory, information decays naturally or is lost when electrical power is switched off. a. True b. False

False

In any number, the rightmost digit is referred to as the most significant digit. a. True b. False

True

In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture. a. True b. False

True

In general, a decoder has n inputs and 2n outputs. a. True b. False

True

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. a. True b. False

512

In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size. a. 64 b. 128 c. 256 d. 512

miss

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory. a. miss b. hit c. line d. tag

load and store

In the ARM architecture only _________ instructions access memory locations. a. data processing b. status register access c. load and store d. branch

True

In the absence of parentheses, the AND operation takes precedence over the OR operation. a. True b. False

False

Not all machine languages include numeric data types. a. True b. False

True

Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide. a. True b. False

True

Negative powers of 10 are used to represent the positions of the numbers for decimal fractions. a. True b. False

True

No single technology is optimal in satisfying the memory requirements for a computer system. a. True b. False

False

Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values. a. True b. False

11 Timing refers to the way in which events are coordinated on the bus. a. TRUE b. FALSE

uniprogramming

A _________ system works only one program at a time. a. batch b. uniprogramming c. kernel d. privileged instruction

True

"Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs. a. True b. False

sequential access

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________. a. sequential access b. direct access c. random access d. associative

1 A cycle is made up of a sequence of micro-operations. a. TRUE b. FALSE

1 A microprogram consists of a sequence of instructions in a microprogramming language. a. TRUE b. FALSE

1 A set of I/O modules is a key element of a computer system. a. TRUE b. FALSE

1 At a top level, a computer consists of CPU, memory, and I/O components. a. TRUE b. FALSE

1 Magnetic disks are the foundation of external memory on virtually all computer systems. a. TRUE b. FALSE

1 Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept. a. TRUE b. FALSE

1 No single technology is optimal in satisfying the memory requirements for a computer system. a. TRUE b. FALSE

1 One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set. a. TRUE b. FALSE

1 One drawback of sign-magnitude representation is that there are two representations of 0. a. TRUE b. FALSE

1 Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture. a. TRUE b. FALSE

1 Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common, example of parallel organization. a. TRUE b. FALSE

1 The basic element of a semiconductor memory is the memory cell. a. TRUE b. FALSE

1 The operation of the digital computer is based on the storage and processing of binary data. a. TRUE b. FALSE

1 The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle. a. TRUE b. FALSE

1 The processor needs to store instructions and data temporarily while an instruction is being executed. a. TRUE b. FALSE

1 The superscalar approach has now become the standard method for implementing high-performance microprocessors. a. TRUE b. FALSE

1 The term microprogram was first coined by __________ in the early 1950s. a. M.V. Wilkes b. D. Siewiorek c. M. Sebern d. S. Tucker

1 The value of the mode field determines which addressing mode is to be used. a. TRUE b. FALSE

1 There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer". a. TRUE b. FALSE

1 With _______, register banks are replicated so that multiple threads can share the use of pipeline resources. a. SMT b. pipelining c. scalar d. superscalar

1 __________ refers to whether memory is internal or external to the computer. a. Location b. Access c. Hierarchy d. Tag

10 A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. a. loop buffer b. delayed branch c. multiple stream d. branch prediction

10 A number of chips can be grouped together to form a memory bank. a. TRUE b. FALSE

10 A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points. a. TRUE b. FALSE

10 An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes. a. TRUE b. FALSE

10 An interrupt is a hardware-generated signal to the processor. a. TRUE b. FALSE

10 Positive numbers less than 2-127 are called ________. a. positive underflow b. positive overflow c. negative underflow d. negative overflow

10 RAID is a set of physical disk drives viewed by the operating system as a single logical drive. a. TRUE b. FALSE

10 The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches. a. TRUE b. FALSE

10 The _______ designates the state of the processor in terms of which portion of the cycle it is in. a. ICC b. BSA c. ALE d. ISC

10 The ________ flip-flop has two inputs and all possible combinations of input values are valid. a. J-K b. D c. S-R d. clocked S-R

10 The cache is capable of handling global as well as local variables. a. TRUE b. FALSE

10 The method of using the same lines for multiple purposes is known as time multiplexing. a. TRUE b. FALSE

10 The most important measure of performance for a processor is the rate at which it executes instructions. a. TRUE b. FALSE

10 The predict-never-taken approach is the most popular of all the branch prediction methods. a. TRUE b. FALSE

10 The principal advantage of the use of microprogramming to implement a control unit is that it simplifies the design of the control unit. a. TRUE b. FALSE

10 The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order. a. TRUE b. FALSE

10 The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write. a. access time b. gap time c. transfer time d. constant angular velocity

10 The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU. a. TRUE b. FALSE

10 The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages. a. TRUE b. FALSE

10 ________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. a. DisplayPort b. PCI Express c. Thunderbolt d. InfiniBand

10 _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions. a. Machine parallelism b. Instruction-level parallelism c. Output dependency d. Procedural dependency

10 __________ is the simplest mapping technique and maps each block of main memory into only one possible cache line. a. Direct mapping b. Associative mapping c. Set associative mapping d. None of the above

11 ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length. a. TRUE b. FALSE

11 An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level. a. TRUE b. FALSE

11 An error-correcting code enhances the reliability of the memory at the cost of added complexity. a. TRUE b. FALSE

11 Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices. a. TRUE b. FALSE

11 Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures. a. TRUE b. FALSE

11 Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations. a. TRUE b. FALSE

11 IBM's System/360 was the industry's first planned family of computers. a. TRUE b. FALSE

11 In general, a decoder has n inputs and 2n outputs. a. TRUE b. FALSE

11 It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired. a. TRUE b. FALSE

11 RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance. a. TRUE b. FALSE

11 Register renaming eliminates antidependencies and output dependencies. a. TRUE b. FALSE

11 Swapping is an I/O operation. a. TRUE b. FALSE

11 The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. a. TRUE b. FALSE

11 The principal disadvantage of a microprogrammed unit is that it will be somewhat slower than a hardwired unit of comparable technology. a. TRUE b. FALSE

4 An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. a. I/O channel b. I/O command c. I/O controller d. device controller

4 Condition codes facilitate multiway branches. a. TRUE b. FALSE

4 In the number 3109, the 3 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

4 It has become common practice to use a symbolic representation of machine instructions. a. TRUE b. FALSE

4 It is common for programs, both system and application, to continue to exhibit new bugs after years of operation. a. TRUE b. FALSE

4 It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete. a. TRUE b. FALSE

4 The IAS is the prototype of all subsequent general-purpose computers. a. TRUE b. FALSE

4 The control unit controls the operation of the processor. a. TRUE b. FALSE

4 The processor requires its own local memory. a. TRUE b. FALSE

4 The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________. a. true data dependency b. output dependency c. procedural dependency d. antidependency

4 The superscalar approach depends on the ability to execute multiple instructions in parallel. a. TRUE b. FALSE

4 The two traditional forms of RAM used in computers are DRAM and SRAM. a. TRUE b. FALSE

4 There are typically hundreds of sectors per track and they may be either fixed or variable lengths. a. TRUE b. FALSE

4 When a microinstruction is read from the control memory it is transferred to a _________. a. control buffer register b. control memory c. control address register d. control unit

4 With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. a. TRUE b. FALSE

4 ________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ. a. Logic b. Arithmetic c. Memory d. Test

5 A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously, and if processors are allowed to update their own copies freely, an inconsistent view of memory can result. a. cache coherence b. cluster c. failover d. failback

5 A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside. a. TRUE b. FALSE

5 A microprogram is midway between hardware and software. a. TRUE b. FALSE

5 A static RAM will hold its data as long as power is supplied to it. a. TRUE b. FALSE

5 An SMP operating system manages processor and other computer resources so that the user perceives a single operating system controlling system resources. a. TRUE b. FALSE

5 Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software. a. TRUE b. FALSE

5 Lotus Domino or Siebel CRM are examples of ___________ applications. a. threaded b. multi-process c. Java d. multi-instance

5 Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address. a. TRUE b. FALSE

5 Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________. a. constant angular velocity b. magnetoresistive c. rotational delay d. constant linear velocity

5 The IAS operates by repetitively performing an instruction cycle. a. TRUE b. FALSE

5 The OS must determine how much processor time is to be devoted to the execution of a particular user program. a. TRUE b. FALSE

5 The delay by the propagation time of signals through the gate is known as the gate delay. a. TRUE b. FALSE

5 The textbook for this course is about the structure and function of computers. a. TRUE b. FALSE

5 True data dependency is also called flow dependency or read after write (RAW) dependency. a. TRUE b. FALSE

5 ________ is when the result may be larger than can be held in the word size being used. a. Overflow b. Arithmetic shift c. Underflow d. Partial product

5 _________ instructions are used to position quantities in registers temporarily for computational operations. a. Load-and-store b. Window c. Complex d. Branch

6 A combinational circuit consists of n binary inputs and m binary outputs. a. TRUE b. FALSE

6 A disadvantage of memory-mapped I/O is that valuable memory address space is used up. a. TRUE b. FALSE

6 Backward compatible means that the programs written for the older machines can be executed on the new machine. a. TRUE b. FALSE

6 For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address. a. indexing b. base-register addressing c. relative addressing d. all of the above

6 For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required. a. TRUE b. FALSE

8 The terms _________ microprogramming are used to suggest the degree of closeness to the underlying control signals and hardware layout. a. hard/soft b. horizontal/vertical c. direct/indirect d. packed/unpacked

8 To handle any possible pattern of calls and returns the number of register windows would have to be unbounded. a. TRUE b. FALSE

8 ________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement. a. State b. Memory address c. Micro-op d. Alias register

8 _________ can be caused by power supply problems or alpha particles. a. Soft errors b. AGT errors c. Hard errors d. SEC errors

9 "Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs. a. TRUE b. FALSE

9 A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology. a. TRUE b. FALSE

9 A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions. a. delayed load b. delayed program c. delayed slot d. delayed register

9 Addresses are a form of data. a. TRUE b. FALSE

9 All DRAMs require a refresh operation. a. TRUE b. FALSE

9 Although convenient for computers, the binary system is exceedingly cumbersome for human beings. a. TRUE b. FALSE

9 An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol. a. TRUE b. FALSE

9 At the completion of the execute cycle a test is made to determine whether any enabled interrupts have occurred, and if they have, the interrupt cycle occurs. a. TRUE b. FALSE

9 Both batch multiprogramming and time sharing use multiprogramming. a. TRUE b. FALSE

9 Bus arbitration makes use of vectored interrupts. a. TRUE b. FALSE

9 One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline. a. TRUE b. FALSE

9 The _________ instruction includes an implied address. a. skip b. rotate c. stack d. push

9 To achieve greatest performance the memory must be able to keep up with the processor. a. TRUE b. FALSE

9 With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0. a. TRUE b. FALSE

False

A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form. a. True b. False

800 to 1600

A DDR3 module transfers data at a clock rate of __________ MHz. a. 600 to 1200 b. 800 to 1600 c. 1000 to 2000 d. 1500 to 3000

True

A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device. a. True b. False

gate

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals. a. gate b. decoder c. counter d. flip-flop

router

A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network. a. memory controller b. TCA c. HCA d. router

data

A ________ hazard occurs when there is a conflict in the access of an operand location. a. resource b. data c. structural d. control

NOOP

A ________ instruction can be used to account for data and branch delays. a. SUB b. NOOP c. JUMP d. all of the above

target channel adapter

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. a. target channel adapter b. InfiniBand switch c. host channel adapter d. subnet

shift register

A _________ accepts and/or transfers information serially. a. S-R latch b. shift register c. FPGA d. parallel register

superpipelined

A _________ architecture is one that makes use of more, and more fine-grained pipeline stages. a. parallel b. superpipelined c. superscalar d. hybrid

FPGA

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs. a. SPLD b. FPGA c. PAL d. PLA

domain

A _________ is a collection of memory regions. a. APX b. nucleus c. domain d. page table

Blu-ray DVD

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side. a. DVD b. DVD-R c. DVD-RW d. Blu-ray DVD

system interconnection

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. a. system interconnection b. CPU interconnection c. peripheral d. processor

loop buffer

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. a. loop buffer b. delayed branch c. multiple stream d. branch prediction

job control language

A _________ is a special type of programming language used to provide instructions to the monitor. a. job control language b. multiprogram c. kernel d. utility

physical address

A _________ is an actual location in main memory. a. logical address b. partition address c. base address d. physical address

True

A combinational circuit consists of n binary inputs and m binary outputs. a. True b. False

system bus

A common example of system interconnection is by means of a __________. a. register b. system bus c. data transport d. control device

False

A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS). a. True b. False

True

A computer must be able to process, store, move, and control data. a. True b. False

False

A control hazard occurs when two or more instructions that are already in the pipeline need the same resource. a. True b. False

True

A disadvantage of memory-mapped I/O is that valuable memory address space is used up. a. True b. False

False

A high-level language expresses operations in a basic form involving the movement of data to or from registers. a. True b. False

False

A key characteristic of a bus is that it is not a shared transmission medium. a. True b. False

True

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet. a. True b. False

tag

A line includes a _________ that identifies which particular block is currently being stored. a. cache b. hit c. tag d. locality

virtual addresses

A logical cache stores data using __________. a. physical addresses b. virtual addresses c. random addresses d. none of the above

False

A microcomputer architecture and organization relationship is not very close. a. True b. False

False

A multipoint external interface provides a dedicated line between the I/O module and the external device. a. True b. False

False

A nibble is a grouping of four decimal digits. a. True b. False

False

A number cannot be converted from binary notation to decimal notation. a. True b. False

True

A number of chips can be grouped together to form a memory bank. a. True b. False

True

A number with both an integer and fractional part has digits raised to both positive and negative powers of 10. a. True b. False

True

A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology. a. True b. False

disk cache

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________. a. disk cache b. latency c. virtual address d. miss

True

A register is a digital circuit used within the CPU to store one or more bits of data. a. True b. False

True

A removable disk can be removed and replaced with another disk. a. True b. False

software

A sequence of codes or instructions is called __________. a. software b. memory c. an interconnect d. a register

False

A sequence of hexadecimal digits can be thought of as representing an integer in base 10. a. True b. False

True

A set of I/O modules is a key element of a computer system. a. True b. False

True

A static RAM will hold its data as long as power is supplied to it. a. True b. False

delayed load

A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions. a. delayed load b. delayed program c. delayed slot d. delayed register

radix

Another term for "base" is __________. a. radix b. integer c. position d. digit

True

Any Boolean function can be implemented in electronic form as a network of gates. a. True b. False

I/O mechanisms

Architectural attributes include __________ . a. I/O mechanisms b. control signals c. interfaces d. memory technology used

True

At a top level, a computer consists of CPU, memory, and I/O components. a. True b. False

1 A taxonomy first introduced by _______ is still the most common way of categorizing systems with parallel processing capability. a. Randolph b. Flynn c. von Neuman d. Desai

1 Our primary counting system is based on binary digits to represent numbers. a. TRUE b. FALSE

1 The ________ specifies the operation to be performed. a. source operand reference b. opcode c. next instruction reference d. processor register

1 The _________ contains logic for performing a communication function between the peripheral and the bus. a. I/O channel b. I/O module c. I/O processor d. I/O command

1 The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware. a. job control language b. operating system c. batch system d. nucleus

13 The ________ contains I/O protocols that are mapped on to the transport layer. a. cable b. application c. common transport d. physical

1 The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand. a. direct addressing b. immediate addressing c. register addressing d. stack addressing

1 The decimal system has a base of _________. a. 0 b. 10 c. 100 d. 1000

1 The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University. a. TRUE b. FALSE

1 Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. a. John Maulchy b. John von Neumann c. Herman Hollerith d. John Eckert

1 _________ determines the control and pipeline organization. a. Calculation b. Execution sequencing c. Operations performed d. Operands used

10 A microcomputer architecture and organization relationship is not very close. a. TRUE b. FALSE

10 A nibble is a grouping of four decimal digits. a. TRUE b. FALSE

10 Not all machine languages include numeric data types. a. TRUE b. FALSE

10 Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words. a. TRUE b. FALSE

10 The execute cycle is simple and predictable. a. TRUE b. FALSE

10 The rotating interrupt mode allows the processor to inhibit interrupts from certain devices. a. TRUE b. FALSE

10 With no multithreading, _________ is the simple pipeline found in traditional RISC and CISC machines. a. superscalar b. single-threaded scalar c. blocked multithreaded scalar d. interleaved multithreaded scalar

11 A _________ accepts and/or transfers information serially. a. S-R latch b. shift register c. FPGA d. parallel register

11 A __________ is the high-level set of rules for exchanging packets of data between devices. a. bus b. protocol c. packet d. QPI

11 Decimal "10" is _________ in hexadecimal. a. 1 b. A c. 0 d. FF

11 For base 2 representation, a normal number is one in which the most significant bit of the significand is zero. a. TRUE b. FALSE

11 Hexadecimal notation is only used for representing integers. a. TRUE b. FALSE

11 Machine cycles are defined to be equivalent to ________ accesses. a. flag b. bus c. clock d. path

11 Positive numbers greater than (2 - 2-23) x 2-128 are called _________. a. negative underflow b. positive overflow c. positive underflow d. negative overflow

11 The L1 cache is slower than the L3 cache. a. TRUE b. FALSE

11 The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________. a. branch b. stack frame c. pop d. push

11 When using graph coloring, nodes that share the same color cannot be assigned to the same register. a. TRUE b. FALSE

11 ________ is when the processor spends most of its time swapping pages rather than executing instructions. a. Swapping b. Thrashing c. Paging d. Multitasking

11 _________ is a principle by which two variables are independent of each other. a. Opcode b. Orthogonality c. Completeness d. Autoindexing

12 A _________ architecture is one that makes use of more, and more fine-grained pipeline stages. a. parallel b. superpipelined c. superscalar d. hybrid

12 Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates. a. TRUE b. FALSE

12 DRAM is much costlier than SRAM. a. TRUE b. FALSE

12 RAID level ________ has the highest disk overhead of all RAID types. a. 0 b. 1 c. 3 d. 5

12 The Intel Core i7-990X, introduced in 2008, implements ______ x86 SMT processors, each with a dedicated L2 cache, and with a shared L3 cache. a. 2 b. 4 c. 6 d. 8

12 The _________ stage includes ALU operations, cache access, and register update. a. decode b. execute c. fetch d. write back

12 The function of switching applications and data resources over from a failed system to an alternative system in the cluster is referred to as failback. a. TRUE b. FALSE

12 The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit. a. logical cache b. split cache c. unified cache d. physical cache

12 With asynchronous timing the occurrence of events on the bus is determined by a clock. a. TRUE b. FALSE

12 With demand paging it is necessary to load an entire process into main memory. a. TRUE b. FALSE

13 An interrupt is generated from software and it is provoked by the execution of an instruction. a. TRUE b. FALSE

13 Binary addition is exactly the same as Boolean algebra. a. TRUE b. FALSE

13 For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits. a. TRUE b. FALSE

13 Processors are called ________. a. dies b. cores c. QPI d. interconnects

13 RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle. a. TRUE b. FALSE

14 An operation that switches the processor from one process to another by saving all the process control data, register, and other information for the first and replacing them with the process information for the second is: a. resource ownership switch b. process switch c. thread switch d. cluster switch

14 Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0. a. TRUE b. FALSE

14 Procedures do not allow programming tasks to be subdivided into smaller units. a. TRUE b. FALSE

14 SSD performance has a tendency to speed up as the device is used. a. TRUE b. FALSE

14 The Advanced Programmable Interrupt controller (APIC) monitors thermal conditions and CPU activity and adjusts voltage levels and power consumption appropriately. a. TRUE b. FALSE

14 The Intel x86 evolved from RISC design principles and is used in embedded systems. a. TRUE b. FALSE

14 The PDP-11 is the first member of the LSI-11 family that was offered as a single board processor. a. TRUE b. FALSE

14 The ________ introduced a full-blown superscalar design with out-of-order execution. a. Pentium b. Pentium Pro c. 386 d. 486

14 The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit. a. TRUE b. FALSE

15 A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device. a. TRUE b. FALSE

15 A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs. a. SPLD b. FPGA c. PAL d. PLA

15 A branch instruction in which the branch is always taken is _________. a. conditional branch b. unconditional branch c. jump d. bi-endian

15 A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS). a. TRUE b. FALSE

15 A logical cache stores data using __________. a. physical addresses b. virtual addresses c. random addresses d. none of the above

15 Binary 0101 is hexadecimal _________. a. 0 b. 5 c. A d. 10

15 Cache design for HPC is the same as that for other hardware platforms and applications. a. TRUE b. FALSE

15 Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain. a. TRUE b. FALSE

15 The OS maintains a __________ for each process that shows the frame location for each page of the process. a. kernel b. page table c. TLB d. logical address

15 The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data. a. TRUE b. FALSE

15 The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices. a. TRUE b. FALSE

15 When data are moved over longer distances, to or from a remote device, the process is known as data transport. a. TRUE b. FALSE

15 __________ means that the number is too small to be represented and it may be reported as 0. a. Negative underflow b. Exponent underflow c. Positive underflow d. Significand underflow

19 _________ attributes include hardware details transparent to the programmer. a. Interface b. Organizational c. Memory d. Architectural

2 A characteristic of ROM is that it is volatile. a. TRUE b. FALSE

2 A microprogrammed control unit is a relatively complex logic circuit. a. TRUE b. FALSE

2 A(n) _________ expresses operations in a concise algebraic form using variables. a. opcode b. high-level language c. machine language d. register

2 Adjacent tracks are separated by _________. a. sectors b. gaps c. pits d. heads

2 Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra. a. TRUE b. FALSE

2 During a read or write operation, the head rotates while the platter beneath it stays stationary. a. TRUE b. FALSE

2 Each instruction executed during an instruction cycle is made up of shorter ______. a. executions b. subcycles c. steps d. none of the above

2 In a system without virtual memory, the effective address is a virtual address or a register. a. TRUE b. FALSE

2 The control unit (CU) does the actual computation or processing of data. a. TRUE b. FALSE

2 The decimal system has a radix of 100. a. TRUE b. FALSE

2 The end user is concerned mainly with the computer's architecture. a. TRUE b. FALSE

2 The variety of computer products is exhibited only in cost. a. TRUE b. FALSE

2 Which digit represents "hundreds" in the number 8732? a. 8 b. 7 c. 3 d. 2

2 __________ representation is almost universally used as the processor representation for integers. a. Biased b. Twos compliment c. Sign-magnitude d. Decimal

20 The __________ interprets the instructions in memory and causes them to be executed. a. main memory b. control unit c. I/O d. arithmetic and logic unit

9 A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading. a. multi-process b. fine-grained c. hybrid d. coarse

9 Cache memory is a much faster memory than the register file. a. TRUE b. FALSE

9 In-order completion requires more complex instruction issue logic than out-of-order completion. a. TRUE b. FALSE

9 It is not possible to connect I/O controllers directly onto the system bus. a. TRUE b. FALSE

9 Negative numbers greater than 2-127 are called _________. a. negative overflow b. negative underflow c. positive overflow d. positive underflow

9 System software was introduced in the third generation of computers. a. TRUE b. FALSE

9 The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. a. DDR-DRAM b. SDRAM c. CDRAM d. none of the above

9 The _________ system uses only the numbers 0 and 1. a. positional b. binary c. hexadecimal d. decimal

9 The advantage of horizontal microinstructions is that they are more compact than vertical microinstructions, at the expense of a small additional amount of logic and time delay. a. TRUE b. FALSE

9 The transfer time to or from the disk does not depend on the rotation speed of the disk. a. TRUE b. FALSE

9 Typically an instruction set will include both preindexing and postindexing. a. TRUE b. FALSE

9 With _________ encoding one field is used to determine the interpretation of another field. a. resource b. indirect c. direct d. functional

9 With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread. a. TRUE b. FALSE

9 __________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. a. Flow dependency b. Instruction-level parallelism c. Machine parallelism d. Instruction issue

True

Backward compatible means that the programs written for the older machines can be executed on the new machine. a. True b. False

True

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. a. True b. False

False

Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates. a. True b. False

True

Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes. a. True b. False

True

Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices. a. True b. False

13 The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. a. fetch/decode unit b. out-of-order execution logic c. execution unit d. memory subsystem

13 The ________ pulse signals the start of each machine cycle from the control unit and alerts external circuits. a. AC b. INSTR c. ALE d. OUT

13 ________ is used for debugging. a. Direction flag b. Alignment check c. Trap flag d. Identification flag

14 A _________ is a collection of memory regions. a. APX b. nucleus c. domain d. page table

14 All instructions in the ARM architecture are __________ bits long and follow a regular format. a. 8 b. 16 c. 32 d. 64

14 SPARC refers to an architecture defined by ________. a. Microsoft b. Apple c. Sun Microsystems d. IBM

14 ________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center. a. Constant angular velocity (CAV) b. Magnetoresistive c. Constant linear velocity (CLV) d. Seek time

14 __________ is when a positive exponent exceeds the maximum possible exponent value. a. Significand underflow b. Significand overflow c. Exponent overflow d. Exponent underflow

15 A _________ is a combinatorial circuit that generates an address based on the microinstruction, the machine instruction, the microinstruction program counter, and an interrupt register. a. microsequencer b. vertical microinstruction c. translation array d. control word

15 The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. a. link b. protocol c. routing d. physical

15 The ________ is responsible for maintaining coherency among L1 data caches. a. VFP unit b. distributed interrupt controller c. snoop control unit (SCU) d. watchdog

15 Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions. a. 486 b. Pentium c. Pentium 4 d. Pentium Pro

16 Computer technology is changing at a __________ pace. a. slow b. slow to medium c. rapid d. non-existent

16 The _________ was the world's first general-purpose electronic digital computer. a. UNIVAC b. MARK IV c. ENIAC d. Hollerith's Counting Machine

2 Internal memory capacity is typically expressed in terms of _________. a. hertz b. nanos c. bytes d. LOR

2 The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines. a. scalar b. branch c. superscalar d. flow dependency

2 The set of microinstructions is stored in the __________. a. control address register b. control buffer register c. control memory d. control word

2 Uniprocessors fall into the _______ category of computer systems. a. MIMD b. SIMD c. SISD d. MISD

2 _________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline, another instruction is executing in another stage of the pipeline. a. Superscalar b. Scalar c. Pipelining d. Simultaneous multithreading

22 The __________ contains the 8-bit opcode instruction being executed. a. memory buffer register b. instruction buffer register c. instruction register d. memory address register

23 An I/O device is referred to as a __________. a. CPU b. control device c. peripheral d. register

25 The _________ stores data. a. system bus b. I/O c. main memory d. control unit

3 Data are transferred to and from the disk in __________. a. tracks b. gaps c. sectors d. pits

3 The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. a. cycle b. status reporting c. control and timing d. data

3 There must be ________ instructions for moving data between memory and the registers. a. branch b. logic c. memory d. I/O

3 Which of the following is correct? a. 25 = (2 x 102) + (5 x 101) b. 289 = (2 x 103) + (8 x 101) + (9 x 100) c. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100) d. 0.628 = (6 x 10-3) + (2 x 10-2) + (8 x 10-1)

3 _________ is the fastest available storage device. a. Main memory b. Cache c. Register storage d. HLL

30 The __________ performs the computer's data processing functions. a. Register b. CPU interconnection c. ALU d. system bus

4 The _________ cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory. a. execute b. indirect c. fetch d. interrupt

4 The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture. a. HLL b. API c. ABI d. ISA

4 The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required. a. direct b. indirect c. register d. displacement

4 The processing required for a single instruction is called a(n) __________ cycle. a. execute b. fetch c. instruction d. packet

5 A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. a. RAM b. SRAM c. ROM d. flash memory

base 2

Numbers in the binary system are represented to the _________. a. base 0 b. base 1 c. base 2 d. base 10

synchronous

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time. a. synchronous b. asynchronous c. clocked S-R d. timed ripple

False

Cache design for HPC is the same as that for other hardware platforms and applications. a. True b. False

False

Cache is not a form of internal memory. a. True b. False

False

Cache memory is a much faster memory than the register file. a. True b. False

False

Changes in computer technology are finally slowing down. a. True b. False

True

Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures. a. True b. False

False

Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra. a. True b. False

True

Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained. a. True b. False

Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software.

both asynchronous and synchronous

Counters can be designated as _________. a. asynchronous b. synchronous c. both asynchronous and synchronous d. neither asynchronous or synchronous

1 A single micro-operation generally involves which of the following? a. a transfer between registers b. a transfer between a register and an external bus c. a simple ALU operation d. all of the above

1 The superscalar approach can be used on __________ architecture. a. RISC b. CISC c. neither RISC nor CISC d. both RISC and CISC

1 Which properties do all semiconductor memory cells share? a. they exhibit two stable states which can be used to represent binary 1 and 0 b. they are capable of being written into to set the state c. they are capable of being read to sense the state d. all of the above

10 A _________ is an actual location in main memory. a. logical address b. partition address c. base address d. physical address

10 The _________ is an example of splitting off a separate, shared L3 cache, with dedicated L1 and L2 caches for each core processor. a. IBM 370 b. ARM11 MPCore c. AMD Opteron d. Intel Core i7

10 Which of the following interrelated factors go into determining the use of the addressing bits? a. number of operands b. number of register sets c. address range d. all of the above

10 Which of the following is a LSI-11 microinstruction? a. add word b. test word c. Jump d. all of the above

10 Which of the following is a true statement? a. a procedure can be called from more than one location b. a procedure call can appear in a procedure c. each procedure call is matched by a return in the called program d. all of the above

11 All MIPS R series processor instructions are encoded in a single ________ word format. a. 4-bit b. 8-bit c. 16-bit d. 32-bit

11 ________ is a protocol used to issue instructions. a. Micro-ops b. Scalar c. SIMD d. Instruction issue policy

12 The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. a. cable b. application c. common transport d. physical

12 The ________ portion of the control unit issues a repetitive sequence of pulses. a. instruction register b. flag c. control bus signals d. clock

13 A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side. a. DVD b. DVD-R c. DVD-RW d. Blu-ray DVD

13 Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance? a. duplication of resources b. out-of-order issue c. renaming d. all of the above

13 Which of the following is an approach to vector computation? a. pipelined ALU b. parallel ALU's c. parallel processors d. all of the above

14 In the number 472.156 the 2 is the _________. a. most significant digit b. radix point c. least significant digit d. none of the above

14 The ARM architecture supports _______ execution modes. a. 2 b. 8 c. 11 d. 7

14 The TL supports which of the following address spaces? a. memory b. I/O c. message d. all of the above

14 Which data type is defined in MMX? a. packed byte b. packed word c. packed doubleword d. all of the above

14 Which of the following is an Intel 8085 external signal? a. CLK(OUT) b. read control c. HOLDA d. all of the above

15 A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network. a. memory controller b. TCA c. HCA d. router

15 The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible. a. flash memory b. Hamming code c. RamBus d. buffer

False

During a read or write operation, the head rotates while the platter beneath it stays stationary. a. True b. False

fetch cycle

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. a. execute cycle b. fetch cycle c. instruction cycle d. clock cycle

lane

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time. a. lane b. path c. line d. bus

True

Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs. a. True b. False

False

External memory is often equated with main memory. a. True b. False

utility

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS. a. utility b. multitasking c. JCL d. logical address

indexing

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address. a. indexing b. base-register addressing c. relative addressing d. all of the above

False

For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits. a. True b. False

For base 2 representation, a normal number is one in which the most significant bit of the significand is zero.

For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required.

unit of transfer

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module. a. access time b. unit of transfer c. capacity d. memory ratio

Quine-McCluskey

For more than four variables an alternative approach is a tabular technique referred to as the _________ method. a. DeMorgan b. Quine-McCluskey c. Karnaugh map d. Boole-Shannon

access time

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. a. memory cycle time b. direct access c. transfer rate d. access time

immediate

For the _________ mode, the operand is included in the instruction. a. immediate b. base c. register d. displacement

nibble

Four bits is called a _________. a. radix point b. byte c. nibble d. binary digit

the glass substrate

Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________. a. magnetic read and write mechanisms b. platters c. the glass substrate d. a solid state drive

False

In-order completion requires more complex instruction issue logic than out-of-order completion. a. True b. False

postindexing

Indexing performed after the indirection is __________. a. relative addressing b. autoindexing c. postindexing d. preindexing

antidependency

Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses. a. in-order issue b. resource conflict c. antidependency d. out-of-order completion

True

Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity. a. True b. False

True

Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip. a. True b. False

True

Interfaces between the computer and peripherals is an example of an organizational attribute. a. True b. False

bytes

Internal memory capacity is typically expressed in terms of _________. a. hertz b. nanos c. bytes d. LOR

True

Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed. a. True b. False

False

Interrupts do not improve processing efficiency. a. True b. False

True

It has become common practice to use a symbolic representation of machine instructions. a. True b. False

True

It has become possible to have a cache on the same chip as the processor. a. True b. False

architectural

It is a(n) _________ design issue whether a computer will have a multiply instruction. a. architectural b. memory c. elementary d. organizational

organizational

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. a. architectural b. memory c. mechanical d. organizational

True

It is common for programs, both system and application, to continue to exhibit new bugs after years of operation. a. True b. False

True

It is extremely easy to convert between binary and hexadecimal notation. a. True b. False

It is not necessary for the ALU to signal when overflow occurs.

False

It is not possible to connect I/O controllers directly onto the system bus. a. True b. False

True

It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired. a. True b. False

True

It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete. a. True b. False

True

John Mauchly and John Eckert designed the ENIAC. a. True b. False

False

Logical functions are implemented by the interconnection of decoders. a. True b. False

False

Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. a. True b. False

True

Magnetic disks are the foundation of external memory on virtually all computer systems. a. True b. False

False

Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain. a. True b. False

False

Memory references are faster than register references. a. True b. False

True

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept. a. True b. False

True

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations. a. True b. False

True

Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address. a. True b. False

False

True

Resources include: memories, caches, buses, and register-file ports. a. True b. False

Sun Microsystems

SPARC refers to an architecture defined by ________. a. Microsoft b. Apple c. Sun Microsystems d. IBM

False

SSD performance has a tendency to speed up as the device is used. a. True b. False

constant angular velocity

Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________. a. constant angular velocity b. magnetoresistive c. rotational delay d. constant linear velocity

True

Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture. a. True b. False

Transistors

Second generation computers used __________. a. integrated circuits b. Transistors c. vacuum tubes d. large-scale integration

False

Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words. a. True b. False

True

Semiconductor memory comes in packaged chips. a. True b. False

True

Swapping is an I/O operation. a. True b. False

False

System software was introduced in the third generation of computers. a. True b. False

True

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems. a. True b. False

first

The ENIAC is an example of a _________ generation computer. a. first b. second c. third d. fourth

vacuum tubes

The ENIAC used __________. a. vacuum tubes b. integrated circuits c. IAS

World War II

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________. a. the Civil War b. the French-American War c. World War I d. World War II

control and timing

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. a. cycle b. status reporting c. control and timing d. data

True

The IAS is the prototype of all subsequent general-purpose computers. a. True b. False

True

The IAS operates by repetitively performing an instruction cycle. a. True b. False

False

The Intel x86 evolved from RISC design principles and is used in embedded systems. a. True b. False

False

The L1 cache is slower than the L3 cache. a. True b. False

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU. a. 16 b. 32 c. 64 d. 128

page table

The OS maintains a __________ for each process that shows the frame location for each page of the process. a. kernel b. page table c. TLB d. logical address

True

The OS must determine how much processor time is to be devoted to the execution of a particular user program. a. True b. False

supervisor mode

The OS usually runs in ________. a. supervisor mode b. abort mode c. undefined mode d. fast interrupt mode

HLL

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture. a. HLL b. RISC c. CISC d. all of the above

execution unit

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. a. fetch/decode unit b. out-of-order execution logic c. execution unit d. memory subsystem

True

The Pentium II includes hardware for both segmentation and paging. a. True b. False

routing

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. a. link b. protocol c. routing d. physical

The R4000 can have as many as _______ instructions in the pipeline at the same time. a. 8 b. 10 c. 5 d. 3

write back

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage. a. write back b. tag check c. data cache d. instruction execute

False

The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data. a. True b. False

True

The SSDs now on the market use a type of semiconductor memory referred to as flash memory. a. True b. False

all of the above

The TL supports which of the following address spaces? a. memory b. I/O c. message d. all of the above

physical

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. a. cable b. application c. common transport d. physical

control

The ________ command is used to activate a peripheral and tell it what to do. a. control b. test c. read d. write

memory cycle time

The ________ consists of the access time plus any additional time required before a second access can commence. a. latency b. memory cycle time c. direct access d. transfer rate

application

The ________ contains I/O protocols that are mapped on to the transport layer. a. cable b. application c. common transport d. physical

control unit

The ________ controls the movement of data and instructions into and out of the processor. a. control unit b. ALU c. shifter d. branch

API

The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls. a. JCL b. ISA c. ABI d. API

Pentium Pro

The ________ introduced a full-blown superscalar design with out-of-order execution. a. Pentium b. Pentium Pro c. 386 d. 486

common transport

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. a. cable b. application c. common transport d. physical

short-term

The ________ scheduler is also known as the dispatcher. a. long-term b. medium-term c. short-term d. I/O

opcode

The ________ specifies the operation to be performed. a. source operand reference b. opcode c. next instruction reference d. processor register

write

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. a. control b. test c. read d. write

MBR

The _________ contains a word of data to be written to memory or the word most recently read. a. MAR b. PC c. MBR d. IR

I/O module

The _________ contains logic for performing a communication function between the peripheral and the bus. a. I/O channel b. I/O module c. I/O processor d. I/O command

program counter

The _________ contains the address of an instruction to be fetched. a. instruction register b. memory address register c. memory buffer register d. program counter

ISA

The _________ defines the repertoire of machine language instructions that a computer can follow. a. ABI b. API c. HLL d. ISA

ABI

The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture. a. HLL b. API c. ABI d. ISA

SDRAM

The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. a. DDR-DRAM b. SDRAM c. CDRAM d. none of the above

skip

The _________ instruction includes an implied address. a. skip b. rotate c. stack d. push

branch history table

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. a. dynamic branch b. loop table c. branch history table d. flag

transaction layer

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. a. transaction layer b. root layer c. configuration layer d. transport layer

long-term

The _________ scheduler determines which programs are admitted to the system for processing. a. long-term b. medium-term c. short-term d. I/O

execute

The _________ stage includes ALU operations, cache access, and register update. a. decode b. execute c. fetch d. write back

main memory

The _________ stores data. a. system bus b. I/O c. main memory d. control unit

binary

The _________ system uses only the numbers 0 and 1. a. positional b. binary c. hexadecimal d. decimal

excitation

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit. a. excitation b. Kenough c. J-K flip-flop d. FPGA

PDP-11

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer. a. PDP-1 b. PDP-8 c. PDP-11 d. PDP-10

ENIAC

The _________ was the world's first general-purpose electronic digital computer. a. UNIVAC b. MARK IV c. ENIAC d. Hollerith's Counting Machine

address lines

The __________ are used to designate the source or destination of the data on the data bus. a. system lines b. data lines c. control lines d. address lines

SIB

The __________ byte consists of three fields: the Scale field, the Index field and the Base field. a. SIB b. VAX c. PDP-11 d. ModR/M

instruction register

The __________ contains the 8-bit opcode instruction being executed. a. memory buffer register b. instruction buffer register c. instruction register d. memory address register

integrated circuit

The __________ defines the third generation of computers. a. integrated circuit b. vacuum tube c. transistor d. VLSI

control unit

The __________ interprets the instructions in memory and causes them to be executed. a. main memory b. control unit c. I/O d. arithmetic and logic unit

operating system

The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware. a. job control language b. operating system c. batch system d. nucleus

speed metric

The __________ measures the ability of a computer to complete a single task. a. clock speed b. speed metric c. execute cycle d. cycle time

I/O

The __________ moves data between the computer and its external environment. a. data transport b. I/O c. register d. CPU interconnection

ALU

The __________ performs the computer's data processing functions. a. Register b. CPU interconnection c. ALU d. system bus

False

The address of the next instruction to be fetched must be a real address, not a virtual address. a. True b. False

False

The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device. a. True b. False

immediate addressing

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand. a. direct addressing b. immediate addressing c. register addressing d. stack addressing

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required. a. direct b. indirect c. register d. displacement

False

The allocation of control information between registers and memory are not considered to be a key design issue. a. True b. False

lands

The areas between pits are called _________. a. lands b. sectors c. cylinders d. strips

True

The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. a. True b. False

True

The basic element of a semiconductor memory is the memory cell. a. True b. False

True

The basic function of a computer is to execute programs. a. True b. False

DE116

The binary string 110111100001 is equivalent to __________. a. DE116 b. C7816 c. FF6416 d. B8F16

True

The cache is capable of handling global as well as local variables. a. True b. False

False

The control unit (CU) does the actual computation or processing of data. a. True b. False

True

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline. a. True b. False

data bus

The data lines provide a path for moving data among system modules and are collectively called the _________. a. control bus b. address bus c. data bus d. system bus

The decimal system has a base of _________. a. 0 b. 10 c. 100 d. 1000

False

The decimal system has a radix of 100. a. True b. False

True

The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9. a. True b. False

True

The delay by the propagation time of signals through the gate is known as the gate delay. a. True b. False

CAV

The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks. a. SSD b. CAV c. ROM d. CLV

True

The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field. a. True b. False

True

The disadvantage of the software poll is that it is time consuming. a. True b. False

False

The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector. a. True b. False

False

The end user is concerned mainly with the computer's architecture. a. True b. False

stack frame

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________. a. branch b. stack frame c. pop d. push

superscalar

The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines. a. scalar b. branch c. superscalar d. flow dependency

True

The exception modes have full access to system resources and can change modes freely. a. True b. False

the Pyramid

The first commercial RISC product was _________. a. SPARC b. CISC c. VAX d. the Pyramid

True

The focus of MMX technology is multimedia programming. a. True b. False

True

The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly. a. True b. False

True

The hierarchical nature of complex systems is essential to both their design and their description. a. True b. False

delay slot

The instruction location immediately following the delayed branch is referred to as the ________. a. delay load b. delay file c. delay slot d. delay register

True

The instruction set is the programmer's means of controlling the processor. a. True b. False

procedural dependency

The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed. a. resource dependency b. procedural dependency c. output dependency d. true data dependency

split cache

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit. a. logical cache b. split cache c. unified cache d. physical cache

False

The major cost in the life cycle of a system is hardware. a. True b. False

False

The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables. a. True b. False

words

The memory of the IAS consists of 1000 storage locations called __________. a. opcodes b. wafers c. VLSIs d. words

True

The memory transfer rate has not kept up with increases in processor speed. a. True b. False

True

The method of calculating the EA is the same for both base-register addressing and indexing. a. True b. False

True

The method of using the same lines for multiple purposes is known as time multiplexing. a. True b. False

keyboard/monitor

The most common means of computer/user interaction is a __________. a. keyboard/monitor b. mouse/printer c. modem/printer d. monitor/printer

data transfer

The most fundamental type of machine instruction is the _________ instruction. a. conversion b. data transfer c. arithmetic d. logical

True

The most important system program is the OS. a. True b. False

True

The number of bits used to represent various data types is an example of an architectural attribute. a. True b. False

The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers.

immediate

The only form of addressing for branch instructions is _________ addressing. a. register b. relative c. base d. immediate

AND

The operand ________ yields true if and only if both of its operands are true. a. XOR b. OR c. AND d. NOT

The operation _________ yields true if either or both of its operands are true. a. NOT b. AND c. NAND d. OR

True

The operation of the digital computer is based on the storage and processing of binary data. a. True b. False

True

The operation to be performed is specified by a binary code known as the operation code. a. True b. False

True

The predict-never-taken approach is the most popular of all the branch prediction methods. a. True b. False

True

The prefetch buffer is a memory cache located on the RAM chip. a. True b. False

direct

The principal advantage of ___________ addressing is that it is a very simple form of addressing. a. displacement b. register c. stack d. direct

True

The principal price to pay for variable-length instructions is an increase in the complexity of the processor. a. True b. False

instruction

The processing required for a single instruction is called a(n) __________ cycle. a. execute b. fetch c. instruction d. packet

True

The processor needs to store instructions and data temporarily while an instruction is being executed. a. True b. False

True

The processor requires its own local memory. a. True b. False

True

The register file employs much shorter addresses than addresses for cache and memory. a. True b. False

True

The register file is on the same chip as the ALU and control unit. a. True b. False

True

The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order. a. True b. False

False

The rotating interrupt mode allows the processor to inhibit interrupts from certain devices. a. True b. False

True

The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution. a. True b. False

cylinder

The set of all the tracks in the same relative position on the platter is referred to as a _________. a. floppy disk b. single-sided disk c. sector d. cylinder

False

With demand paging it is necessary to load an entire process into main memory. a. True b. False

True

The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion). a. True b. False

true data dependency

The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________. a. true data dependency b. output dependency c. procedural dependency d. antidependency

access time

The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write. a. access time b. gap time c. transfer time d. constant angular velocity

both RISC and CISC

The superscalar approach can be used on __________ architecture. a. RISC b. CISC c. neither RISC nor CISC d. both RISC and CISC

True

The superscalar approach depends on the ability to execute multiple instructions in parallel. a. True b. False

True

The superscalar approach has now become the standard method for implementing high-performance microprocessors. a. True b. False

True

The textbook for this course is about the structure and function of computers. a. True b. False

False

The transfer time to or from the disk does not depend on the rotation speed of the disk. a. True b. False

True

The two traditional forms of RAM used in computers are DRAM and SRAM. a. True b. False

NOT

The unary operation _________ inverts the value of its operand. a. OR b. NOT c. NAND d. XOR

False

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit. a. True b. False

False

The unit of transfer must equal a word or an addressable unit. a. True b. False

multicore

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. a. multicore b. GPU c. data channels d. MPC

True

The value of the mode field determines which addressing mode is to be used. a. True b. False

True

The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU. a. True b. False

False

The variety of computer products is exhibited only in cost. a. True b. False

all of the above

The von Neumann architecture is based on which concept? a. data and instructions are stored in a single read-write memory b. the contents of this memory are addressable by location c. execution occurs in a sequential fashion d. all of the above

False

The width of a track is double that of the head. a. True b. False

False

The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University. a. True b. False

integer

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________. a. general b. ordinal c. integer d. packed BCD

True

The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages. a. True b. False

200 to 600

Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz. a. 200 to 600 b. 400 to 1066 c. 600 to 1400 d. 800 to 1600

True

There are 50 tens in the number 509. a. True b. False

True

There are typically hundreds of sectors per track and they may be either fixed or variable lengths. a. True b. False

True

There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer". a. True b. False

memory

There must be ________ instructions for moving data between memory and the registers. a. branch b. logic c. memory d. I/O

False

Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing. a. True b. False

True

Timing refers to the way in which events are coordinated on the bus. a. True b. False

True

To achieve greatest performance the memory must be able to keep up with the processor. a. True b. False

True

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded. a. True b. False

False

Uniprogramming is the central theme of modern operating systems. a. True b. False

True

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance. a. True b. False

Pentium 4

Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions. a. 486 b. Pentium c. Pentium 4 d. Pentium Pro

TLB

Virtual memory schemes make use of a special cache called a ________ for page table entries. a. TLB b. HLL c. VMC d. SPB

John von Neumann

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. a. John Maulchy b. John von Neumann c. Herman Hollerith d. John Eckert

data communications

When data are moved over longer distances, to or from a remote device, the process is known as __________. a. data communications b. registering c. structuring d. data transport

False

When data are moved over longer distances, to or from a remote device, the process is known as data transport. a. True b. False

True

When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA). a. True b. False

double sided

When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________. a. multiple sided b. substrate c. double sided d. all of the above

False

When using graph coloring, nodes that share the same color cannot be assigned to the same register. a. True b. False

write through

When using the __________ technique all write operations made to main memory are made to the cache as well. a. write back b. LRU c. write through d. unified cache

data-processing instructions

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions? a. data-processing instructions b. branch instructions c. load and store instructions d. extend instructions

all of the above

Which data type is defined in MMX? a. packed byte b. packed word c. packed doubleword d. all of the above

Which digit represents "hundreds" in the number 8732? a. 8 b. 7 c. 3 d. 2

all of the above

Which of the following interrelated factors go into determining the use of the addressing bits? a. number of operands b. number of register sets c. address range d. all of the above

all of the above

Which of the following is a functionally complete set? a. AND, NOT b. NOR c. AND, OR, NOT d. all of the above

all of the above

Which of the following is a fundamental limitation to parallelism with which the system must cope? a. procedural dependency b. resource conflicts c. antidependency d. all of the above

all of the above

Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance? a. duplication of resources b. out-of-order issue c. renaming d. all of the above

all of the above

Which of the following is a true statement? a. a procedure can be called from more than one location b. a procedure call can appear in a procedure c. each procedure call is matched by a return in the called program d. all of the above

7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100)

Which of the following is correct? a. 25 = (2 x 102) + (5 x 101) b. 289 = (2 x 103) + (8 x 101) + (9 x 100) c. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100) d. 0.628 = (6 x 10-3) + (2 x 10-2) + (8 x 10-1)

all of the above

Which of the following memory types are nonvolatile? a. erasable PROM b. programmable ROM c. flash memory d. all of the above

all of the above

Which properties do all semiconductor memory cells share? a. they exhibit two stable states which can be used to represent binary 1 and 0 b. they are capable of being written into to set the state c. they are capable of being read to sense the state d. all of the above

all of the above

Which stage is required for load and store operations? a. I b. E c. D d. all of the above

True

While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur. a. True b. False

flash memory

With _________ the microchip is organized so that a section of memory cells are erased in a single action. a. flash memory b. SDRAM c. DRAM d. EEPROM

unsegmented unpaged memory

With _________ the virtual address is the same as the physical address. a. unsegmented unpaged memory b. unsegmented paged memory c. segmented unpaged memory d. segmented paged memory

True

With a batch operating system the user does not have direct access to the processor. a. True b. False

False

With a daisy chain the processor just picks the interrupt line with the highest priority. a. True b. False

With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0.

False

With asynchronous timing the occurrence of events on the bus is determined by a clock. a. True b. False

State

________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement. a. State b. Memory address c. Micro-op d. Alias register

Logic

________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ. a. Logic b. Arithmetic c. Memory d. Test

DisplayPort

________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. a. DisplayPort b. PCI Express c. Thunderbolt d. InfiniBand

Instruction issue policy

________ is a protocol used to issue instructions. a. Micro-ops b. Scalar c. SIMD d. Instruction issue policy

Read only memory

________ is implemented with combinational circuits. a. Nano memory b. Random access memory c. Read only memory d. No memory

Trap flag

________ is used for debugging. a. Direction flag b. Alignment check c. Trap flag d. Identification flag

Out-of-order completion

________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles. a. In-order completion b. In-order issue c. Out-of-order completion d. Out-of-order issue

Cycle stealing

________ is when the DMA module must force the processor to suspend operation temporarily. a. Interrupt b. Thunderbolt c. Cycle stealing d. Lock down

Constant linear velocity (CLV)

________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center. a. Constant angular velocity (CAV) b. Magnetoresistive c. Constant linear velocity (CLV) d. Seek time

Thrashing

________ is when the processor spends most of its time swapping pages rather than executing instructions. a. Swapping b. Thrashing c. Paging d. Multitasking

Instruction issue

________ refers to the process of initiating instruction execution in the processor's functional units. a. Instruction issue b. In-order issue c. Out-of-order issue d. Procedural issue

Data

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. a. General purpose b. Data c. Address d. Condition code

Organizational

_________ attributes include hardware details transparent to the programmer. a. Interface b. Organizational c. Memory d. Architectural

Soft errors

_________ can be caused by power supply problems or alpha particles. a. Soft errors b. AGT errors c. Hard errors d. SEC errors

Execution sequencing

_________ determines the control and pipeline organization. a. Calculation b. Execution sequencing c. Operations performed d. Operands used

Load-and-store

_________ instructions are used to position quantities in registers temporarily for computational operations. a. Load-and-store b. Window c. Complex d. Branch

Arithmetic

_________ instructions provide computational capabilities for processing number data. a. Boolean b. Logic c. Memory d. Arithmetic

All of the above

_________ is a pipeline hazard. a. Control b. Resource c. Data d. All of the above

Orthogonality

_________ is a principle by which two variables are independent of each other. a. Opcode b. Orthogonality c. Completeness d. Autoindexing

Machine parallelism

_________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions. a. Machine parallelism b. Instruction-level parallelism c. Output dependency d. Procedural dependency

_________ is the fastest available storage device. a. Main memory b. Cache c. Register storage d. HLL

Registers

_________ provide storage internal to the CPU. a. Control units b. ALUs c. Main memory d. Registers

Registers

__________ are a set of storage locations. a. Processors b. PSWs c. Registers d. Control units

Condition codes

__________ are bits set by the processor hardware as the result of operations. a. MIPS b. Condition codes c. Stacks d. PSWs

Hard errors

__________ can be caused by harsh environmental abuse, manufacturing defects, and wear. a. SEC errors b. Hard errors c. Syndrome errors d. Soft errors

Instruction-level parallelism

__________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. a. Flow dependency b. Instruction-level parallelism c. Machine parallelism d. Instruction issue

Displacement addressing

__________ has the advantage of flexibility, but the disadvantage of complexity. a. Stack addressing b. Displacement addressing c. Direct addressing d. Register addressing

Indirect addressing

__________ has the advantage of large address space, however it has the disadvantage of multiple memory references. a. Indirect addressing b. Direct addressing c. Immediate addressing d. Stack addressing

DDR2

__________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. a. DDR2 b. RDRAM c. CDRAM d. DDR3

All of the above

__________ is a design principle employed in designing the PDP-10 instruction set. a. Orthogonality b. Completeness c. Direct addressing d. All of the above

Direct mapping

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line. a. Direct mapping b. Associative mapping c. Set associative mapping d. None of the above

CEA Chapter 12, CEA - UNIT 10, CEA, CEA Chapter 1, CEA Chapter 2, CEA Chapter 3, CEA Chapter 4, CEA Chapter 5, CEA Chapter 6, CEA Chapter 7, CEA Chapter 8, CEA Chapter 9, CEA Chapter 13, CEA Chapter 11, CEA Chapter 14, CEA Chapter 15, CEA Chapter 16

Conjuntos de estudio relacionados

Prep U P1

Fin 3040 exam 1

BA Exam 3 Ch 4

Biology 1406 Chapter 2

Hospitality Law Final

Weathering, Erosion and Deposition

CHEM 237...

English plus 2

fire science chapter 5 fire behavior

ch 9 sb

Word Roots Level 1 Lesson 20

Biology - Chapter 12: DNA Technology - Quiz

PSY Lecture Quiz Questions

C.N.A

chapters 6 landforms exam

MUS 225 Exam 2 Practice Questions

Irregular Verbs (b-k)

JTC-100 Chapter 10 Quiz

Chapter 44: Cardiotonic Agents

Missouri Property and Casualty