Ch.5

Von Neumann Bottleneck

the inability of the sequential one-instruction-at-a-time Von Neumann Model to handle todays large scale problems.

Seek time

time needed to position the Read/Write head to the correct position

Read-Only Memory (ROM)

type of Random Access Memory into which information has been prerecorded during manufacturing. It cannot be modified or removed, only fetched.

MIMD Parallel Processing

a computer system has multiple, independent processors each with its own primary memory unit, and every processor is capable of executing its own separate program in its own private memory at its own rate.

Sequential Execution of Instruction

In which one instruction at a time is fetched from memory and passed to the control unit, where it is decoded and executed

Stored Program Concept

In which the instructions to be executed by the computer are represented as binary values and stored in memory

Volatile Memory

Information disappears when the power is turned off

Nonvolatile Memory

Information is saved between shutdown of the machine

Fetch (address), 3 steps

Load the address into the MAR, Decode the address in the MAR, Copy the contents of that memory location into the MDR.

Store (address, value), 4 steps

Load the address into the MAR, Load the Value into the MDR, Decode the address in the MAR, Store the contents of the MDR into that memory location.

Parallel Processing

Many Processing units operating at the same time.

Memory Units contain 2 Registers

Memory Address Register (MAR), Memory Data Register (MDR)

Arithmetic/Locit Unit (ALU)

is the subsystem that performs such mathematical and Logical operations such as addition, subraction, and comparison for equality

Control Unit task 1- Fetch

retrieve from memory the next instructions to be executed

Register

special high-speed storage cell that holds the operands of an arithmetic operation and that, when the operations is complete, holds its results

Machine Language

the instructions that can be decoded and executed by the control unit of a computer. to perform simple tasks

Nondestructive

the origional contents of the memory cell remain unchanged

Cache Hit Rate

the percent of time the cache is utilized over the RAM

Destructive

the previous contents of the cell are lost

Parallel Algorithm

the study of techniques that make efficient use of parallel architectures, is an important branch of research in computer science.

Latency

time for the beginning of the desired sector to rotate under the Read/Write head

Transfer

time for the entire sector to pass under the Read/Write head and have its contents read into or written form memory

Access time

time it takes to find ay sector

ROM

used to hold important system instructions and data in a place where a user cannot accidentally or intentionally overwrite them.

Random Access Memory (RAM)

what the memory units are frequently refereed to as

Source Cell

where it is now

Destination Cell

where it will go

Use power of ____ for time

10

a computer with 16 bit address has 65,536 Bytes of storage and __________ of memory

64kb

ALU will consist of _____-_____registers to hold all the values

16-128

Use power of ____ for storage

2

Von Neumann Architecture is based on 3 principles

4 major subsystems, Stored Program Concept, Sequential Execution of Instruction.

Average Memory Access Time

5-10 nanoseconds

Cashe Memory is usually _______ times faster than RAM but much smaller, on the order of a few ______ rather than ________

5-10, MB, GB

concept of ___________ is used throughout computer science. (transistors to gates, gates to circuits)

Abstraction

Central Processing Unit (CPU)

ALU and Control Unit are often bundled together

Processor (CPU)

ALU and Control unit are joined together to create a single component

Computer Organization

Branch of computer science that studies computer in terms of their major functional units or subsystems

I/O Controller has a memory location called _____

Buffer

_________ Machines Includes a much larger number of very powerful instructions in the instruction set

CISC Machines

Sum of products algorithm

Circuit construction algorithm that allows us to design circuit.

Multiple Instruction Stream/ Multiple Data Stream (MIMD) Parallel Processing is also called

Cluster Computing

It is the task of the _______________ to fetch and execute instructions

Control Unit

Operation of Fetch. Value=Fetch (address)

Copy the contents of an address and return the contents as a result. Nondestructive Fetch, the origional contents of the memory cell remain unchanged

Machine Language Instructions can be grouped into 4 basic classes

Data Transfer, Arithmetic, Compare, Branch

CISC Machines

Designed to directly provide a wide range of powerful features so that the finished programs for these processors are shorter.

Control Unit task 2- Decode

Determine what is to be done

Mass Storage Systems come in 2 forms

Direct Access Storage Device (DASD), Sequential Access Storage Device (SASD)

Register

Does not have a numeric memory address but are access by a special register designator, such as A, X, R

SASD

Does not require that all units of data identifiable via unique addresses

Grid Computing

Enables researchers to easily and transparently access unused computer facilities without regard for their location. like renting out your home or car when its not being used.

Control Unit task 3- Execute

Execute it by using the appropriate command to the ALU, Memory, or I/O controllers

2 basic memory operations

Fetch and Store

Control Unit. (Has 3 Tasks)

Fetch, Decode, Execute.

RAM consists of 3 charatoristics

Memory is dived into cells and each cell has its own unique address. Address consists of unsigned integers from 0-max. the time it takes to fetch or store the contents of a single cell is the same for all cells in memory.

4 Major Subsystems

Memory, Input/Output, Arithmetic/ Logic Units (ALU), and the Control Units.

Mass Storage Systems (Data Centers)

Nonvolatile storage such as disks, flash drives, tapes and servers

Register

Not used for general purpose storage but for specific purposes such as holding operands for an upcoming arithmetic computation

Bus

Path for electrical signals

Control Unit relies on 2 special Registers called _________ and _________ and on a __________ circuit.

Program Counter (PC), Instruction Register(IR), Instruction Decoder Circuit.

__________ Machines designing instruction sets to make them as small and as simple as possible

RISC Machines

what are the 2 approaches to designing instruction sets

Reduced Instruction Set Computers (RISC Machines), Complex Instruction Set Computers (CISC Mashines)

ALU is made up of 3 parts, which together create the Data path

Register, Interconnecitons between components, ALU circuitry

Memory locations in 2 dimensions start with the

Row designation.

Principle of Locality

Says that when the coputer uses something it will probably use it again very soon

Magneti Disk

Sectors, stores information in these units.

Acess time = _________ + _________ + __________

Seek time, Latency, Transfer

Stored Program

Sequence of machine language instructions stored as binary values in memory

Interrupt Signal

Special hardware signal sent to the processor when the I/O operation is done

Condition Codes

Special set of bits inside the processor

Condition codes are special set of bits inside the processor often called _________ or _________

Status Register, Conditin Register

Operation of Store Store (Address, value)

Store the specified value into the memory cell specified. Destructive store, the previous contents of the cell are lost

Von Neumann Architecture

Structure and organization of virtually all modern computational devices

Cache Memory

The first time a computer references a piece of data, it should copy that data from the RAM memory to a special, high speed memory Unit.

Instruction Set

The set of all operations that can be executed by a processor. (every processor is different)

Arithmetic

These operations cause the ALU to perform a computation.

Compare

These operations compare two alues and set an indicator on the basis of the results of the compare

Data Transfer

These operations move information between or within the different components of a computer

RISC Machines

This approach minimize the amount of hardware circuitry needed to build a processor.

Fetch/Store Controller

This unit determines whether we put the contents of a memory cell into the MDR, or put the contents of the MDR into the memory cell

Memory Access Time

Time it takes to carry out a fetch or store operation. (which is the same for all 2^n addresses)

Range of addresses available on a computer is ________

[0.......(2^n-1)]

Random Acess

an access technique the computer memory uses

Input/Output (I/O) Units

are the devices that allow a computer system to communicate and interact with the outside word as well as store information for the long term

Address Fields

are the memory addresses of the values on which this operation will work

Status Register and Condition Register

bits are set aside by the compare operations. 3 1-bit operations. (GT, EQ, LT)

Memory Width (cell size)

bits per cell. Usually denoted as W. Standard cell size is universally a Byte

Register

can be accessed much more quikly than reguar memory cells because there are only a few of them. 5-10 times faster.

MDR

contains the data value being fetched or stored. Size, usually multiles of 8, typically 32 bit and 64 bit This allows us to fetch, in a sing step, either integer or real value respectivly

DASD

every unit of information still has a unique address, but the time needed to access it depends on its physical location and current state of the device

Instruction Register (IR)

holds a copy of the instructions just fetched from memory

MAR

holds the address of the cell to be accessed. must be N bits wide, wehre 2^n is the address space of the computer

Program Counter (PC)

holds the address of the next instruction to be executed.

Operation Code (Op Code)

is a unique unsigned integer value assigned to each machine language operation recognized by the hardware

I/O Controller is

is like a special purpose computer whose responsibility is to handle the details of input/output and to compensate for any speed difference between the I/O devie and other parts of the compmuter

Momory

is the functional unit of a computer that stores and retrieves instructions and data