Chapter 12 - I/O Systems

Device Status Table

Used to keep track of many I/O requests at the same time; wait queue may be attached to this. Entry for each I/O device - and indicates type, address, and state.

I/O Subsystem

OS is responsible for managing and control I/O operation and devices. Responsible for separating the rest of the kernel from the complexities of managing I/O devices.

Direct Memory Access

For a devices that does LARGE transfers, such as a disk drive, we use a direct memory access controller. To initate a DMA transfer, the host writes a command block into memory. The CPU writes the address of the command block to the DMA controller. The DMA controller proceeds to operate the memory bus directly, place addresses on the bus to perform transfers without the main CPU.

Interrupt Handlers

The address is an offset in a table called the interrupt vector. This vector contains the memory addresses of interrupt handlers. The vector mechanism is to quickly find the addresses and which one needs service (and not reduce the need for a single interrupt handler to search all possible sources of interrupt to determine which one needs service).

Interrupt Request Line

The CPU hardware has a wire called the interrupt request line that the CPU senses after executing every instruction. When the CPU detects a controller has asserted a signal on the interrupt request line, the CPU performs a state save and jumps to the interrupt-handler routine at the fixed address in memory. Interrupt handler performs the processing, performs a state restore, and execute a return from interrupt.

Kernel I/O subsystem Function

-Management of files and devices -Access control to files and devices -Operation control -Device allocation -Buffering, caching, and spooling -I/O scheduling -Device status monitoring, error handling, failrue recovery -Device driver configuration and initalization

Device variation on dimensions

1. Character-stream or block. A character stream transfers bytes one by one; a block transfers blocks of bytes 2. Sequential or random access (we can transfer data in a fixed order by the device or user of a random access device can instruct the device to seek to any of the available data storage location) 3. Synchronous or asynchronous (synchronous performs data transfers with response time; asynchronous ehxihit irregular or unpredictable response times not coordinate with events) 4. Shared or dedicated (sharable device can be used concurrently by several processes ot threads; dedicated cannot) 5. Speed of operation (device speeds ranges from bytes/second to GB/second) 6. Read-write, read only, write-only (some devices perform both input and output; others suppot 1 data transfer direction)

DMA Transfer

1. Device Driver is told to transfer disk data to a buffer at address X 2. Device Driver tells the disk controller to transfer bytes from a disk to buffer at address X. 3. Disk controller initates the DMA transfer 4. Disk controller sends each byte to DMA controller 5. DMA controller transfers byte to buffer X, increasing memory address, and decreasing C 6. When C = 0, DMA interrupts CPU to signal transfer completion.

Interrupt-Handling Features

1. We need the ability to defer interrupt handling during critical processing 2. We need an efficient way to get the proper interrupt handler for a device without first polling all the devices to see which one is raised the interrupt 3. We need multilevel interrupts - so the OS can distinguish between high and low-priority interrupts and can respond with urgency

Controller

A controller is a collection of electronics THAT can operate a port, bus, or device.

Communication between system and device

A device communicates with a computer system by sending signals over cable OR air.

Interrupt-Driven I/O Cycle

A DEVICE controller "raises" an interrupt by asserting a signal on the interrupt request line. The CPU "catches" the interrupt and "dispatches" it to the interrupt handler. The handler "clears" the interrupt by servicing the device. This interrupt mechanisms enables the CPU to respond to an asynchronous event - when a device controller becomes ready.

Kernel I/O subsystem: Buffering

A buffer is a memory area that stores data being transffered between two devices OR between a device and an appliication. 1. It is done for three ways: cope with speed mismatch between a producer and consumer of a data stream; we use it to store the slower device 2. Provide adaptions for devices that have data transfer sizes. -A large message is broken up into small network packets, they are sent in the network. The receiving side places them in a buffer to form an image of the data. 3. To use that the data is NOT changed from an application We copy it to a kernel buffer, and disk write is performed from the buffer onto the disk

Buffer vs. Cache

A buffer may hold the only existing copy of an item. The cache holds data that is stored elsewhere.

Kernel I/O subsystem: Caching

A cache is a region of fast memory that holds copies of data. Access to the cache copy is more efficient than access to the original.

Serial port controller

A serial-port controller is a simple DEVICE controller. It is a single chip in the computer that controls the signals wires of a serial port.

Small Computer System Interface (SCSI)

A small computer systems interface (SCSI) is a standard interface for connecting peripheral devices to a PC

Device Driver

A software program that hides the details and oddities of different devices from the operating system. It presents a uniform interface to the I/O subsystem.

Kernel I/O subsystem: Spooling

A spool is a buffer THAT holds output for a device that cannot accept interleaved data streams. Spooling is a process in which data is temporarily held to be used and executed by a device, program or the system. Data is sent to and stored in memory or other volatile storage until the program or computer requests it for execution

I/O port

An I/O port consists of 4 registers - called the status, control, data-in, data-out 1. Data-In Register: Read by the host to get input 2. Data-Out Register: Written by the host to send output 3. Status Register: Contains bits that can be read by the host. These bits indicates states (e.g. current command has completed, a byte is available to be read from the data-in register) 4. Control Register: Written by the host to start a command or change the mode of a device.

Vectored I/O

Allows one system call to perform multiple I/O operations involving multiple locations.

Non-blocking I/O

An asynchronous call returns immediately, without waiting for the I/O to complete An example is a user interface that receives a keyboard and mouse input, while processing and displaying data on the screen. We can do this through a multithreaded application. In a non-blocking I/O - we do not halt the execution of the appliation for an extended time. It returns quickly, with a return value that indicates bytes transferred. Difference between non-blocking and blocking is that a nonblocking read() returns immediately

Serial Port

An asynchronous port on the computer used to connect a serial device to the computer and capable of transmitting one bit at a time.

Block-device interface

Block-device interface captures all of the aspects necessary accessing disk drives and other block-oriented devices. Device is expected to understand commands like read() and write(), or seek() - which is used in a random access device to specify which block to transfer next.

Clocks and Timers

Computers have hardware clocks and timers that provide 3 function 1. Give the current time 2. Give the elapsed time 3. Set a timer to trigger operation X at time T.

Expansion Bus

Connects relatively slow devices such as keyboard, serial and USB ports.

PCI Bus (common PC system bus)

Connects the processor-memory to fast devices

How does a processor give commands and data to a controller to accomplish I/O transfer?

Controller has ONE or more registers for data and control signals. The processor communicates with the controller by READING and WRITING bit patterns in these registers. Communication can occur through special I/O instruction that specify the transfer of a byte or word to an I/O port address. The I/O instruction triggers triggers bus lines to select the proper device and to move bits into or out of a device register. OR The device controller can support memory mapped I/O. The device control registers are mapped into the address space of the processor. The CPU executes I/O requests using standard data transfer instructions to read and write the device-control registers at their mapped locations in physical memory

How does OS interact with interrupt mechanism?

During boot time, all the interrupt handlers are installed into the interrupt vector. During I/O, device controllers raise interrupts when they are ready for server (e.g. output has completed, input data is available, failure detected) or error like dividing by 0, accessing privilieged instructions. They all require urgent, self-contained routine. Interrupts can be used for paging. System calls execute a software interrupt or error is a trap. Interrupts can be used to manage flow of control within a kernel. We can use this to handle high-priority interrupts, and deal with low-priority tasks after.

Programmable Interval Timer

Hardware to measure elapsed time and trigger operations. It can be set to wait an amount of time and then generate an interrupt

Application I/O Interface

I/O system calls encapsulate device behaviour in generic class. The device-driver layers hides difference among I/O controllers from the kernel. Each OS has its own I/O subsystem structure and device driver frameworks.

Busy Waiting vs. Polling

If a program polls a device say every second, and does something else in the mean time if no data is available it's polling. If the program continuously polls the device (or resource or whatever) without doing anything in between checks, it's called a busy-wait.

Bus

If the devices share a common set of wires, the connection is called a bus. A bus is a set of wires and a rigidly defined protocol that specifies the types of messages that can be sent on the wires. The message conveys through electrical voltages. Buses are widely used in computer architecture and vary in terms of methods, speed, throughput, and connection methods

Kernel I/O subsystem: I/O scheduling

Implement this through a wait queue of requests for each devicce. -When a blocking call is made, request is placed on queue for that device. -I/O scheduler rearranges order of queue to improve system efficiency and average response time.

Polling

Interaction between host and controller is done by bits. The controller indicates its state through the BUSY BIT in status register. The controller sets a busy bit when it is busy working, and clears the busy bit when it is ready to accept the next command The host signals its wishes through the command-ready bit in the command register. The host sets the command-ready bit when a command is available for the controller to execute. Example: Host writes output through a port, coordinating with the controller by handshaking: 1. The host repeatedly reads the busy BIT until the bit is cleared 2. The host SETS the write bit in the command register and writes a byte into the DATA-OUT register 3. The HOST sets the command-ready bit 4. When the controlelr notices the command-ready BIT is set, it sets the busy bit 5. Controller reads the command register, and sees the write command. It reads the data-out register to get the byte and does the I/O for the device. 6. The controller clears he command-ready bit, clears the error-bit to indicate device I/O has succeded and clears the busy bit to indicate it is finished.

Interrupts in Solaris

Interrupt handlers are executed as kernel threads - a range of high priorities is reserved for these threads. A range of high priorities is reserved for these threads. Solaris preempts low priority interrupt handlers in favour of high priority ones, and the threaded implementation lets us handle interrupt handlers concurrently.

Interrupts in OS

Interrupts are used in OS to handle asynchronous events and to trap to supervisor-mode routines in the kernel. To enable the most urgent work to be done first, modern computers use a system of interrupt priorities. Device controllers, hardware faults, and system calls all raise interrupts to trigger kernel routines.

Memory-Mapped I/O

Memory-mapped I/O uses the same address space to address both memory and I/O devices. The memory and registers of the I/O devices are mapped to (associated with) address values. So when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to memory of the I/O device.

The interrupt-controller hardware

Provides the 3 features. Most CPUs have two interrupt request LINES: 1. Nonmaskable interrupt - cannot be turned off (urgent) 2. Maskable interrupt (e.g. it can be turned off by the CPU before the execution of critical instruction sequences that MUST not be interrupted). This is what device controllers use to request service. The interrupt mechansims accepts an address - a number that selects a specific interrupt handling routine from a small set.

Device Driver Layer

Purpose of this layer is to hide the difference among device controller from the I/O subsytem to the kernel.

Interrupt Chaining

Solves this problem - each element in the interrupt vector points to the head of a list of interrupt handlers. When an interrupt is raised - the handlers on the list is called one by one, until one is found that can service he request (compromise between overhead of a huge interrupt table)

ioctl()

Some OS have a escape that passses command from an application to a device driver. The ioctl() for I/O control - enables an application to access any functionality implemented by any device driver, without need to invent a new system call.

Raw I/o

Some application want to access a block device as an linear array of blocks.

Direct Virtual Memory Access

Some computer use physical memory addresses for DMA. We use DVMA for virtual addresses that undergo a transition to physical addresses. They can perform a transfer between two memory-mapped devices without the CPU or main memory.

Port

The device communicates with the machine through a connection point or port (serial port)

SCSI Bus Controller

The protocol is complex, and this bus controller is implemented as a separate circuit board (or host adapter) that plugs into the computer. It contains a processor, microcode, and some private memory to enable it to process SCSI protocol messages. Some devices have their own built-in controller. A disk drive has a circuit board attached, and the board is the disk controller. It implements the disk side o the protocol for a connection (e.g. SCSI or Serial Advanced Technology Attachment).

Interrupt Priority Levels

These levels enable the CPU to defer the handling of low-priority interrupts WITHOUT masking all the interrupts and makes it possible for a high-priority interrupt to preempt the execution of a low-priority interrupt.

PCI Express (PCIe)

This bus is used to interconnect main parts of a computer with throughput up to 16 GB per second

HyperTransport

This bus is used to interconnect parts of a computer with throughput up to 25 GB/second

Graphic Controller

This controller has I/O ports for basic control operations; the controler memory mapped region to hold screen contents. The process sends output to the screen by writing data into the memory-mapped region. Controller generates the image.

Busy Waiting or Polling

This is when the host is in a loop, reading the status register over and over until the busy bit becomes clear. If the controller and device are fast, this method is reasonable. If the wait is long, the host should switch to a task. Polling is inefficient when it is attempted repeatedly BUT finds rarely finds a device ready for service, while other CPU processing is undone. A host knows when the controller is idle when it receives an interrupt

Processes and Device Controllers

We don't want processes to access low-level operations on hardware; we want to protect memory. While high performance, it interferes with system security.

Programmed I/O

We use a processor to watch status bits and to feed data into a controller register 1 byte at a time.

Daisy Chain

When a device A is plugged into a device B which is plugged into a device C, which is connected to the computer, this arrangement is a daisy chain. A daisy chain usually operates as a bus

Blocking System Call

When an application issues a blocking system call - the execution of an application is suspended. It is moved from the run queue to the WAIT queue. After the system call completes, the application is moved back to the run queue, where it resumes execution. Control does not return to the application until I/O is complete.

Cycle Stealing

When the DMA controller seizes the memory, the CPU is prevented from accessing main memory for a second, but access data items in primary and secondary caches.

Handshaking & DMA controller and Device Controller

When two device issue communications. We handshake between DMA controller and device controller through a pair of wires called the DMA-request and DMA-acknowledge. We place a signal on the DMA-request wire when a word of data is available for transfer. This requests causes the DMA-acknowledge to get a memory bus, place the address on the memory address wire, and place a signal on the DMA-acknowledge signal. When the transfer is done, the DMA controller interrupts the CPU.

Memory-Mapped Device Register

While it is efficient in terms of writing bytes, one issue that is an incorrect pointer to an unintended region of memory can cause accidental modification.

Serial ATA (Serial Advanced Technology Attachment or SATA)

is a standard for connecting and transferring data from hard disk drives (HDDs) to computer systems. It has a microcode, processor to do many tasks like buffering, cachine, and bad-sector mapping.