Chapter 19: Translation Lookaside Buffers

What information is in a TLB?

- A TLB is fully associative. - Each entry contains the VPN, PFN and other bits. - Other bits include: i) a valid bit: indicates whether the entry has a valid translation or not. ii) protection bits: determines how a page can be accessed iii) address space identifier, dirty bit etc.

What is a TLB?

- A TLB is part of the chip's memory-management unit (MMU), and is simply a hardware cache of popular virtual-to-physical address translations. - Upon each virtual memory reference, the hardware first checks the TLB to see if the desired translation is held. If so, the the translation is performed quickly without having to consult the page table.

Why do we use caches?

- Caches are used to take advantage of locality in instructions and data references. - TLB's rely on both spatial and temporal locality for success, which are program properties. - If a program exhibits such locality (many programs do), the TLB hit rate will likely be very high.

What is the primary advantage of software-managed TLB's?

- Flexibility: the OS can use any data structure it wants to implement the page table, without requiring a hardware change. - Simplicity: the hardware doesn't do much on a miss, just raise an exception

What does it mean to exceed TLB coverage?

- If the number of pages a program accesses in a short period of time exceeds the number of pages that fit into the TLB, the program will generate a large number of TLB misses. This is referred to as exceeding the TLB coverage.

Why don't we have much larger caches to get even more benefits?

- If we want a fast cache, it has to be small, otherwise issues like speed of light and other physical constraints become relevant. - Any large cache is slow, and defeats the purpose.

In the olden days, was a TLB miss handled by the hardware of the software (OS)?

- In the olden days, the hardware had complex instruction sets (CISC), thus the hardware would handle the TLB miss entirely. - To do this, the hardware had to know exactly where the page tables are located in memory, as well as there exact format, this was done via a page table register. - The hardware would: i) "walk" the page table ii) find the correct page table entry iii) extract the desired translation iv) update the TLB with the translation v) retry the instruction.

How do modern architectures handle a TLB miss?

- More modern architectures are RISC and have a software-managed TLB. - On a TLB miss, the hardware raises an exception, which pauses the current instruction stream, raises the privilege level to kernel mode and jumps to a trap handler. - This trap handler is code within the OS that is written to handle TLB misses. - The code will: i) look-up the translation in the page table ii) use special privileged instructions to update the TLB iii) return from trap - At this point the hardware retries the instruction, resulting in a TLB hit.

What is a TLB hit rate?

- The TLB hit rate is the number of TLB hits divided by the number of total memory accesses.

Why is the TLB valid bit useful?

- The TLB valid bit is especially useful when performing context switches. - By setting all TLB entries to invalid, the system can ensure that the soon-to-be running process does not accidentally use a translation from a previous process.

How does the page size affect TLB performance?

- The larger the page size, the better the TLB performance, because there are more memory accesses to the same page frame.

How is the return from trap instruction different for a TLB miss exception?

- When returning from a TLB miss handling trap, the hardware must resume execution at the instruction that caused the trap. This retry thus lets the instruction run again, this time resulting in a TLB hit. - Thus depending on how an exception was caused, the hardware must save a different PC when trapping into the OS, in order to resume properly when the execution of the program continues.

What is cache replacement?

- When we are installing a new entry in a cache, when the cache is full, it is necessary to replace an old one.

What is spatial locality?

- With spatial locality, the idea is that is a program accesses memory at address x, it will likely soon access memory near address x.

What is temporal locality?

- With temporal locality, the idea is that an instruction or data item that has been recently accessed will likely be re-accessed soon in the future.

CISC

Complex Instruction Set Computer

Give an example of an older architecture that used hardware-managed TLB's.

Intel x86 architecture

What is the difference between a TLB valid bit and a PT valid bit?

Page Table Valid Bit: --------------------- - When a PTE is marked invalid, it means that the page has not yet been allocated by the process, and should not be accessed by a correctly working program. - When an invalid page is accessed, an exception is raised, and the offending program will likely be terminated. TLB Valid Bit: ------------- - A TLB valid bit refers to whether a TLB entry has a valid translation within it. - An initial state for each TLB entry is to be set to invalid, because not address translations have been cached yet. - Once programs start running and accessing their virtual address spaces, the TLB is slowly populated, thus valid entries fill the TLB.

RISC

Reduced Instruction Set Computer

What is the overhead associated with a TLB miss versus a TLB hit?

TLB hit: -------- - If translations are found in the cache, little overhead is added, because the TLB is found near the processing core and is designed to be quite fast. TLB miss: ---------- - When a miss occurs, the high cost of paging is incurred. - The page table must be accessed to find the translation, resulting in an extra memory reference. - If this happens, the program will run noticeably more slowly because memory accesses are quite costly compared to most other CPU instructions.

TLB

Translation Lookaside Buffer

Describe the steps in the address translation algorithm when using a TLB.

i) First, extract the virtual page number from the virtual address. ii) check if the TLB holds the translation for the VPN. if it does (TLB hit)... iii) we can now extract the page frame number from the TLB entry, concatenate the offset from the original virtual address and form the desired physical address. if not (TLB miss)... iii) the hardware accesses the page table to find the translation. iv) assuming the virtual memory reference generated by the process is valid and accessible, the TLB is update with the translation. v) once the TLB is updated, the hardware retries the instruction, this time the translation is found in the TLB and the memory reference is processed quickly.

What are some replacement policies used by the TLB?

i) LRU: least recently used - LRU assumes that an entry that has not been recently used is a good candidate for eviction ii) Random Policy - Evicts a TLB mapping at random

How can the TLB handle context switches?

i) flush the TLB on context switches, thus emptying it before running the next process. - For a software-managed TLB this would mean using a privileged hardware instruction, that simply sets all valid bits to 0. - There is a cost, each time a process runs it must incur a TLB misses as it touches its data and code pages. ii) Address Space Identifiers (ASID) - The ASID is used to differentiate otherwise identical translations. - The OS must, on a context switch, set some privileged register to the ASID of the current process to tell the hardware which process is currently running.

How can the OS be sure that when handling a TLB miss an infinite chain of TLB misses will not occur?

i) you could keep TLB miss handler in physical memory, where they are unmapped and thus not subject to address translation. ii) reserve some entries in the TLB for permanently valid translations, and use some of those permanent slots for the handler code.