Computer Arch TEST 2

RAID 1

- In (???), redundancy is achieved by duplicating all the data. - Data striping is used. Each logical strip is mapped to two separate physical disks so that every disk in the array has a mirror disk that contains the same data. - Advantages: A read request can be serviced by either of the two disks that contains the requested data. A write request requires that both corresponding strips be updated, but this can be done in parallel. However, there is no write penalty. Recovery from a failure is simple. When a drive fails, the data may still be accessed from the second drive. - Disadvantages: The principal disadvantage of (???) is the cost; it requires twice the disk space of the logical disk that it supports. - Applications: System software and data and other highly critical files. - Applications: Accounting; Payroll; Financial - In a transaction-oriented environment, (???) can achieve high I/O request rates if the bulk of the requests are reads. (???) may also provide improved performance over RAID 0 for data transfer intensive applications with a high percentage of reads. Improvement occurs if the application can split each read request so that both disk members participate.

Multiple interrupt lines

- Provide multiple interrupt lines between the processor and the I/O modules. - However, it is impractical to dedicate more than a few bus lines. - Hence, even if multiple lines are used, it is likely that each line will have multiple I/O modules attached to it. Thus, one of the other three techniques must be used on each line.

RAID 5

- RAID __ distributes the parity strips across all disks. - Advantage: The distribution of parity strips across all drives avoids the potential I/O bottleneck found in RAID 4. - Applications: File and application servers; Database servers; Web, e-mail, and news servers

RAID 2

- RAID levels __ and 3 make use of a parallel access technique. In a parallel access array, all member disks participate in the execution of every I/O request. Typically, the spindles of the individual drives are synchronized so that each disk head is in the same position on each disk at any given time. - An error-correcting code such as Hamming Code is stored along with data bits. - Data striping is used. In the case of RAID __ and 3, the strips are very small, often as small as a single byte or word. - Disadvantage: Although (???) requires fewer disks than RAID 1, it is still rather costly. The number of redundant disks is proportional to the log of the number of data disks. - On a single read, all disks are simultaneously accessed. On a single write, all data disks and parity disks must be accessed for the write operation. - Applications: Environment in which many disk errors occur. No commercial implementations exist / not commercially viable.

RAID 4, 5 6 (common attributes)

- RAID levels __ through __ make use of an independent access technique. In an independent access array, each member disk operates independently, so that separate I/O requests can be satisfied in parallel. - Because of this, independent access arrays are more suitable for applications that require high I/O request rates and are relatively less suited for applications that require high data transfer rates. - Data striping is used. Strips are relatively large.

RAID 3

- Similar to RAID 2, RAID __ employs parallel access, with data distributed in small strips. - Instead of an error-correcting code, a simple parity bit is computed for the set of individual bits in the same position on all of the data disks. - RAID (?) requires only a single redundant disk, no matter how large the disk array. - In the event of a drive failure, the parity drive is accessed and data is reconstructed from the remaining devices. Once the failed drive is replaced, the missing data can be restored on the new drive and operation resumed. - Because data are striped in very small strips, RAID (?) can achieve very high data transfer rates. Any I/O request will involve the parallel transfer of data from all of the data disks. - Disadvantage: Only one I/O request can be executed at a time. Thus, in a transaction-oriented environment, performance suffers. - Applications: Video production and live streaming; Image editing; Video editing; Prepress applications

Bus arbitration

- This method also uses the vectored interrupt technique. - With this method, an I/O module must first gain control of the bus before it can raise the interrupt request line. Thus, only one module can raise the line at a time. - When the processor detects the interrupt, it responds on the interrupt acknowledge line. The requesting module then places its vector on the data lines.

Software poll

- When the processor detects an interrupt, it branches to an interrupt-service routine whose job it is to poll each I/O module to determine which module caused the interrupt. - The poll could be in the form of a separate command line (e.g., TESTI/O). In this case, the processor raises TESTI/O and places the address of a particular I/O module on the address lines. The I/O module responds positively if it set the interrupt. - Alternatively, each I/O module could contain an addressable status register. The processor then reads the status register of each I/O module to identify the interrupting module. Once the correct module is identified, the processor branches to a device-service routine specific to that device. - The disadvantage of the software poll is that it is time consuming.

RAID 4

- With RAID (?), a bit-by-bit parity strip is calculated across corresponding strips on each data disk, and the parity bits are stored in the corresponding strip on the parity disk. - Disadvantage: RAID 4 involves a write penalty when an I/O write request of small size is performed. Every write operation must involve the parity disk, which therefore can become a bottleneck. - Applications: No commercial implementations exist / not commercially viable

NAND flash memory

-- Logical organization: resembles NAND logic devices -- Basic unit of access: 16 or 32 bits -- Access type: Does NOT provide a random access, reads/writes in small blocks, each block holds 100s/1000s of bits, provides higher bit density than NAR flash and greater write speed -- Applications: Used in USB flash drives, memory cards and in SSDs

NOR flash memory

-- Logical organization: resembles a NOR logic device -- Basic unit of access: bit -- Access type: High speed random, read and write to specific locations, and can reference/retrieve a single byte -- Applications: used to store cell phone operating system code and on Windows computers for BIOS program that runs a startup

Hamming code

(???) is an error detecting and error correcting code. Hamming codes can detect up to two-bit errors or correct one-bit errors.

RAID 6

- RAID (?) distributes the parity strips across all disks. - Two different parity calculations are carried out and stored in separate blocks on different disks. Thus, a RAID (?) array whose user data require N disks consists of N+2 disks. This makes it possible to regenerate data even if two disks containing user data fail. - Advantage: RAID (?) provides extremely high data availability. - Disadvantage: RAID (?) incurs a substantial write penalty, because each write affects two parity blocks. - Applications: mission critical applications

38400 bps = 38400/8 = 4800 chars/sec (Assuming 1 char = 8 bits) Processor speed = 4 MIPS = 4x106 instructions/sec = 4000000 fetch would be reduced to 4x106 - 4800 = 3995200 Hence, the processor would be slowed down due to DMA activity. Percentage of processor speed reduction is 4800 / 4000000 *100 = 0.12%

A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 38400 bps. The processor is fetching instructions at the rate of 4 million instructions per second (4 MIPS). By how much will the processor be slowed down due to the DMA activity?

Just something you might need to know...

CD-ROM disk contains a single spiral track, beginning near the center and spiraling out to the outer edge of the disk. Sectors near the outside of the disk are the same length as those near the inside. Thus, information is packed evenly across the disk in segments of the same size and these are scanned at the same rate by rotating the disk at a variable speed. Data is then accessed at a constant linear velocity (CLV).

The effectiveness of data striping in RAID 0 for - A single process requests large data sets

If the application requests large amounts of logically contiguous data, compared to the size of a strip, then a single I/O request involves the parallel transfer of data from multiple disks, which increases the effective transfer rate compared to a single-disk transfer.

The effectiveness of data striping in RAID 0 for - Multiple processes request several small sized data

If the strip size is relatively large, so that a single I/O request only involves a single disk access, then multiple waiting I/O requests can be handled in parallel, reducing the queuing time for each request. This improves I/O response time and facilitates high I/O execution rates.

Memory-mapped I/O

- A single address space for memory locations and I/O devices - The processor treats the status and data registers of I/O modules as memory locations and uses the same machine instructions to access both memory and I/O devices. - A single read line and a single write line are needed on the bus. - For example, with 10 address lines, a combined total of 210 = 1024 memory locations and I/O addresses can be supported, in any combination. - For most types of processors, there is a relatively large set of different instructions for referencing memory. Hence the advantage of memory-mapped I/O is that the large set of instructions can be used, allowing more efficient programming. - Disadvantage is that valuable memory address space is used up to address I/O devices.

Isolated I/O

- Address space for I/O is isolated from that for memory - Bus is equipped with memory read and write plus input and output command lines. - Command line specifies whether the address refers to a memory location or an I/O device. - Full range of addresses may be available for both memory and I/O devices. - For example, with 10 address lines, 1024 memory locations and 1024 I/O addresses can be supported. - Disadvantage: If isolated I/O is used, there are only a few I/O instructions, as compared to memory-mapped I/O method.

Hardware poll

- Also referred as 'Daisy Chain' method - More efficient technique, compared to software poll - For interrupts, all I/O modules share a common interrupt request line. The interrupt acknowledge line is daisy chained through the modules. - When the processor senses an interrupt, it sends out an interrupt acknowledge. This signal propagates through a series of I/O modules until it gets to a requesting module. The requesting module typically responds by placing a word on the data lines. This word is referred to as a vector and is either the address of the I/O module or some other unique identifier. - Processor uses the vector as a pointer to the appropriate device-service routine. This avoids the need to execute a general interrupt-service routine first. This technique is called a vectored interrupt.

RAID 0

- Data are striped across the available disks. - Advantage of this layout is that if a single I/O request consists of multiple logically contiguous strips, then individual strips for that request can be handled in parallel, greatly reducing the I/O transfer time. - If the typical request is for large amounts of logically contiguous data, compared to the size of a strip, then a single I/O request involves the parallel transfer of data from multiple disks, increasing the effective transfer rate compared to a single-disk transfer. - If the strip size is relatively large, so that a single I/O request only involves a single disk access, then multiple waiting I/O requests can be handled in parallel, reducing the queuing time for each request. - Applications in which performance and capacity are primary concerns and low cost is more important than improved reliability. - Applications: Video production and editing; Image Editing

Processor speed = 3 MIPS = 3x106 instructions/sec = 3000000 Background tasks run 96% of the time. i.e. only 4% of the time available to execute I/O operations. = 4/100*3000000 = 120000 I/O instructions/sec a. As each word transfer requires 3 instructions, maximum I/O data transfer rate = 120000 / 3 = 40000 words/sec. b. Available machine cycle = 4% x 3MIPS x 5 CPI = 600000 machine cycles Available machine cycles = 96% x 3MIPS x 2 CPI = 5760000 Total I/O data transfer rate = 600K + 5760K = 6360000 words/sec

A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a max of 3 MIPS. An average instruction requires 5 machine cycles, 3 of which use the memory bus. A memory read/write operation uses 1 m/c cycle. Suppose that the processor is continuously executing "background" programs that require 96% of the instruction rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is used to transfer very large amounts of data between M and D. a. If programmed I/O is used and each one word transfer requires the processor to execute 3 instructions, estimate the max I/O data transfer rate in words/sec possible through D. b. Estimate the same rate if DMA is used.

Double-Data-Rate SDRAM (DDR-SDRAM)

A new version of SDRAM, that can send data twice per clock cycle, once on the rising edge of the clock pulse and once on the falling edge.

Synchronous DRAM (SDRAM)

exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

Dynamic RAM (DRAM)

is made with cells that store data as charge on capacitors. Because capacitors have a natural tendency to discharge, (?) require periodic charge refreshing to maintain data storage.

Optically Erasable Programmable Read-Only Memory (EPROM)

is read and written electrically. However, before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. This erasure process can be performed repeatedly; each erasure can take as much as 20 minutes to perform. Thus, the (?) can be altered multiple times and holds its data virtually indefinitely.

Phase-Change RAM (PRAM)

is recommended for standard interface or storage memory applications because of its non-volatility, relatively fast operational speed, and scalability. It basically applies two phases of chalcogenide materials: the amorphous phase with high resistance and the crystal phase with low resistance. Controlling the write voltage and time can reversibly transform the written data from amorphous phase to the crystalline phase. The read data is the result of sensing the resistance difference between the two phases.

In a typical SDRAM

it exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. With synchronous access, SDRAM moves data in and out under control of the system clock. The processor or other master issues the instruction and address information, which is latched by SDRAM. SDRAM then responds after a set number of clock cycles. Meanwhile, the master can safely do other tasks while SDRAM is processing the request.

Resistive RAM (ReRAM)

operation is mainly field-induced ion migration and hence has a relatively slow speed and limited endurance, relatively good data retention and a simple cell structure that is easy to manufacture. It has reliability advantages, low operation voltage, and random access, its power consumption is higher because it has fewer parallel working cells.

USB

short for Universal Serial Bus, is an industry standard developed in the mid-1990s that defines the cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices.

In a typical DRAM...

the processor presents addresses and control levels to the memory, indicating that a set of data at a particular location in memory should be either read from or written into the DRAM. After a delay, the access time, the DRAM either writes or reads the data. During the access-time delay, the DRAM performs various internal functions, such as activating the high capacitance of the row and column lines, sensing the data, and routing the data out through the output buffers. The processor must simply wait through this delay, slowing system performance.

STT-MRAM

uses tunneling resistance that depends on the relative magnetization directions of ferromagnetic electrodes.6-8 It is an attractive memory option because of its superior scalability, speed, and power consumption. Depending on the writing technique, MRAM is classified as either field switching or spin-transfer torque (STT) MRAM, the latter type being of more interest because of its simple structure and excellent scalability.

even parity bit

In the case of (???) parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to 1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value remains 0.

odd parity bit

In the case of (???) parity, the situation is reversed. Instead, if the sum of bits with a value of 1 is odd, the parity bit's value is set to zero. And if the sum of bits with a value of 1 is even, the parity bit value is set to 1, making the total count of 1's in the set an odd number.

interleaved memory

Main memory is composed of a collection of DRAM memory chips. A number of chips can be grouped together to form a memory bank. It is possible to organize the memory banks in a way known as (???). Each bank is independently able to service a memory read or write request, so that a system with K banks can service K requests simultaneously, increasing memory read or write rates by a factor of K. If consecutive words of memory are stored in different banks, then the transfer of a block of memory is speeded up.

Tracks

On a magnetic disk, data is organized on a platter in a concentric set of rings, each (???) is the same width as the head. There are thousands of (???) per surface. Adjacent (???) are separated by gaps.

transfer time

Once the head is in position, the read or write operation is then performed, i.e. data is transferred, as the sector moves under the head. The time required for the transfer is referred as the (???).

rotational delay

Once the track is selected, the disk controller waits until the appropriate sector rotates to line up with the head. The time it takes for the beginning of the sector to reach the head is known as (???)

Burst Mode

SDRAM employs a (?) to eliminate the address setup time and row and column line pre-charge time after the first access. In burst mode, a series of data bits can be clocked out rapidly after the first bit has been accessed. This mode is useful when all the bits to be accessed are in sequence and in the same row of the array as the initial access.

cylinder

Some disk drives accommodate multiple platters stacked vertically a fraction of an inch apart. Multiple arms are provided. Multiple-platter disks employ a movable head, with one read-write head per platter surface. All of the heads are mechanically fixed so that all are at the same distance from the center of the disk and move together. Thus, at any time, all of the heads are positioned over tracks that are of equal distance from the center of the disk. The set of all the tracks in the same relative position on the platter is referred to as a (???)

• Bits are packed more closely on a DVD using a laser with shorter wavelength. • DVD employs a second layer of pits and lands on top of the first layer. A dual layer DVD has a semi-reflective layer on top of the reflective layer, and by adjusting focus, the lasers in DVD drives can read each layer separately. This technique almost doubles the capacity of the disk. • DVD-ROM can be two sided, whereas data are recorded on only one side of a CD.

DVD's greater capacity is due to three differences from CDs

Sector

Data are transferred to and from the disk in (???). There are typically hundreds of (???) per track, and these may be of either fixed or variable length. In most contemporary systems, fixed-length (???) are used, with 512 bytes being the nearly universal (???) size.

constant angular velocity (CAV)

Data is stored on a magnetic disk / hard drive in concentric tracks. Data on tracks is accessed at the same rate by rotating the disk at a fixed speed, known as (???). With CAV system, number of bits per track is constant.

Interrupt Driven I/O

The processor issues I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter is ready to exchange data with the processor. The processor then saves the current execution state on stack, executes the data transfer as before, and then restores the execution state from stack and resumes its former processing. This is more efficient as it eliminates needless waiting by processor, which is free to execute other instructions while I/O module performs data transfer (read/write) operation with the slow peripheral device. A disadvantage is that the processor is responsible for extracting data from main memory for output and storing data in main memory for input.

access time

The sum of the seek time and the rotational delay equals the (???), which is the time it takes to get into position to read or write.

Direct Memory Access (DMA)

Unlike Programmed, and Interrupt-Driven I/O, (???) does not involve the processor. The I/O module and main memory exchange data directly without processor involvement.

The processor may perform background activity which does not need the active use of bus while DMA is busy performing data transfer using bus. Otherwise, the processor may be halted in the process of accessing the bus, and must pause completely for one bus cycle. This is much less of a delay, though, than what would be necessary to save the processor's state and move to an IO handler, so the net increase in speed is very good.

When a DMA module takes control of the bus, and while it retains control of the bus, what does the processor do?

seek time

When the disk drive is operating, the disk is rotating at constant speed. To read or write, the head must be positioned at the desired track and at the beginning of the desired sector on that track. The time it takes to position the head at the track is known as (???)

Read-Only Memory (ROM)

contains a permanent pattern of data that cannot be changed. A (?) is nonvolatile, i.e. no power source is required to maintain the bit values in memory.

FireWire

developed as an alternative to SCSI, to be used on smaller systems such as personal computers and servers. The objective was to meet the increasing demands for high I/O rates while avoiding bulky and expensive I/O channel technologies developed for mainframe and supercomputer systems. It uses a daisy chain configuration, with up to 63 devices connected off a single port.

Static RAM (SRAM)

is a digital device and stores binary values using flip-flop logic-gate configurations. (?) holds data as long as power is supplied to it and does not need refresh circuitry.

Electrically Erasable Programmable Read-Only Memory (EEPROM)

is a read-mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. The write operation takes considerably longer than the read operation, on the order of several hundred microseconds per byte. (?) combines the advantage of non-volatility with the flexibility of being updatable-in-place, using ordinary bus control, address, and data lines. (?) is more expensive than EPROM and also is less dense, supporting fewer bits per chip.

Flash memory

is a type of semiconductor memory. It is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, it uses an electrical erasing technology. An entire (???) can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, (???) does not provide byte-level erasure. Like EPROM, (???) uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM.

Parity bit:

or check bit is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd. Parity bits are used as the simplest form of error detecting code.

Programmed I/O

The processor executes a program that gives it direct control of the I/O operation, including sensing device status, sending a read or write command, and transferring the data. When the processor issues a command to the I/O module, it must wait until the I/O operation is complete. If the processor is faster than the I/O module, this is wasteful of processor time. This is a time-consuming process that keeps the processor busy needlessly. Processor performance is severely degraded.