COSC 2425 Chapter 1 -7 Quiz
The logic circuit shown in the diagram directly implements which of the Boolean expressions given below?
((x + y')y + (x + y'))'
The logic circuit shown in the diagram directly implements which of the Boolean expressions given below?
((x + y)'(xy'))'
Consider the postfix (reverse Polish notation) 10 5 + 6 3 - /. The equivalent infix expression is:
(10 + 5)/(6 - 3)
The _____ is the agreed-upon interface between all the software that funs on the machine and the hardware that executes it. It allows you to talk to the machine.
(ISO) Instruction Set Architecture
01AF (base 16) = _____ (base 10)
01AF = (0 × 16³) + (1 × 16²) + (10 × 16¹) + (15 × 16⁰) = 431
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory. Suppose the page size is 2^4 bytes. How many page frames are there in main memory?
16
Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. To which cache block will the memory address 0x13A4498A map?
Block 6
The Boolean AND operation is also known as
Boolean product
Suppose someone writes a program to find the perfect solution to a problem, but it will take 150 years to run. We say that this particular solution is:
Computationally infeasible
In the von Neumann architecture, the central processing unit (CPU) consists of registers, an arithmetic-logic unit (ALU), and a(n) ________.
Control Unit
The _____ is a digital logic component that is often used in computer registers.
D flip-flop
Memory organization has no effect on instruction format.
False
Which MARIE instruction is being carried out by the RTN statement that follows? PC ¬ X
Jump X
The main memory in a desktop personal computer is made of:
RAM
______________are divisions of concentric circles called tracks in disk drives.
Sectors
The offset field of a main memory address is used to determine:
The location of the desired data in the cache block
COLD means
computer output laser disc
the average time required to reach a memory storage location and retrieve its contents is called:
effective access time
The approach of using a combination of memory types to provide the best performance at the best cost is called:
hierarchical memory
When the requested data resides in a given level of memory, we call this a _______.
hit
The ___________ of a machine specifies the instructions that the computer can perform and the format for each instruction.
instruction set architecture
The register that holds the actual data to be read from or written to a given memory address is called:
memory buffer register
The _____ register keeps track of the next instruction to be fetched
program counter
Which of the following of the following types of memory has the shortest (fastest) access time?
registers
There are three basic ISA architectures for internal storage in the CPU:
stack, accumulator, and general-purpose registers
Assembly Language
uses alphabetic (mnemonic) codes in place of binary strings
What characteristic of RAM makes it unsuitable for for permanent storage?
volatile
Write a simplified expression for the Boolean function defined by the following Kmaps.
w'z' + w'y'z' + wyz
The logic circuit shown in the diagram directly implements which of the Boolean expressions given below?
xy+y'
Instruction sets are differentiated by which feature?
All of the choices
The logic circuit shown in the diagram directly implements which of the Boolean expressions given below?
(xy + z')(y + z)'
Consider a 32-bit hexadecimal number stored in memory as follows: (picture on back) If the machine is little endian and the number is an IEEE single-precision floating point value, determine the decimal equivalent of the number stored at address 100 (you may leave your answer in scientific notation form, as a number times a power of two).
+1.00010001100001000101010 x 2 ^ -73
Consider a 32-bit hexadecimal number stored in memory as follows: ( If the machine is big endian and the number is an IEEE single-precision floating point value, determine the decimal equivalent of the number stored at address 100 (you may leave your answer in scientific notation form, as a number times a power of two).
+1.10000100000100000011011 x 2 ^ - 42
The first two bytes of a 2M X 16 main memory have the following hex values Byte 0 is FE Byte 1 is 01 If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if memory is little endian?
+510^10
The first two bytes of a 2M X 16 main memory have the following hex values Byte 0 is FE Byte 1 is 01 If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if memory is big endian?
-511^10
What decimal value does the 8-bit binary number 10110100 have if: it is on a computer using signed - magnitude representation?
-52
What decimal value does the 8-bit binary number 10110100 have if: it is on a computer using one's complement representation?
-75
What decimal value does the 8-bit binary number 10110100 have if: it is on a computer using two's complement representation?
-76
Show how the following floating point values would be stored using IEEE-754 double precision (be sure to indicate the sign bit, the exponent, and the significand fields): it is .75
0 01111111110 1000000...0
Show how the following floating point values would be stored using IEEE-754 double precision (be sure to indicate the sign bit, the exponent, and the significand fields): it is 12.5
0 10000000010 1001000...0
Show how the following floating point values would be stored using IEEE-754 double precision (be sure to indicate the sign bit, the exponent, and the significand fields): it is 26.265
0 10000000011 1010101...0
Convert 0.2578125 to binary with 8 bits to the right of the binary point.
0.2578125 • 2 = 0.515625 == 0 0.515625 • 2 = 1.03125 == 1 1.03125 • 2 = 0.0625 == 0 0.0625 • 2 = 0.125 == 0 0.125 • 2 = 0.5 == 0 0.5 • 2 = 1 == 1 == 0.0100010 (added extra zeros for 8 bits)
Fill in the following table to show how the given integers are represented, assuming 16-bits are used to store values and the machine uses 2's complement notation.
0000000000011100 001C 001C 1C00
Perform the following binary multiplication, assuming unsigned integers: 1011 x 101 -----
00110111
Using the CRC polynomial 1001, create the CRC code word for the information word 01010101.
01010101110
given the following two binary numbers: 11111100 and 01110000, which of these two is the larger when it is being interpreted on a computer using signed - two's complement representation?
01110000
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. Assuming the following page table, answer the questions below:(table on back) What physical address corresponds to the following virtual addresse (if the address causes a page fault, simply indicate this is the case)? 0x00
0x0 = 000 000000 so this address is on page 0, offset 0. Page 0 maps to frame 1. Substituting 01 for 000, we get 01 000000, or 0x10.
Show how the following floating point values would be stored using IEEE-754 double precision (be sure to indicate the sign bit, the exponent, and the significand fields): it is -1.5
1 01111111111 1000000...0
1101101 (base 2) = ______ (base 10)
1 • 2^6 = 64 1 • 2^5 = 32 0 •2^4 = 0 1 • 2^3 = 8 1 • 2^2 = 4 0 • 2^1 = 0 1 • 2^0 = 1 Sum = 109 base 10 Answer: 109
Calculate the overall speedup of a system that spends 40% of its time in calculations with a processor upgrade that provides for 100% greater throughput
1.25
Suppose your company has decided that it needs to make certain busy servers 30% faster. Processes in the workload spend 70% of their time using the CPU and 30% on I/O. In order to achieve an overall system speedup of 30%: How much faster does the CPU need to be?
1.4918
Suppose your company has decided that it needs to make certain busy servers 50% faster. Processes in the workload spend 60% of their time using the CPU and 40% on I/O. In order to achieve an overall system speedup of 25%: How much faster does the CPU need to be?
1.5
Suppose we have a 1024-word memory that is 16-way low-order interleaved. What is the size of the memory address offset field?
10 bits
Subtract the following signed binary numbers as shown using 2's complement arithmetic. 11000100 -00111011 -----------
10001001
728 (base 9) = ______(base 10)
10| 593 10| 59 - Remainder = 3 10| 5 - Remainder = 9 10| 5 - Remainder = 5 Answer: 593
The ASCII code for the letter A is 1000001, and the ASCII code for the letter a is 11000001. Given that the ASCII code for the letter G is 1000111, without looking at Table 2.7, what is the ASCII code for the letter g?
1100111
Perform the following binary divisions, assuming unsigned integers: 11111101 / 1011 --------
11010
Given the following two binary numbers: 11111100 and 01110000 which of these two is the smaller when it is being interpreted on a computer using signed - magnitude representation?
11111100
Given the following two binary numbers: 11111100 and 01110000. Which of these two numbers is the larger unsigned binary number?
11111100
Add the following unsigned binary number as shown. 01000100 + 10111011 ------------
11111111
Fill in the following table to show how the given integers are represented, assuming 16-bits are used to store values and the machine uses 2's complement notation.
1111111111110100 FFF4 FFF4 F4FF
Suppose a disk drive has the following characteristics: • 6 surfaces • 16,383 tracks per surface • 63 sectors per track • 512 bytes/sector • Tract-to-track seek time of 8.5 milliseconds • Rotational speed of 7,200 RPM. What is the access time?
12.67 ms
Suppose we have 1Gx16 RAM chips that make up a 32Gx64 memory that uses high interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these words.) How many RAM chips are necessary?
128
Suppose a disk drive has the following characteristics: • 5 surfaces • 1024 tracks per surface • 256 sectors per track • 512 bytes/sector • Track-to-track seek time of 8 milliseconds • Rotational speed of 7500 RPM. What is the access time?
12ms
Show how the following value would be stored by byte-addressable machines with 32-bit words, using Big endian format. Assume each value starts at address 0x10. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations. 0x14148888
14 14 88 88
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are left for the address part of the instruction?
16
Suppose a computer's control unit consists of a 4-bit counter and a 4 × 16 decoder. What is the maximum number of clock cycles that can be consumed by any instruction?
16
Consider the infix expression: 16/(5+3). the equivalent postfix (reverse Polish notation) expression is:
16 5 3 + /
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields?
17 bits in the tag field, 10 in the block field, and 5 in the offset field
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. How large must the address field be?
18
what decimal value does the 8-bit binary number 10110100 have if: it is interpreted as an unsigned number?
180
Consider a 32-bit hexadecimal number stored in memory as follows: (picture on back side) If the machine is little endian and uses 2's complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex).
1B08C2A2
Suppose your company has decided that it needs to make certain busy servers 50% faster. Processes in the workload spend 60% of their time using the CPU and 40% on I/O. In order to achieve an overall system speedup of 25%: How much faster does the disk need to be?
2
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. How many blocks of main memory are there?
2 ^ 18
Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there?
2 ^ 26
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. How many blocks of main memory are there?
2 ^ 27
The binary string 01000110001000 is a floating point number expressed using the 14-bit simple model given in your text. (There are no implied bits.) What is its decimal equivalent?
2.125
Suppose a disk drive has the following characteristics: • 6 surfaces • 16,383 tracks per surface • 63 sectors per track • 512 bytes/sector • Tract-to-track seek time of 8.5 milliseconds • Rotational speed of 7,200 RPM. What is the capacity of the drive?
2.9 GB
Suppose that a system uses 32-bit memory words and its memory is built from 16 1M × 8 RAM chips. How many address bits are required to uniquely identify each memory word?
22
Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
23 bits in the tag field, 3 in the block field, and 6 in the offset field
Ultra Density Optical disks can store up to __________ and _________ respectively.
23GB and 60GB
Suppose that a system uses 16-bit memory words and its memory is built from 32 1M × 8 RAM chips. How many address bits are required to uniquely identify each memory word?
24
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields?
24 bit addresses with 18 bits in the tag field and 6 in the offset field
If a system's instruction set consists of an 8-bit opcode, what is the maximum number of output signal lines required for the control unit?
256
Suppose a system has a byte-addressable memory size of 256MB. How many bits are required for each address?
28
Consider a 32-bit hexadecimal number stored in memory as follow: (back side picture) If the machine is big endian and uses 2's complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex).
2AC2081B
There are ______ megabytes in a terabyte.
2^10
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. What is the maximum allowable size for memory?
2^16
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. What is the largest unsigned binary number that can be accommodated in one word of memory?
2^24-1
There are _____ kilobytes in a exabyte.
2^50
If the opcodes field for an instruction has n bits, that means there are ____ potential distinct operations.
2^n
The truth table shown below is supposed to reflect the function F(x, y, z) = y(x + z') but two lines are in error. Identify them.
3 and 4
Suppose we have 1Gx16 RAM chips that make up a 32Gx64 memory that uses high interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these words.) How many lines must go to each chip?
30
If a system's instruction set consists of a 5-bit opcode, what is the maximum number of output signal lines required for the control unit?
32
Suppose a computer's control unit consists of a 5-bit counter and a 5 × 32 decoder. What is the maximum number of clock cycles that can be consumed by any instruction?
32
Suppose we have 1Gx16 RAM chips that make up a 32Gx64 memory that uses high interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these words.) Assuming 4 chips per bang, how many banks are required?
32
Suppose we have 1Gx16 RAM chips that make up a 32Gx64 memory that uses high interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these words.) How many bits are needed for a memory address, assuming it is word addressable?
35
67 (base 10) = _______ (base 3)
3|67 3| 22 - Remainder = 1 3| 7 - Remainder = 1 3| 2 - Remainder = 1 3| 2 - Remainder = 2 Answer: 2111
Suppose we have a 4096-word memory that is 64-way high-order interleaved, what is the size of the memory address offset field?
4 bits
Suppose your company has decided that it needs to make certain busy servers 30% faster. Processes in the workload spend 70% of their time using the CPU and 30% on I/O. In order to achieve an overall system speedup of 30%: How much faster does the disk need to be?
4.33333
The binary string 01001010001100 is a floating point number expressed using the 14-bit simple model given in your text. (There are no implied bits.) What is its decimal equivalent?
4.375
A nonpipelined system takes 200ns to process a task. The same task can be processed in a 5-segment pipeline with a clock cycle of 40ns. Determine the speedup ratio of the pipeline for 200 tasks. What is the maximum speedup that could be achieved with the pipeline unit over the nonpipelined unit?
5
How many control lines does a multiplexer have if it has 32 inputs?
5
Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips?
5
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. How large is the opcode field?
5
What decimal value does the 8-bit binary number 10110100 have if: it is on a computer using excess-127 representation?
53
How many inputs does a decoder have if it has 64 outputs?
6
Suppose that a 64MB system memory is built from 64 1MB RAM chips. How many address lines are needed to select one of the memory chips?
6
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory. Suppose the page size is 2^4 bytes. How many entries are there in the page table for a process that uses all of virtual memory?
64
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory. Suppose the page size is 2^4 bytes. How many page frames are there in main memory?
64
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. How large must the register field be?
64
Suppose a disk drive has the following characteristics: • 5 surfaces • 1024 tracks per surface • 256 sectors per track • 512 bytes/sector • Track-to-track seek time of 8 milliseconds • Rotational speed of 7500 RPM. What is the capacity of the drive?
640MB
If a cache access requires one clock cycle and dealing with casche misses requires an additional five clock cycles, which of the following cache hit rates results in an effective access time of 2 clock cycles?
75%
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. To which cache block will the memory address 0x000063FA map?
799
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are needed for the opcode?
8
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. Assuming the following page table, answer the questions below: How many bits are in a physical address?
8
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. How large must the mode field be?
8
Convert the following expressions from infix to reverse Polish (postfix) notation. (8 - 6) / 2
8 6 - 2 /
Show how the following value would be stored by byte-addressable machines with 32-bit words, using little endian format. Assume each value starts at address 0x10. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations. 0x0000058A
8A 05 00 00
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. Assuming the following page table, answer the questions below: (table on back) How many bits are in a virtual address?
9
Transfer rate of a disk drive can be no faster than the bit density (bits / track) times the rotational speed of the disk. Figure 7.15 gives a data transfer rate of 112 GB/sec. Assume that the average track length of the disk is 5.5 inches. What is the average bit density of the disk?
93 B/Track
The logic circuit below is supposed to implement the truth table also shown below. However, one of the components is malfunctioning: It is producing the opposite of its specified output. Which component is defective?
A
Show how the following value would be stored by byte-addressable machines with 32-bit words, using little endian format. Assume each value starts at address 0x10. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations. 0x456789A1
A1 89 67 45
In reverse Polish notation, the expression A*B+C*D is written:
AB*CD*+
Consider the postfix expression: A-B+C*(D*E-F)/(G+H*K). The equivalent postfix (reverse Polish notation) expression is:
AB-CDE*F-* +GHK*+/
The logic circuit below is supposed to be designed to produce the truth table also shown below. However, there is a component missing. Which type of component is missing?
AND
The Boolean expressions x(x + y) = x and x + xy = x are examples of (the):
Absorption Law
Given the instruction set for MARIE in yourtextbook, decipher the following MARIE machine language instruction. (Write the assembly language equivalent.) 0011000000001001
Add 009
_________________ law states the interrelationship of all components with the overall efficiency of a computer system with a simple formula.
Amdahl's
Computer ______________ concerns itself with instruction sets and formats, operation codes, data types, the number and types of registers, addressing modes, main memory access methods, and various I/O mechanisms.
Architecture
The first completely electronic computer was the ________
Atanasoff-Berry Computer
The equation below relates seconds to instruction cycles. What goes in the ???? space?
Average cycles
The logic circuit below is supposed to implement the truth table also shown below. However, one of the components is malfunctioning: It is producing the opposite of its specified output. Which component is defective?
B
Deep Blue beat a human chess Grandmaster using ______ methods.
Brute force
The term endian refers to a computer architecture's:
Byte order
Which of the following types of memory needs to be refreshed periodically to maintain its data?
DRAM
The mechanical computer that included mechanisms that provided memory and an arithmetic processing unit was the:
Difference engine
The first general-purpose programmable electronic computer was the______
ENIAC
Assume a system? 's memory has 128M bytes. Blocks are 64 bytes in length and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set associative cache mapping scheme and byte addressing. Be sure to include the fields as well as their sizes.
Each address has 27 bits, and there are 7 in the tag field, 14 in the set field, and 6 in the offset field.
Accumulator architectures store one operand on the stack and the other in the accumulator.
False
Variable - length instructions are easier to decode than fixed-length instructions
False
Assuming we are using the Hamming algorithm presented in your text and even parity to design an error-correcting code, find the code word to represent the 8-bit information word 01001000.
Given Code: 01001000 For Encoding: P1: P2: d1: 0 P4: d2: 1 d3: 0 d4: 0 P8: d5: 1 d6: 0 d7: 0 d8: 0 P1:
In RAID-2, the error-correction information generated in additional drive is using_________.
Hamming code
Convert 0B2C (base 16) to binary.
Hexadecimal Binary 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 0B2C => 0 in binary is 0000 => B in binary is 1011 => 2 in binary is 0010 => C in binary is 1100 so, 0B2C in binary is 0000101100101100
____________ follows closely behind the CPU and memory in determining the overall effectiveness of a computer system.
I/O
The large computer systems use an intelligent type of DMA interface known as ______________
I/O channel
The organization that sets standards from computer components, signaling protocols, and data representation is the:
IEEE
The Organization the sets standards for photographic film and the pitch of screw threads, in addition to matters concerning computers, it the:
ISO
The Boolean expressions, xx = x and x + x = x, are examples of (the):
Idempotent Law
Cloud storage is a limited form of ____________.
Infrastructure as a Service (IaaS)
Given the instruction set for MARIE in yourtextbook, decipher the following MARIE machine language instruction. (Write the assembly language equivalent.) 1001000000001011
Jump 00B
26. Which MARIE instruction is being carried out by the RTN that follows? MAR - X MBR - M[MAR] AC - MBR
Load X
The RTN for the first step in the fetch-decode-execute cycle is:
MAR ¬ PC
___________ is the oldest and most cost-effective of all mass-storage devices .
Magnetic tape
. ______________ devices offer another approach to transcend the limits of magnetic storage.
Micro-electro-mechanical
The state machine shown below is an example of a(n):
Moore Machine
We study computer ___________ to become familiar with how circuits and signals collaborate to create working computer systems.
Organization
Many desktop computers utilize the ___________ bus standard in which the system augments its main bus with dedicated I/O buses using expansion slots.
Peripheral component Interconnect
Systems that require high availability and must be able to tolerate more than one concurrent drive failure use________________.
RAID 6
_______ memory allows data to be both read from and written to easily and rapidly.
RAM
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. To which cache block will the memory address 0x01D872 map?
Since it's associative cache, it can map anywhere
Given the instruction set for MARIE in yourtextbook, decipher the following MARIE machine language instruction. (Write the assembly language equivalent.) 0010000000000111
Store 007
Which MARIE instruction is being carried out by the RTN that follows?
StoreI X
The ____ connects the CPU to memory.
System bus
Cache mapping is necessary because:
The address generated by the CPU must be converted to a cache location.
Cognitive Computing can make inferences within a problem's context using hard facts and incomplete information
True
In high-order memory interleaving, the high-order bits of the memory address are used to select the memory bank.
True
Short instructions are typically better because they take up less room and can be fetched quickly.
True
Fixed-length instructions:
Waste space but are fast and perform better than variable length instructions
Convert the following expressions from reverse Polish notation to infix notation. X Y Z + V W - * Z + +
X + ((Y + Z) * (V - W) + Z)
The Boolean function F(x, y) = x'y + xy' + (x'+y')(xy) can be simplified to:
XY
A stack-organized computer uses _______ addressing.
Zero
A "store" statement is an example of:
a data movement instruction
A "jump" statement is an example of:
a transfer of control instruction
A computer bus consists of data lines, _____, control lines, and power lines
address lines
A "subtract" statement is an example of:
an arithmetic operation
The ratio of horizontal pixels to vertical pixels that a monitor can display is its _____ ratio.
aspect ratio
Memory that is accessed by searching for content is called:
associative memory
Electrical signal loss over time or distance during data transfer is called an ________.
attenuation
If, after fetching a value from memory, we discover that the system has returned only half of the bits that we expected; it is likely that we have a problem with:
byte alignment
_______ memory is a small, high-speed, high-cost memory that servers as a buffer for frequently accessed data.
cache
CCW means ______________
channel command words
The ______ is responsible for fetching program instructions, decoding each one, and performing the indicated sequence of operations.
control unit
Clock speeds in today's microprocessors are measured in ________ .
gigahertz
Information can be retrieved fastest from:
hard disk
If a read/write head in Rigid Disk Drives were to touch the surface of the disk, the disk would become unusable. This condition is known as a _________
head crash
A major advantage of direct mapped cache is its simplicity and ease of implementation. The main disadvantage of direct mapped cache is:
its performance is degraded if two or more blocks that map to the same location are used alternately.
Lineal spaces between the pits in a CD-ROM are called ____________
lands
Example of secondary memory include:
magnetic disk drives and solid state memory
The register that holds the address of the data to be transferred is called:
memory address register
General-purpose architectures are divided into three groups:
memory-memory, register-memory, and load-store
Computer chips having multiple processing units on a single chip are _____ architectures.
multicore
Cache memory is effective because:
of the principle of locality
To carry out a binary arithmetic operation, an accumulator architectures uses _____ operand(s).
one
The __________ is a group of bits that tells the computer to perform a specific operation.
opcode
This common method used to increase CPU throughput can result in destructive overheating of the CPU:
overclocking
________ allow movement of data to and from devices external to the computer
ports
Consider a 32-bit hexadecimal number stored in memory as follows: (picture on back side) If the machine is big endian and the number is an IEEE single-precision floating point value, is the number positive or negative?
positive
Consider a 32-bit hexadecimal number stored in memory as follows: (picture on back) If the machine is little endian and the number is an IEEE single-precision floating point value, is the number positive or negative?
positive
The signals exchanged between a sender and a receiver is called a ________.
protocol
Examples of hazards in pipelines sinclude:
resource conflicts, data dependencies, and conditional branch statements
A simpler and more elegant approach is memory-mapped I/O because I/O devices and main memory share the ____________________.
same address space
Which of the following types of memory has the longest (slowest) access time?
secondary memory
The extra line used for synchronization in parallel data transmission is called a _____________.
strobe
Buses having memory on its own do memory transfer _________________
synchronously
Big data is measured in ______________ bytes.
tera
Cache memory is typically positioned between:
the CPU and RAM
Holographic data storage stores enormous data density by using _______________.
three-dimensional medium
Cache replacement policies are necessary:
to determine which block in cache should be the victim block
Write a simplified expression for the Boolean function defined by the following Kmaps.
wy ' + w 'x'yz
Write a simplified expression for the Boolean function defined by the following Kmaps.
wy' + y'z + w'xy + x'yz'
Write a simplified expression for the Boolean function defined by the following Kmaps.
x + y'z'
The logic circuit shown in the diagram directly implements which of the Boolean expressions given below?
x' (x+y)
Write a simplified expression for the Boolean function defined by the following Kmaps.
x' + xy'z'
Find the minimized Boolean expression for the function defined by the truth tables provided below.s.
x'y'z + w
Which of the following equations correctly reflects the truth table shown below?
x'yz' + x'yz + xy'z' + xyz' + xyz
Find the minimized Boolean expression for the function defined by the truth tables provided below:
x'z' + xz
The complement, F', of F(x, y, z) = (x' + yz)(xy' + z) (not simplified) is:
x(y' + z') + z'(x' + y)
The Boolean function F(x, y) = x'y' + x'y + xy' is equivalent to:
x+y