CS061 Quizzes

In order to overcome the gate delay problem of the simple ripple-carry adder circuit, we can design an adder with the following design improvement:

"Recursively" pre-calculate the carry bit for each digit.

The total "number of numbers" representable by a 24-bit binary word (using conventional abbreviations) is:

16M

A microprocessor's Instruction Set Architecture specifies, among other things, which higher level languages can be used to program it.

False

Convert the 8-bit two's complement number 1000 1111 into decimal

-113

What is the decimal equivalent of the IEEE-754 binary floating point number (as hex) xC1080000

-8.5

What range of numbers is represented by a 10-bit number using the unsigned magnitude representation (i.e. representing "natural" or counting numbers)?

0 to 1023

How many outputs does a multiplexer with 8 data inputs have?

1

Represent the hex word xAC9F as a binary word:

1010 1100 1001 1111

Convert the decimal 3,297 to 12-bit unsigned magnitude binary

1100 1110 0001

Convert the number -41 into 8-bit two's complement binary representation:

1101 0111

In the LC-3, the DR decoder input comes from the DRMUX. What are the two inputs to the DRMUX? Hint: think subroutines

111 and IR11:9

For the following four questions: An ISA specifies a word size of 4 bytes, byte addressability, and an address space of 16 M What is the total size of the memory in bytes?

16 Mbytes

For the following four questions: An ISA specifies a word size of 8 bytes, byte addressability, and an address space of 256 K; it uses single-word instructions (i.e. each instruction is a single 8 byte word). What is the size of the MAR?

18 bits

For the following four questions: An ISA specifies a word size of 8 bytes, byte addressability, and an address space of 256 K; it uses single-word instructions (i.e. each instruction is a single 8 byte word). What is the size of the PC?

18 bits

How many outputs does a full adder circuit have?

2

A simplified garage door controller can be described by the following rules: The system is controlled by a single-button clicker. • If the door is fully OPEN or fully CLOSED, clicking the button will cause the door to move down/up respectively, until it completes the cycle of closing or opening. • The CC ("cycle complete") sensor is true when the door is either stopped at the top, or stopped at the bottom. • If the door is currently opening or closing, clicking the button will make the door stop in place. When clicked again, the door will move in the opposite direction, until cycle complete, or until the button is clicked again (i.e. the system needs to know if it was interrupted while going up, or interrupted while going down). The motor is controlled by a 2-bit control signal: U and D: • {U,D} = {0,0} => motor stopped • {U,D} = {1,0} => door moving up • {U,D} = {0,1} => door moving down • {U,D} = {1,1} => to be avoided! This simplified system does not incorporate the standard safety mechanism of halting a closing door if a light beam is interrupted: don't use it for your own garage😊 Sketch the FSM diagram of this system, then answer the following questions: How many control signals are involved in this system (how many inputs, how many outputs)?

2 inputs, 2 outputs

For the following four questions: An ISA specifies a word size of 4 bytes, byte addressability, and an address space of 16 M How many bits are used for addresses?

24 bits

How many trap service routines could theoretically be created for the LC-3, given the format of the TRAP instruction? (hint: how many bits are used for the trap vector?)

256

How many input lines do you need for a decoder with 7 output lines?

3

How many select lines does a multiplexer with 8 data inputs have?

3

A state machine with 7 states has two external inputs and three external outputs. Answer the following questions with regards to this state machine: How many rows does the truth table for this state machine have?

32

For the following four questions: An ISA specifies a word size of 4 bytes, byte addressability, and an address space of 16 M How many bits are in a word?

32 bits

What logic components are used to make a 4-bit register?

4 D-Latches

How many distinct truth tables could be constructed for 5 independent variables?

4G

How many state bits are necessary for a state machine with 18 states?

5

A state machine with 7 states has two external inputs and three external outputs. Answer the following questions with regards to this state machine: How many colums does the truth table have for outputs?

6

A simplified garage door controller can be described by the following rules: The system is controlled by a single-button clicker. • If the door is fully OPEN or fully CLOSED, clicking the button will cause the door to move down/up respectively, until it completes the cycle of closing or opening. • The CC ("cycle complete") sensor is true when the door is either stopped at the top, or stopped at the bottom. • If the door is currently opening or closing, clicking the button will make the door stop in place. When clicked again, the door will move in the opposite direction, until cycle complete, or until the button is clicked again (i.e. the system needs to know if it was interrupted while going up, or interrupted while going down). The motor is controlled by a 2-bit control signal: U and D: • {U,D} = {0,0} => motor stopped • {U,D} = {1,0} => door moving up • {U,D} = {0,1} => door moving down • {U,D} = {1,1} => to be avoided! This simplified system does not incorporate the standard safety mechanism of halting a closing door if a light beam is interrupted: don't use it for your own garage😊 Sketch the FSM diagram of this system, then answer the following questions: How many states comprise this FSM, and how many bits will the storage component of the FSM need to store (i.e. what is the size of a state label)?

6 states, 3 bits

A "gate delay" can be described as the time needed for the output of a gate to "settle" to its correct level after one of its inputs has been changed. The full-adder circuit we have designed would therefore result in a gate delay of 2 units (ignoring the NOT inputs for the moment). How many units of gate delay would a 32-bit ripple-adder display?

64

For the following four questions: An ISA specifies a word size of 8 bytes, byte addressability, and an address space of 256 K; it uses single-word instructions (i.e. each instruction is a single 8 byte word). What is the size of the IR?

8 Bytes

For the following four questions: An ISA specifies a word size of 4 bytes, byte addressability, and an address space of 16 M How many bits are in any value of the memory?

8 bits

For the following four questions: An ISA specifies a word size of 8 bytes, byte addressability, and an address space of 256 K; it uses single-word instructions (i.e. each instruction is a single 8 byte word). What is the size of the MDR?

8 bytes

What is decimal result of adding the two's complement numbers 110 + 0101 0101?

83

A label in assembly language code is:

A symbolic representation (i.e. an "alias") of a memory location

Which of the following is NOT a characteristic of finite state machines?

An explicit set of accept states

The next three questions relate to the following LC-3 code fragment (the hex values in the first column give the address at which the corresponding instruction is stored): xB824 LDI R3, pointer ...... xB920 pointer .FILL x6000 ...... Given: Mem[x6000] = xA429; Mem[xA429] = x0FFF The instruction at address xB824 can be replaced by the pair of instructions LEA R6, pointer LDR R3, R6, #0

False

What logic circuit would you use for addressing memory?

Decoder

The DR decoder input comes from the DRMUX. What are the two inputs to the DRMUX?

IR11:9 and 111

In the LC-3, the SR1 decoder input comes from the SR1MUX. What are the two inputs to the SR1MUX? Hint: think store instructions

IR11:9 and IR8:6

In the LC-3, the SR1 decoder input comes from the SR1MUX. What are the two inputs to the SR1MUX? (Hint: think about the Store instructions)

IR8:6 and IR11:9

Some microprocessor instructions use an addressing mode called Immediate. In this mode where is the operand stored?

Inside the instruction itself

How does the control unit decide whether to take the branch pointed to in a BR instruction? (n, z & p represent IR [11:9]; N, Z & P represent the condition code registers)

LD.PC = n.N + z.Z + p.P

Construction of an LC-3 instruction (Instruction Register fields): opcode: [15:12] Destination register/Source register/condition code test (nzp): [11:9] Source Register 1/Base Register: [8:6] Source Register 2: [2:0] PCoffset9: [8:0] PCoffset11: [10:0] Offset6: [5:0] Imm5: [4:0] trapvec8: [7:0] Mode flags: [11], [5] What is the Register Transfer description of the following LC-3 instruction? STR SR, BaseReg, Offset6

Mem[ (BaseReg) + SEXT(IR5:0) ] <- (SR)

You have to implement a digital circuit module that can perform either of two possible operations: output = a + b; or output = a + c where a, b, c and output are all 16-bit 2's complement numbers, and the operation + is 2's complement addition (not OR). Which of the following circuits would you use to make the selection between inputs b and c?

Multiplexer

The next three questions relate to the following LC-3 code fragment (the hex values in the first column give the address at which the corresponding instruction is stored): xB824 LDI R3, pointer ...... xB920 pointer .FILL x6000 ...... Given: Mem[x6000] = xA429; Mem[xA429] = x0FFF Which of the condition code registers will be set following the operation?:

N

The LC-3 does not have a bitwise OR instruction, so we need to write code that will perform that operation. Which of the following snippets of LC-3 assembly code would reproduce an instruction of the format: OR R3, R1, R2 ; i.e. write the bitwise OR of {R1, R2} into R3

NOT R1, R1 // NOT R2, R2 // AND R3, R1, R2 // NOT R3, R3

What is the logic expression for the truth table shown here, in the form Out = f(A, B, C)?

OUT = A. B. C. + A' B' C'

In the LC-3 data path, the output of the address adder goes to both the MARMUX and the PCMUX, potentially causing two very different register transfers to take place. Why does this not happen?

Only one of the two subsequent control signals (Gate.Marmux and LD.PC) will be asserted.

Assembly language instructions can be grouped into three categories. These are:

Operations, data movement and control

A student writes the following LC-3 AL code to output the character value '&' stored at a remote address, the value of which is stored at label pointerA (address x302A): labelA LEA R6, pointerA LDR R0, R6, #0 OUT The student has followed instructions and opened the text window. What will this code do?

Ouptut '&' to console

In the LC-3, address calculations are performed by an address adder which adds an offset to an existing 16-bit address, with one multiplexer selecting one of two possible "base addresses", and another multiplexer selecting one of 4 possible offsets. Which are the two possible base addresses, i.e. the sources of the 16-bit address inputs?

PC and SR1

What is the Register Transfer description of the LC-3 instruction JSRR?

R7 <- (PC); PC <- (BaseReg)

What is the Register Transfer description of the LC-3 instruction JSR?

R7 <- (PC); PC <- (PC) + SEXT(IR10:0)

What is the Register Transfer description of the LC-3 instruction TRAP?

R7 <- (PC); PC <- Mem[ ZEXT(IR7:0) ]

Which of the following are components used to build circuits for state machines?

Registers, AND gates, and OR gates

One of the four values of ALUK, the control signal to the LC-3 ALU, selects the ALU action "pass-through input A" - i.e. input A is connected directly to the output. Which of the following instructions would use this control signal?

ST, STI & STR

What inputs are given to the combinational logic of a state machine?

The inputs and current state

Given the following code, and given that a) the current value in r1 is #72 (decimal 72); b) the instruction at B has just been executed, with the result that the value 0 was stored to R6: A ADD r1, r1, r2 B ADD r6, r6, #-1 ; "#-1" means decimal negative 1 BRnp A X NOT r6, r6 Y HALT After the BR instruction, what instruction will be executed next?

X

Simplify the boolean expression a + a'.b

a + b

The next question refers to the von Neumann model of computing. The Instruction Register is:

a register that stores the instruction currently being executed

The next question refers to the von Neumann model of computing. The Program Counter is:

a register that stores the memory address of the next instruction

.ORIG x3000 LEA R1, label1 LD R2, label2 LDI R3, label3 LDR R4, R2, #0 HALT label1 .FILL x4000 ; label1 is an alias for mem. add. x3005 label2 .FILL x4100 ; label2 is an alias for mem. add. x3006 label3 .FILL x4200 ; label3 is an alias for mem. add. x3007 The following memory locations hold the values shown: ADDRESS VALUE x4000 x4100 x4100 x4200 x4200 x4300 After the code has executed, what will be the content of R1?

x3005

Simplify the Boolean expression: a.b'.c'.d + a.b'.c.d + a.b.c'.d + a.b.c.d' + a.b.c.d

a.d + a.b.c

What operation(s) will convert the binary representation of a single-digit decimal number into the ASCII code for the corresponding numeric digit? Carefully consider ALL options

add x30 to the binary number or the binary number with the mask x30

A "pseudo-op" (e.g. .ORIG or .FILL) in assembly language code is:

an instruction to the assembler

Given that the ASCII codes for 'A' through 'Z' are x41 through x5A; and the codes for 'a' through 'z' are x61 through x7A: which of the following operations would force the character stored in R0 to upper case - i.e. convert a character stored in R0 from lower case into upper case, or preserve the case if it was upper case already (so 'a' would become 'A', and 'A' would remain unchanged). Note: the LC-3 stores ASCII characters in the lower ("right-hand") byte of a 16-bit word, with the upper byte set to zero.

and R0 with x005F

.ORIG x3000 LEA R1, label1 LD R2, label2 LDI R3, label3 LDR R4, R2, #0 HALT label1 .FILL x4000 ; label1 is an alias for mem. add. x3005 label2 .FILL x4100 ; label2 is an alias for mem. add. x3006 label3 .FILL x4200 ; label3 is an alias for mem. add. x3007 The following memory locations hold the values shown: ADDRESS VALUE x4000 x4100 x4100 x4200 x4200 x4300 After the code has executed, what will be the content of R2?

x4100

Under what circumstances will the addition of two binary numbers in 2's complement representation, one of which is negative and one positive, result in an invalid result?

never

Given that the ASCII codes for 'A' through 'Z' are x41 through x5A; and the codes for 'a' through 'z' are x61 through x7A: which of the following operations would force the character stored in R0 to lower case - i.e. convert a character stored in R0 from upper case into lower case, or preserve the case if it was lower case already (so 'A' would become 'a', and 'a' would remain unchanged). Note: the LC-3 stores ASCII characters in the lower ("right-hand") byte of a 16-bit word, with the upper byte set to zero. This NOT the same question that was on last week's quiz!

or R0 with x0020

In the LC-3 (and other ISAs), the System Control Block, or Trap Vector Table, contains

the starting addresses of the Trap Service Routines

What is the main purpose of the first pass of a two-pass assembler?

to build a symbol table relating labels to memory addresses

The next question refers to the von Neumann model of computing. The main purpose of the control unit is:

to fetch the next instruction from memory & decode it

What data types are implemented natively in the LC-3?

two's complement integer

"Condition Codes" are "flags" used to indicate:

whether the value last stored to a register was positive, negative, or zero

Consider the following LC-3 code fragment (the hex values in the first column give the address to which the corresponding instruction is loaded): x3025 loop1 ADD R4, R5, R6 ..... x30EB BRn loop1 Given that the BR opcode is b0000, what does the instruction at x30EB assemble to? (Note the direction of the branch!)

x0939

.ORIG x3000 LEA R1, label1 LD R2, label2 LDI R3, label3 LDR R4, R2, #0 HALT label1 .FILL x4000 ; label1 is an alias for mem. add. x3005 label2 .FILL x4100 ; label2 is an alias for mem. add. x3006 label3 .FILL x4200 ; label3 is an alias for mem. add. x3007 The following memory locations hold the values shown: ADDRESS VALUE x4000 x4100 x4100 x4200 x4200 x4300 After the code has executed, what will be the content of R4?

x4200

.ORIG x3000 LEA R1, label1 LD R2, label2 LDI R3, label3 LDR R4, R2, #0 HALT label1 .FILL x4000 ; label1 is an alias for mem. add. x3005 label2 .FILL x4100 ; label2 is an alias for mem. add. x3006 label3 .FILL x4200 ; label3 is an alias for mem. add. x3007 The following memory locations hold the values shown: ADDRESS VALUE x4000 x4100 x4100 x4200 x4200 x4300 After the code has executed, what will be the content of R3?

x4300

Represent the binary word 0110 1110 1011 1101 as a hex word:

x6EBD

The next three questions relate to the following LC-3 code fragment (the hex values in the first column give the address at which the corresponding instruction is stored): xB824 LDI R3, pointer ...... xB920 pointer .FILL x6000 ...... Given: Mem[x6000] = xA429; Mem[xA429] = x0FFF What value will R3 contain after the instruction executes?

xA429

Evaluate the bitwise OR expression: xABCD OR x1234

xBBFD

Evaluate the arithmetic addition x4A + x7D

xC7