CS2350 Chapter 4 & 6

Virtual Memory

A method that uses the hard disk as an extension to RAM, thus increasing the available address space a process can use.

Paging

A method used for implementing virtual memory in which main memory is divided into fixed-size blocks (frames) and programs are divided into the same size blocks (pages). The process of copying a virtual page from disk to a page frame in the main memory.

Bus Protocol

A set of usage rules governing how buses are used.

Disk Cache

A specialized buffer used to store data read from disk.

Interrupt

An event that alters (or interrupts) the normal fetch-decode-execute cycle of execution in the system.

System Bus

An internal bus that connects the CPU, memory, and all other internal components.

Backplane Bus

Built into the chassis of the machine and connects the processor, the I/O devices, and the memory (so all devices share one bus).

Cache is often called _______.

CAM (Content Addressable Memory)

Clock Skew

Clock drift: A situation where coordinated clocks in system or network gradually lose synchronization.

Synchronous Buses

Clocked and things happen only at the clock ticks (a sequence of events is controlled by the clock).

Local Buses

Data buses that connect peripheral devices directly to the CPU. High-speed bus, but allow for only a limited number of similar devices.

Distributed Arbitration Using Self-Selection

Devices determine who has the highest priority and who should get the bus.

Centralized Parallel Arbitration

Each device has a request control line to the bus and a centralized arbiter selects who gets the bus. Bottlenecks can result using this type of arbitration.

Distribued Arbitration Using Collision Detection

Each device is allowed to make a request for the bus. If the bus detects any collisions, the device must make another request. (Ethernet uses this type of arbitration.)

Expansion Bus

External bus that connects external devices, peripherals, expansion slots, and I/O ports to the rest of the computer. Slower bus than others, but allow for more generic connectivity.

An interrupt can be triggered for the following reasons:

I/O Requests Arithmetic errors Arithmetic underflow or overflow Hardware malfunction User-defined break points Page faults Invalid instructions Miscellaneous

If the grocery store is main memory, you could consider your refrigerator as the _______ cache and the table the _______ cache.

L2 L1

I/O Buses

Longer than processor-memory buses and allow for many types of devices with varying bandwidths. Compatible with many different architectures.

ROM (Read Only Memory)

Nonvolatile memory that always retains its data.

Processor-Memory Buses

Short, high-speed buses that are closely matched to the memory system on the machine to maximize the bandwidth (transfer data) and are usually design specific.

Segmentation

Similar to paging except that instead of dividing the virtual address space into equal, fixed-size pages, and the physical address space into equal-size page frames, the virtual address space is divided into logical, variable-length units, or segments.

Memory Cache

Smaller and faster than main memory. There are 2 types: Level 1 cache L1 - small, fast memory cache that is built into the microprocessor chip and helps speed up access to frequently-used data. Level 2 cache L2 - a collection of fast, built-in memory chips situated between the microprocessor and main memory.

Cache

Specialized, high-speed storage used to store frequently accessed or recently accessed date. There are 2 types of cache.

Clock Rate

Synchronization by the rate at which the clock ticks. The reciprocal of the bus clock rate.

Cache Coherence Problem

The problem that results when the value stored in cache differs from the value stored in memory.

Cache Mapping

The process of converting a memory address into a cache location.

Bus Arbitration

The process used to determine which device should be in control of the bus.

Clock Speed

The speed of the processor, usually measured in megahertz (millions of pulses per second) or gigahertz (billions of pulses per second).

True or False Cache is not accessed by address, it is accessed by content.

True

True or False Memory Access times are slower than the processor speed?

True

Daisy Chain Arbitration

Uses a "grant bus" control line that is passed down the bus from the highest priority device to the lowest priority device. This scheme is simple but not always fair.

RAM (Random Access Memory)

Volatile memory that is used to store programs and data on a computer. Each memory location has a unique address.