Digital Circuits Final

Synchronous

operation of flip flops are all synchronized by a common clock

Guidelines for constructing a state graph

1. First, construct some sample input and output sequences to make sure that you understand the problem statement. 2. Determine under what conditions, if any, the circuit should reset to its initial state. 3. If only one or two sequences lead to a nonzero output, a good way to start is to construct a partial state graph for those sequences. 4. Another way to get started is to determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly. 5. Each time you add an arrow to the state graph, determine whether it can go to one of the previously defined states or whether a new state must be added. 6. Check your graph to make sure there is one and only one path leaving each state for each combination of values of the input variables. 7. When your graph is complete, test it by applying the input sequences formulated in part 1 and making sure the output sequences are correct.

Memory

A circuit is said to have memory because its output depends not only on the present inputs, but also on the past sequence of inputs.

Counter

A digital circuit which is used for a counting pulses

Latch

A memory element that has no clock input

Mealy Machine

A state machine whose output is determined by both the sequential logic and the combinational logic of the machine.

Moore Machine

A state machine whose output is determined only by the sequential logic of the machine.

State Table

A table whose entries represent the sequence of individual FF states (i.e., 0 or 1) for a sequential binary circuit.

Edge Triggered

Certain FFs that require a change in the clock signal as a condition for switching states

Ripple Counter

Is two or more logical flip-flops connected sequentially with the input pulses toggling the first one

Moore vs Mealy Circuit

Moore Circuit depends only on flip flops. Mealy circuit is also state-dependent as a function of x.

Characteristic Equations for Flip Flops

Q+ = S + R′Q (SR = 0) (S-R latch or flip-flop) (11-6) Q+ = GD + G′Q (gated D latch) (11-7) Q+ = D (D flip-flop) (11-8) Q+ = D·CE + Q·CE′ (D-CE flip-flop) (11-9) Q+ = JQ′ + K′Q (J-K flip-flop) (11-10) Q+ = T ⊕ Q = TQ′ + T ′Q (T flip-flop) (11-11)

Setup Time

The amount of time that D must be stable before the active edge

Falling Edge

The part of a pulse where the logic level is in transition from a HIGH to a LOW.

Rising Edge

The part of a pulse where the logic level is in transition from a LOW to a HIGH.

Clock Enable

a line to replace a gated clock, lacks the synchronization issues present using gates to synchronize flip flops

Flip Flop

a memory element synchronized to clock input

T Flip Flop

also called the toggle flip-flop, is frequently used in building counters. Most CPLDs and FPGAs can be programmed to implement T flip-flops. The T flip-flop in Figure 11-26(a) has a T input and a clock input. When T = 1 the flip-flop changes state after the active edge of the clock. When T = 0, no state change occurs.

Load

alternate signal in normal clock gate, =0, holds present value

Signal Tracing

analyze the circuit to determine the flip-flop state sequence and the output sequence by tracing the 0 and 1 signals through the circuit.

Counter Design

circuit design using basic memory properties of flip flops

Clock

common timing signal used to change flip flops

Register

consists of a group of flip-flops with a common clock input.

D Flip Flop

has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change in D.

Gated Latch

have an additional input called the gate or enable input. When the gate input is inactive, which may be the high or low value, the state of the latch cannot change. When the gate input is active, the latch is controlled by the other inputs and operates as indicated in the preceding section.

JK Flip Flop

is an extended version of the S-R flip-flop. Unlike the S-R flip-flop, a 1 input may be applied simultaneously to J and K, in which case the flip-flop changes state after the active clock edge.

Asynchronous

operation of flip flops are not all synchronized by a common clock, some signals may be out of sync

General Model for Mealy and Moore

p. 433 and p.435

Minimum Clock Period

shortest change period for clock state that will work for the circuit

Timing Diagram

shows the state changes for input, output, and clock of a circuit

Shift

signal to apply to binary register to transfer binary data right or left

SR Flip Flop

similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge. The truth table and characteristic equation for the flip-flop are the same as for the latch, but the interpretation of Q+ is different. For the latch, Q+ is the value of Q after the propagation delay through the latch, while for the flip-flop, Q+ is the value that Q assumes after the active clock edge.

State Graph

state table which represents the behavior of the circuit

Hold Time

the amount of time that D must hold the same value after the active edge

Clock Skew

the difference in the arrival time of the clock edges to two flip-flops

Feedback

the output of one of the gates is connected back into the input of another gate in the circuit so as to form a closed loop.