Digital Design Interview Review
Hexadecimal
- A base-16 number system that uses sixteen distinct symbols 0-9 and A-F to represent numbers from 0 to 15. - 123 = (1 * 16^2) + (2 * 16^1) + (3 * 16^0) = 291 - Good for representing a large amount of data
Parity Bit
- A bit that is added at the end of a binary string. - Can indicate whether the number of bits having a value 1 in the string is even/odd - Simplest form of error detection - Can be found by taking XOR of all bits in a string - Up to designer if they want to use an odd/even parity
Buffer
- A gate that passes its input to the output, unchanged. - Use cases include: synchronizing n-signals by introducing delay, signal amplification by taking "weak" source signal and boosting its capacity to drive a load - "Transparent Gate"
P-N Junction
- Boundary between two types of semiconductor metals. Created by "doping" - p - positive side, excess holes - n - negative side, excess electrons
Hold Time Constraint
- Depends on minimum delay from register R1 through combinational logic. Input to register R2 must be stable for at least t_hold AFTER the clock edge. - Hard to fix hold time after manufacturing, requires circuit modification.
(Verilog) Difference between logical equalities and logical case equalities
- Equality operators return logical 1 or 0. - Operands are compared bit by bit - Logical case inequality allows for checking of x and z values (Not synthesizable!)
(Verilog) Blocking Assignment
- Evaluation and assignments happen immediately - Used in combinational logic - Ex: x = a | b; y = a & b; z = x | y;
(Verilog) Non-Blocking Assignment
- Evaluation and assignments wait until the right side of the statement is determined, then the left - Used in sequential logic - Ex: x <= a | b; y <= a & b; z <= x | y;
Asynchronous Counter
- FF's connected in a way that the outputs of one drive the clock of the next one - FF's NOT clocked simultaneously - Circuit is simple for large designs - Slow du to clock propagation through all FF's
Synchronous Counter
- FF's driven by clock individually - FF's clocked simultaneously - Complicated circuit given large designs - High speed due to same clock
Delay Sources
- Fundamentally caused by capacitance and resistance of a circuit - Rising and Falling signals - Process Variation (variation in the attributes of transistors during fabrication) - Temperature changes - Age of citcuit
NOR
- Gate that produces a 1 only when all the inputs are 0. - Universal Gate
NAND
- Gate that produces a 1 when it is NOT AND. - Universal Gate
Product-Of-Sums
A form of Boolean expression that is basically the AND'ing of OR'ed terms. All output entries that are equal to 0 in the truth table are grouped together. Terms are called maxterms. ex: (A + B + C) * (B + C)
Sum-Of-Products (SOP)
A form of Boolean expression that is basically the OR'ing of AND'ed terms. All output entries that are equal to 1 in the truth table are grouped together. Terms are called minterms ex: ABC + BC + C
NOT (Inverter)
A gate that inverts the output.
Truth Table
A logic function table that specifies all cases of inputs and outputs for a circuit. Illustrates complete functionality.
XNOR
A logic gate that produces a LOW output only when its two inputs are at opposite levels. Use case: Comparator
Path Sensitization
A path is sensitized when it follows a logic signal to propagate along with it.
Static Sensitization
A path where the other incoming signals to the gate of that path have a non-controlling value
(Verilog) Synchronous Reset
A design that samples the reset on a clocks edge.
(Verilog) Asynchronous Reset
A design that samples the reset without a clock.
Logic Gate
an elementary building block of a digital circuit. Performs basic digital operations.
JK Flip Flop
- Gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1". - Most universally used. - Generally leads to simpler circuits due to many dont care values for flip flop inputs to achieve next state from a present state
(Verilog) Difference between LOGICAL and BITWISE operations
- Logical - result in logical 1, 0, or x - Bitwise - result in bit-by-bit value
D Flip Flop (FF)
- Memory element that is edge-triggered, driven by a CLK signal. Built from two back to back latches with opposite polarity clocks, which form a master slave topology. - Each flip flop can carry 1 bit of information. Ex: 32-bit register requires 32 flip flops. - Generally simpler to implement - Other Flip Flops include: D Flip Flop, JK Flip Flop, T Flip Flop, SR Flop Flop
Mealy Machine Characteristics
- Outputs depend on BOTH CURRENT STATES & INPUTS - Less states than Moore - Reacts in the same clock cycle - More difficult to design
Moore Machine Characteristics
- Outputs depend only on CURRENT states - Generally has more states than Mealy - Generally reacts one clock - Easier to design
(Verilog) Common Bitwise Operators
- Performs bitwise operations on two operands ~ - Bitwise Negation (NOT) & - Bitwise AND | = Bitwise OR ^ - Bitwise XOR ^- or -^ - Bitwise XNOR
Clock Skew
- Phenomenon in which synchronous circuits arrive at different components in different times. - Caused by material imperfections - temperature variations - varied wire length - Setup and hold violations - Positive clock skew - transmitting register gets the clock tick earlier than the receiving register - Negative clock skew - receiving register gets the clock tick earlier than the sending register - Positive skews can help fix setup violations, but cause hold violations - Negative skews can fix hold violations, but cause setup violations
(Verilog) Concatenation Operator
- Provides a way to append busses or wires to make busses - Must be sized ex: y = {b, c} // concatenate wires b and c to make a bus y
(Verilog) Common Logical Operators
- Return a logical 1 or 0. - Take variables or expressions as operators ! - Logical Negation (NOT) && - Logical AND || - Logical OR == - Logical Equality != - Logical Inequality === - Logical case equality !== - Logical case inequality
Ring Counter
- Shift register in which the output of the last flip-flop is connected to the input of the first flip-flop - Synchronized
Slack
- Slack at vertex v is the difference of RAT and AAT of v. Determines if the design is working at the specified speed or frequency. A negative slack means a circuit doesn't meet timing constraints, but a positive one does. Aim to achieve a slack closest to 0. - Slack(v) = RAT(v) - AAT(v)
Propagation Delay
- T_pd : MAXIMUM time from when an input changes until output FINISHES TO CHANGE it's output. - Total T_pd is the sum of propagation delays through each element on the CRITICAL (longest) path.
Octal
- The octal number system is base 8, using only digits 0 through 7. - Not commonly used
Field-Effect Transistor (FET)
- Transistor that uses a voltage to control current in a semiconductor. - Source, Gate, Drain
Race Condition
- When an output has an unexpected dependency on the timing of a different event. - Hardware race condition or Simulation induced race condition
Calculating Critical Path
1) Create DAG on the circuit 2) Compute AAT and RAT, and calculate the Slack. 3) Determine the critical path
Functional Analysis
1) Detect a critical path using topological analysis 2) Determine logic values that are necessary for static sensitizability of the critical path
Steps in a typical ASIC/SOC
1) Specification - important parameters 2) High Level design - design architecture is defined 3) Low level design - microarchitecture (muxes, registers) 4) RTL Coding - HDL modeling using synthesizable constructs 5) Functional Verification - verifying properties, input driven 6) Logic Synthesis - compiler takes RTL and maps to technology primitives 7) Place and Route - Gate level netlist from synthesis is taken and placed 8) Fabrication - GDS file is sent to foundry which fabricates silicon 9) Post Silicon Validation - Chip put in a real test environment and tested
GDS file (GDSII)
A binary database file format which is an industry standard for layout artwork
Multiplexer
A combinational logic block that allows one of its inputs to be routed to a single output. A 2^n mux requires n-selection bits.
Overlapping/Nonoverlapping Sequence Detector
A sequence detector capable of detecting overlapping/nonoverlapping sequences
Finite State Machine
A synchronous sequential circuit that has a finite number of states.
Tri-State Inverter (E-INV)
A type of gate that behaves like an inverter. when EN = 1, the output is inverted. When EN = 0, its output is disconnected and results in high-impedance.
Complimentary Metal Oxide Semiconductor (CMOS)
A way of constructing MOSFETS in a way they compliment each other to form logic gates - A voltage of LOGIC HIGH ranges from 3.5v to 5v - A voltage of LOGIC LOW ranges rom 0v to 1.5v.
Actual Arrival Time (AAT)
AAT of a vertex v is the longest path from source to v.
Mealy Machine
An FSM where the output depends on both INPUTS & CURRENT STATES. Outputs are only valid at the pos/neg transition of clock.
Karnaugh Map (K-Map)
An illustrated way to minimize combinational logic functions. SOP - logic 1 are circled. POS - logic 0 are circled.
Glitches
An unwanted transition when an input transition causes multiple output transitions. Prevent these by adding extra groups to avoid intergroup transitions.
Grey Code
Binary number system where two successive values differ only in 1 bit. Advantages over Binary Code - fewer bits toggling means less power consumption - facilitate error correction since only 1 bit changes at a time
Carry-Look Ahead Adder (CLA)
Cascaded configuration of multiple one-bit full adders where the Carry-In bits to all full-adders are available simultaneously. For n-bit CLA, the propagation delay is 2n + 2 gate delays.
Ripple-Carry Adder (RCA)
Cascaded configuration of multiple one-bit full adders where the n-bits are inputted to the FA n, and each Carry-Out is wired to the next adders Carry-Out. Slower, but smaller. The result of the RCA is valid only after the joint propagation delays of all the FA's are finished. For an n-bit RCA, the propagation delay is n gate delays.
Synchronous Sequential Circuit
Circuit in which changes in state memory are synchronized by a common clock
Combinational Circuit
Combination of logic gates that its output depends only on its current inputs
One-Bit Half Adder
Combinational logic block that adds the contents of A, B, without taking a Carry-In. Outputs a 1 bit sum and Carry-Out(Cout).
One-Bit Full Adder
Combinational logic block that adds the contents of its 3 inputs, A, B, and Carry-In (Cin) and outputs a 1-bit sum and Carry-Out(Cout)
Decoder
Combinational logic block that receives n inputs and produces a 2^n decoded output.
ASIC (Application Specific Integrated Circuit)
Component designed for a specific application and is used by specific companies in a specific system for a specific use.
Metastability
Condition a FF can enter when the setup or hold times are violated in which the output is indeterminate (neither High nor Low) for usually a short period of time
Setup Time Constraint
Depends on the maximum delay from register R1 through combinational logic. Input register R2 must be stable at least tsetup BEFORE clock edge May increase clock period to fix setup time after manufacturing. Design performance determined by critical path.
Topological Timing Analysis
Determines if a circuit will operate correctly at the intended clock frequency. Allows us to determine how to improve timing of the circuit.
Ring Oscillator
Device composed of an ODD number of NOT gates whose outputs oscillates between two voltage levels.
Contamination Delay Clock-to-Q (t_cq)
Earliest time after the clock active edge that the output (Q) starts to change
Hardware Race Condition
Example : an SR latch where both inputs = 1, we would obtain an oscillating output value for Q and Q'. Solution: Use enable/control signals
Software Induced Race Condition
Example: two always blocks where the first always block executes before the second one, which results in 1. If second executes before first, results in 0. Solution: Use non-blocking assignments instead of blocking assignments
Moore Machine
FSM where outputs depend on ONLY current states. Outputs are valid only AFTER transition of state.
Overflow Flag
Flag that indicates the SIGNED result is too large to fit in the n-bit output. Find the overflow by Cout XOR Cn-1. Meaningless when UNSIGNED numbers are added or subtracted.
XOR
Gate that produces a 1 exclusively if one or the other input has a 1.
AND
Gate that produces a 1 only when all inputs are 1.
OR
Gate that produces a 1 when any input has a 1.
State Diagram
Graphical form that represents the behavior of a synchronous sequential circuit
Dont' Cares
Indicated by X in a truth table or K-map that can be either a 0 or 1. Used to represent an output value that is unimportant, and useful for logic minimization.
Propagation Delay Clock-to-Q (t_pq)
Latest time after the clock active edge that output (Q) stops changing
Hold Time (t_h)
Minimum amount of time AFTER clocks active edge by which the input (D) must be stable.
Setup Time (t_s)
Minimum amount of time BEFORE clocks active edge by which the input (D) must be stable.
D Latch
Most basic memory element. Level sensitive, and takes EN as an input and not a CLK signal. Asynchronous.
Combinational Circuit Delay
Outputs always change with some amount of delay from the input.
What does the output of a sequential circuit depend on?
Past and present inputs. AKA uses memory.
Subtractors
Performed by using two's complement. First, compliment one of the adder inputs (1s compliment), and then adding 1 to the LSB.
What does the output of a combinational circuit depend on?
Present inputs only.
Required Arrival Time (RAT)
RAT of a vertex v is the latest time that the signal is allowed to leave v to make it to sink in time.
Sequence Detector
Sequential circuit that outputs 1 when a particular pattern of bits sequentially arrives at its input.
Register
Sequential logic block made up of Flip Flops that can hold data perpetually until power is off.
Counter
Special form of register designed to count up/down at each rising/falling edge of clock
Shift Register
Special form of register designed to shift bits left/right.
Contamination Delay
Tcd : MINIMUM time from when an input changes until output STARTS TO CHANGE its value. Total Tcd is the sum of all contamination delays through each element on the SHORTEST path.
Binary
The binary number system is base 2, using only bits 0 and 1. Ex: 101 = (1 * 2^2) + (0 * 2^1) + (1 * 2^0) = 5
Even Parity
The number of ones in a string of binary are even. - If a string is already in even parity, we don't need to add a 1, so we can assert 0 - If a string isn't already in even parity, we can assert a 1 to make it into even parity
Odd Parity
The number of ones in a string of binary are odd. - If a string is already in odd parity, we don't need to add a 1, so we can assert 0 - If a string isn't already in odd parity, we can assert a 1 to make it into odd parity
Critical Path
The path in the entire design with the maximum delay.
ε-Critical Network
The set of ε-critical vertices which forms a connected network consisting of paths from sink to source. A vertex v is ε-critical if Slack(V) ≤ Slack_min + ε ε-critical paths may become critical when optimized.
Controlling Value
The value that determines the output value of the gate irrespective of other inputs. NAND - 0 NOR - 1 AND - 0 OR - 1
(Verilog) Reset
Used to force the state of a design to a known condition after power up.
Directed Acyclic Graph (DAG)
Visual representation that shows corresponding delays between gates and wires. Source vertex is connected to inputs, and outputs are connected to a sink vertex.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
Voltage controlled field effect transistor, which is electrically insulated from the n/p channel by a thin layer of silicon dioxide (glass).
SoC (System-on-Chip)
chip that integrates an entire subsystem including a microprocessor or microcontroller, memory, peripherals, or custom logic.
(Verilog) Sensitivity List
list of signals that trigger execution of the block when they change values
Transistor Transistor Logic (TTL)
logic family built from bipolar junction transistors. - A voltage of LOGIC HIGH ranges from 2v to 5v - A voltage of LOGIC LOW ranges from 0v to 0.8v
