Final
How many different states does a 2 - bit asynchronous counter have ?
4
The ADC0804 is an example of a
Ⓒsuccessive approximation analog - to - digital converter
A bidirectional 4 - bit shift register is storing the nibble 1101. Its control input is HIGH . The nibble 1011 is waiting to be entered on the serial data - input line . After three clock pulses , the shift register is storing
0111
A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s .
1.8 uF
In a 555 timer , three 5 k resistors provide a trigger level of
1/3 VCC and a threshold level 2/3 VCC
Three cascaded decade counters will divide the input frequency by
1000
Which of the following is an invalid state in an 8421 BCD counter ?
1110
The group of bits 10110111 is serially shifted ( right - most bit first ) into an 8 bit parallel output shift register with an initial state of 11110000. After two clock pulses , the register contains
11111100
Using four cascaded counters with a total of 16 bits , how many states must be deleted to achieve a modulus of 50,000 ?
15536
A4 - bit counter has a maximum modulus of
16
The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address
16358
Four J - K flip - flops are cascaded with their J - K inputs tied HIGH . If the input frequency ( fin ) to the first flip - flop is 32 kHz , the output frequency ( fout ) is
2 kHz
An 8 - bit serial in / serial out shift register is used with a clock frequency of 150 kHz . What is the time delay between the serial input and the Q3 output ?
26.64 us
A 12 MHz clock frequency is applied to a cascaded counter of a modulus - 5 counter , a modulus - 8 counter , and a modulus - 10 counter . The lowest output frequency possible is
30 kHz
An 8 - bit serial in / serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay ( td ) of
4 us
With a 200 kHz clock frequency , eight bits can be serially entered into a shift register in
40 us
For a 4 - bit DAC , the least significant bit ( LSB ) is
6.25 % of full scale .
A 5 - bit asynchronous binary counter is made up of five flip - flops , each with a 12 ns propagation delay . The total propagation delay ( tp ( tot ) ) is_________ ..
60 ns
In a 4 - bit Johnson counter sequence there are a total of how many states , or bit patterns ?
8
Which is a typical application of digital signal processing ?
All of them
Which of the following is not a flash memory mode or operation ?
Burst
A BCD counter is a
Decade counter
What do we call the manipulation of an analog signal in a digital domain ?
Digital signal processing
An invalid condition in the operation of an active - HIGH input S - R latch occurs when
HIGHS are applied simultaneously to both inputs S and R
Which term applies to the maintaining of a given signal level until the next sampling ?
Holding
AJ - K flip - flop is in a " no change " condition when
J = 0 , K = 0
What is the result of taking more samples during the quantization process ?
More bit requirements and more accurate signal representation
How much storage capacity does each stage in a shift register represent ?
One bit
If an S - R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0 , the latch will be
RESET
Which is not characteristic of a shift register ?
Serial in / parallel in
The pulse width of a one - shot circuit is determined by
a resistor and capacitor
An op - amp has very
all of them
The smallest unit of binary data is the
bit
FPGA are internally configured automatically by programming a set of
cells
EEPROM stands for
electrically erasable programmable read - only memory
L1 is also called and is made up of
primary cache , SRAM
In a flash analog - to - digital converter , the output of each comparator is connected to an input of a
priority encoder
With regard to a D latch ,
the Q output follows the D input when EN is HIGH
A 4 - bit R / 2R ladder digital - to - analog converter uses_______
two resistor values
The terminal count of a modulus - 11 binary counter is
Ⓒ1010
In a digital representation of voltages using an 8 - bit binary code , how many values can be defined ?
Ⓒ256
A 4 - bit ripple counter consists of flip - flops , each of which has a propagation delay from clock to Q output of 15 ns . For the counter to recycle from 1111 to 0000 , it takes a total of
Ⓒ60 ns
The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 uF is
Ⓒ73 us
On the fifth clock pulse , a 4 - bit Johnson sequence is Q0 = 0 , Q1-1 , Q2 = 1 , and Q3 1. On the sixth clock pulse , the sequence is
ⒸQ0-0 , Q1 = 0 , Q2 = 1 , Q3-1
The location of a unit of data in a memory array is called
Ⓒaddress
A 74HC195 4 - bit parallel access shift register can be used for
Ⓒall of them
ROMs retain data when the
Ⓒall of them
