IT 254 Chapter 8

11) There are a number of difficult technical issues that must be resolved to make it possible to execute multiple instructions simultaneously. One of the most important of these is a) Instructions completing out of order. b) Instructions that have floating point operations. c) Instructions that can be serialized. d) Instructions that require the same number of CPU cycles complete.

a) Instructions completing out of order. Section 8.2 CPU Features and Enhancements

25) Which of the following is most likely: a) L1 cache has 32KB and L2 cache has 1MB b) L1 cache has 1MB and L2 cache has 32KB c) L1 cache has 32KB and L2 cache has 32KB d) L1 cache has 1MB and L2 cache has 1MB

a) L1 cache has 32KB and L2 cache has 1MB Section 8.3 Memory Enhancements

16) What are the slowest steps in the instruction fetch-execute cycle? a) Slowest steps are those that require memory access. b) Slowest steps involve incrementing the instruction pointer. c) Slowest steps are those that require special integer register access. d) Slowest steps are those that require floating point register access.

a) Slowest steps are those that require memory access. Section 8.3 Memory Enhancements

3) There are several factors that determine the number of instructions that a computer can perform in a second. Which of the following is NOT a factor? a) Word size b) Clock speed c) Instruction format - fixed or variable d) Number of steps required by each instruction type

a) Word size Section 8.2 CPU Features and Enhancements

31) Each CPU in the processor, within a single integrated chip, is called a ___________ a) core. b) CPU unit. c) control unit. d) Independent Processor Chip (IPC).

a) core. Section 8.5 Multiprocessing

5) The fetch unit portion of the CPU consists of an instruction fetch unit and an instruction ____________ unit. a) decode b) translate c) decipher d) conversion

a) decode Section 8.2 CPU Features and Enhancements

26) A part of main memory can be allocated to store several adjoining blocks of disk memory. If the requested data is in _________ then no disk access is necessary. a) disk cache b) cache blocks c) read once cache d) buffer disk cache

a) disk cache Section 8.3 Memory Enhancements

14) Branch instructions must always be processed ahead of subsequent instructions. Conditional branch instructions are more difficult than unconditional branches. These types of dependencies are known as control dependencies or sometimes as ______________ or branch dependencies. a) flow b) decision c) qualified d) provisional

a) flow Section 8.2 CPU Features and Enhancements

35) Simultaneous thread multiprocessing (STM) is also known as ___________ a) hyperthreading. b) superthreading c) expert threading d) concurrent threading

a) hyperthreading. Section 8.5 Multiprocessing

30) Under ideal conditions, each CPU processes its own assigned sequence of program instructions a) independently of other CPUs. b) partially sharing the workload with other CPUs. c) without interrupting the other CPUs. d) by sharing L1 cache between other CPUs.

a) independently of other CPUs. Section 8.5 Multiprocessing

27) Instructions, fetched from memory, are _____________within the instruction unit, to determine the type of instruction that is being executed. This allows branch instructions to be passed quickly to the branch processing unit for analysis of future instruction flow. a) partially decoded b) partially executed c) completely decoded d) completely executed

a) partially decoded Section 8.4 The Complete Modern Superscalar CPU

28) In a superscalar CPU, the instruction unit has a(n) ____ to hold instructions until the required type of execution unit is available. a) pipeline b) assembly unit c) instruction set d) cache memory

a) pipeline Section 8.4 The Complete Modern Superscalar CPU

24) When a cache miss occurs, however, there is a time delay while new data is moved to the cache. The time to move data to the cache is called _____________ time. a) stall b) backup c) write-through d) cache back

a) stall Section 8.3 Memory Enhancements

9) Which of the following is not a specific execution unit? a) steering unit b) LOAD/STORE unit c) integer arithmetic unit d) floating point arithmetic unit

a) steering unit Section 8.2 CPU Features and Enhancements

33) What is a "thread"? a) The same segment of code used by many programs. b) Independent segments of programs available to be executed in parallel. c) The set of all variables that are used by all programs in execution. d) Shared allocation of cache memory used by programs available to be executed.

b) Independent segments of programs available to be executed in parallel. Section 8.5 Multiprocessing

32) Which of the following is not an advantage of adding more than one CPU processor within a single integrated chip? a) Relatively inexpensive. b) Reduce resource conflicts. c) Programs can be divided into independent pieces and run separately. d) Reduces power consumption, heat, and stress but gives equivalent processing power.

b) Reduce resource conflicts. Section 8.5 Multiprocessing

15) Some systems provide a small amount of dedicated memory built into the CPU that maintains a record of previous choices for each of several branch instructions that have been used in the program being executed to aid in determining whether a branch is likely to be taken. What are the contents of this memory called? a) look-ahead table b) branch history table c) branch prediction table d) future speculation table

b) branch history table Section 8.2 CPU Features and Enhancements

4) The __________ must be designed to assure that each step of the instruction cycle has time to complete before the results are required by the next step. a) ALU b) clock cycle c) Control Unit d) instruction pointer

b) clock cycle Section 8.2 CPU Features and Enhancements

7) Overlapping instructions—so that more than one instruction is being worked on at a time—is known as the a) conveyor belt method. b) pipelining method. c) assembly line method. d) accelerator method.

b) pipelining method. Section 8.2 CPU Features and Enhancements

13) CPUs can actually search ahead for instructions without apparent dependencies, to keep the execution units busy. Current Intel x86 CPUs, can search ___________ instructions ahead, if necessary, to find instructions available for execution. a) five to ten b) ten to twenty c) twenty to thirty d) fifty to one hundred

b) ten to twenty Section 8.2 CPU Features and Enhancements

20) Each block of cache memory provides a small amount of storage, perhaps between 8 and 64 bytes, also known as a) a cache hit. b) niche cache. c) a cache line. d) a small block cache.

c) a cache line. Section 8.3 Memory Enhancements

6) The ___________ unit contains the arithmetic/logic unit and the portion of the control unit that identifies and controls the steps that comprise the execution part for each different instruction. a) fetch b) decode c) execution d) conversion

c) execution Section 8.2 CPU Features and Enhancements

12) Out-of-order instruction execution can cause problems because a later instruction may depend on the results from an earlier instruction. This situation is known as a __________ or a _______________. a) hazard, reliance b) risk, reliance c) hazard, dependency d) risk, dependency

c) hazard, dependency Section 8.2 CPU Features and Enhancements

1) CPU architecture is defined by the basic characteristics and major features of the CPU. "CPU architecture" is sometimes called a) architecture design b) structural organization c) instruction set architecture d) CPU design and organization

c) instruction set architecture Section 8.1 CPU Architectures

19) Another method for increasing the effective rate of memory access is to divide memory into parts, called, _____________ so that it is possible to access more than one location at a time. a) block separation b) high-low separation c) memory interleaving d) wide-path separation

c) memory interleaving Section 8.3 Memory Enhancements

29) Computers that have multiple CPUs within a single computer, sharing some or all of the system's memory and I/O facilities, are called______________, or sometimes tightly coupled systems. a) bundled systems b) simultaneous systems c) multiprocessor systems d) compound processor systems

c) multiprocessor systems Section 8.5 Multiprocessing

10) A(n) _____________ processor is one that can complete an instruction with each clock tick. a) linear d) direct c) scalar d) express

c) scalar Section 8.2 CPU Features and Enhancements

8) Instruction reordering makes it possible to provide parallel pipelines, with duplicate CPU logic, so that multiple instructions can actually be executed a) sequentially. b) consecutively. c) simultaneously. d) very fast in serial operation.

c) simultaneously. Section 8.2 CPU Features and Enhancements

23) Cache memory hit ratios of ________ percent and above are common with just a small amount of cache. a) 30 b) 60 c) 80 d) 90

d) 90 Section 8.3 Memory Enhancements

18) Which of the following is a commonly used approach for improving performance of memory? a) Doubling the capacity of memory. b) Using DRAM instead of SDRAM. c) Compressing instructions and data in RAM. d) Widening the system bus between memory and the CPU.

d) Widening the system bus between memory and the CPU. Section 8.3 Memory Enhancements

34) In Symmetrical Multiprocessing (SMP) each CPU has a) identical access to memory. b) identical access to the I/O and memory. c) identical access to the operating system, I/O and memory d) identical access to the operating system, and to all system resources, including memory.

d) identical access to the operating system, and to all system resources, including memory. Section 8.5 Multiprocessing

2) The use of fixed-length, fixed-format instruction words with the op code and address fields in the same position for every instruction would allow instructions to be fetched and decoded a) independently. b) dependently and in parallel. c) independently and in serial. d) independently and in parallel.

d) independently and in parallel. Section 8.1 CPU Architectures

17)What is the major drawback of Dynamic RAM (DRAM)? a) cost b) capacity c) data loss d) memory latency

d) memory latency Section 8.3 Memory Enhancements

21) What does "locality of reference" mean? a) most memory references occur concurrently b) most memory references will pull data of numeric type c) most memory references will be accessed in a predictable order d) most memory references are confined to one or a few small regions of memory

d) most memory references are confined to one or a few small regions of memory Section 8.3 Memory Enhancements

22) The locality of reference principal makes sense because most of the instructions being executed at a particular time are a) register-to-memory type instructions. b) math and logical type instructions. c) control and branch type instructions. d) part of a small loop or a small procedure or function.

d) part of a small loop or a small procedure or function. Section 8.3 Memory Enhancements