Terms

is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.

ASIC

Design Netlist (after synthesis) Floorplanning Partitioning Placement Clock-tree Synthesis (CTS) Routing Physical Verification GDS II Generation

ASIC Physical Design Flow

is a process which makes sure that the clock gets distributed evenly to all sequential elements in a design.

CTS

1. The violation can be removed by increasing the drive strength of the cell. 2. By buffering the some of the fan-out paths to reduce the capacitance seen by the output pin.

Cap violation fixing in CTS

clock tree balancing is done by clock tree buffers (CTB) to meet the skew and latency requirements.

Clock tree balancing

Clock tree can be built by clock tree inverters so as to maintain the exact transition (duty cycle)

Clock tree building

Latency, Skew, Maximum transition, Maximum capacitance, Maximum fan-out, list of buffers and inverters etc

Clock tree constraints

is the general engineering art of designing products in such a way that they are easy to manufacture.

Design for manufacturability

Dynamic power is the power consumed during switching of transistors.

Dynamic Power

Many clock buffers are added, congestion may increase, crosstalk noise, crosstalk delay etc.

Effects of CTS

1. Clock tree building 2. Clock tree balancing and clock tree balancing is done by clock tree buffers (CTB) to meet the skew and latency requirements.

Elements of CTS

is an integrated circuit designed to be configured by a customer or a designer after manufacturing - hence "field-programmable".

FPGA

is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

Floorplanning

Designer has full flexibility on the layout design, no predefined cells are used.

Full-custom design

to minimize the skew and latency.

Goal of CTS

1. Downsizing the cells (decrease the drive strength) in data path. 2. Pull the capture clock. 3. Push the launch clock. 4. By adding buffers/Inverter pairs/delay cells to the data path. 5. Decreasing the size of certain cells in the data path, It is better to reduce the cells n capture path closer to the capture flip flop because there is less chance of affecting other paths and causing new errors. 6. By increasing the wire load model, we can also fix the hold violation.

Hold time fixing methods in CTS

In a top level digital design, you will have one more more clock sources, like PLLs or oscillators within the chip. You may also have an external clock source connection through an IO.

How is clock generated

by buffer sizing, gate sizing, HFN synthesis, Buffer relocation.

How is clock tree optimized

re-optimizes the logic based on VR. This can perform cell sizing, cell moving, cell bypassing, net splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of setup fixing, incremental timing and congestion driven placement.

In-placement optimization

1. SDC version (optional) 2. SDC units (optional) 3. Design constraints 4. Comments (optional)

Information given to SDC

placement data and the clock tree constraints.

Inputs to CTS

is a set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon.

Integrated circuit

is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.

Integrated circuit layout

HVT - High Threshold Voltage causes less power consumption and timing to switch is not optimized. It is used in power critical functions. LVT - Low Threshold Voltage causes more power consumption and switching timing is optimized, used in time critical functions. SVT - Standard Threshold Voltage offers trade-off between HVT and LVT i.e., moderate delay and moderate power consumption.

LVT, LVT and SVT cell

- Pre-placement optimization - In placement optimization - Post Placement Optimization (PPO) before clock tree synthesis (CTS) - PPO after CTS.

Optimization phases of placement

DEF, SPEF, netlist

Outputs of clock CTS

Partitioning is a process of dividing the chip into small blocks. This is done mainly to separate different functional blocks and also to make placement and routing easier. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. These modules are linked together in the main module called the TOP LEVEL module. This kind of partitioning is commonly referred to as Logical Partitioning.

Partitioning

is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components.

Physical design

assign cells to positions on the chip, such that no two cells overlap with each other (legalization) and some cost function (e.g., wirelength) is optimized.

Placement

- "before CTS" performs netlist optimization with ideal clocks. It can fix setup, hold, max trans/cap violations. It can do placement optimization based on global routing. It re does HFN synthesis. - "after CTS" optimizes timing with propagated clock. It tries to preserve clock skew.

Post placement optimization (PPO)

optimizes the netlist before placement, HFNs (high fan-out nets) are collapsed. It can also downsize the cells.

Pre-placement Optimization

Synopsys Design Constraints. SDC is a format used to specify the design intent, including the timing, power and area constraints for a design. SDC is tcl based.

SDC

Pre-designed library cells (preferably tested with DFM) are used, designer has flexibility in placement of the cells & routing

Semi-Custom design

1. Upsizing the cells (increase the drive strength) in data path. 2. Pull the launch clock 3. Push the capture clock 4. We can reduce the buffers from datapath . 5. We can replace buffers with two inverters placing farther apart so that delay can adjust. 6. We can also reduce some larger than normal capacitance on a cell output pin. 7. We can upsize the cells to decrease the delay through the cell. 8. LVT cells

Set up fixing methods in CTS

Static power is due to leakage current that flows when the transistor is powered on (in logical OFF state).

Static Power

- H-tree - X-tree - Multi-level - Fish bone

Structures for clock tree

DC, ICC, PT

Tools that use SDC format

1. By upsizing the driver cell. 2. Decreasing the net length by moving cells nearer (or) reducing long routed net. 3. By adding Buffers. 4. By increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation.

Transition violation fixing in CTS

If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Useful Skew

is the shortest Manhattan distance between two pins

Virtual Route

1. Set Up Fixing 2. Hold Fixing 3. Transition violation 4. Cap violation

What fixing are done at CTS

The normal inverters and buffers are not used for building and balancing because, the clock buffers provides a better slew and better drive capability when compared to normal buffers and clock inverters provides a better balance with rise and fall times and hence maintaining the 50% duty cycle.

What inverters and buffers are used in CTS