VLSI

How does noise effect a phase locked loop?

-Contributes to the jitter

What is DC power dissipation and when is it relevant?

-DC power consumption is caused by DC current flowing from power supply to ground during steady state. -This is most prevelant when there is low swing circuitry used to drive long interconnects.

What is the difference between drift and diffusion and when is one more prevalent?

-Diffusion is a natural occurrence where carriers flow from a high concentration to a low concentration and do not need an external force to do this. -Drift current is caused when there is an electric field applied to the carriers causing them to move in a certain direction. -Drift current is due to strong inversion where diffusion is done in the subthreshold region.

Describe short-circuit power and what it depends on and why?

-During a switch, when both the pull-down and pull-up networks are simultaneously on, a DC current is passed to ground. -It depends on the rise and fall times of the input and output signals and the output load capacitance. 1. If the rise and fall time is longer, the transistors are simultaneously on for longer which increases the short circuit current. 2. If the output load is higher, the impedance is lower because of capacitance inverse relation to impedance 1/jwc.

What is the elmore delay and how do we find 50% delay?

-Elmore delay is used to approximate a damped system. -e=1-e^(-t/tau) where tau = RC -To find 50% delay: 1/2=1-e^(-.693)

What is the difference between enhancement and depletion mode?

-Enhancement: Device is normally off and needs enhancing -Depletion mode is normally on and needs to be charge depleted.

What is the gate depletion effect and how does a metal gate with a high permittivity dielectric alleviate this? What are other pros of metal gate?

-Gate depletion effect is when a depletion layer is formed in the active region under a thin oxide thickness. This produces a voltage drop increasing the oxide thickness. Metal Gate Pros -Lessens gate depletion effect -Reduces gate sheet resistance -Improves mobility degradation from high k material -High permittivity dielectric is more stable with a metal gate lessening the voltage and bias temperature instability

Define a race condition and how to solve it.

-If a signal is latched within the first register, propagates through the logic and is latched within the second register during the same edge of the clock that activated the initial register -To solve this: Tc-q +Tlogic +Tint +Tskew >= Thold of second register

How does noise effect a low noise amplifier?

-If the noise is high, it can alter the gain -If switching noise is periodic and in the right frequency band of the signal, it can degrade the performance. -Distortion causes higher bit error rate -Passes noise through the system

Why is CMOS technology considered a power constrained era?

-In constant voltage scaling, power density and power consumption increase significantly -In both, constant subthreshold slope scales the same which means the off current stays the same making the Ion/Ioff ratio smaller reducing transistor quality.

Why is interconnect modeling important now?

-Interconnect capacitance and resistance became comparable to gate capacitance and resistance.

What is a subthreshold slope and how do we want it?

-It characterizes leakage behavior by graphing the required gate to source voltage to vary the subthreshold current by one decade -A lower subthreshold slope is desired because the transistor can be more effectively turned off and the transistor can be turned on an off faster.

From an energy perspective, how is it best to deal with noise?

-It is better to make errors and correct rather than expend energy to reduce noise.

What is the Manhattan distance?

-It is the distance between two points measured along the axes with only right angles permitted.

Why is shielding used on interconnects and where?

-It is used to constrain the return current minimizing inductance and making measurements easier.

Explain the concept of a guard ring and when it is best used.

-It provides a low impedance path for the noise current -Can only be placed around aggressor to minimize vertical current or the victim to enhance noise isolation or both -More efficient in lightly doped substrate since noise will flow through heavily doped bulk in epi. -Wiring width provides only initial improvements until it takes up unnecessary space -Localized guard ring used to weave through aggressor block for better use

When should resistance be considered in interconnect modeling and what is the equation for sheet resistance and resistivity?

-It should be considered when the resistance of the channel on (1/(u*Cox*W/L*(Vgs-Vth) is comparable to the interconnect resistance. -Resistivity = p*l/(W*thickness) -Sheet resistance = p/thickness

Noise margin for logic 1 and logic 0

-NM high = Voh - Vih -NM low = Vil - Vol

What are the three variables changed in Electric Field scaling and the four ways of changing them.

-Physical dimensions, voltages and doping concentration 1. Increase current: Scale gate insulator thickness and channel length 2. Lower vertical electric field and power dissipation: Scale power supply voltage 3. Maintain current drive capability: scale threshold voltage by reducing insulator thickness 4. Decrease depletion layer width: Increase substrate doping concentration

How does an inductive interconnect help at high frequencies?

-Short Circuit power can be decreased with underdamped inductive lines. -Transition time is minimum when load is matched with driver -Longer more inductive lines reduce power. -Improves signal transition time.

How does capacitance dominance differ at different interconnect width spacing?

-Since thickness stays constant, as width becomes smaller, coupling takes over, as width becomes larger, parallel plate takes over.

Describe Dynamic Switching Power and its dependencies.

-Switching power is dissipated while charging or discharging parasitic capacitances during voltage transitions. -This is dependent on 1. Power supply voltage (V) 2. Switching frequency (f) 3. Capacitance being charged 4. Switching activity factor (a) P = aCV^2f

What is electro-migration when does it occur and how is it mitigated?

-When too much current pushes away the metal due to a small structure size and creates an open circuit. -Use static electromigration analysis even though it ignores transient currents -It tends to happen where material transitions from thicker material to finer ones. -Copper is better than aluminum -Temperature increases mean time to failure -Wider wires to reduce current density -Self Healing: Balanced current flow in both directions undoes electromigration

What are the two effects of substrate noise?

1. Body effect varies threshold voltage -Increase in body voltage reduces Vt 2. Capacitive coupling to the signal, power/ground lines and source/drain nodes -Noise couples through oxide capacitance to the power/ground line and through junction capacitance to source/drain

Depending on what dominates the load, what type of circuit optimization will you use? How do they effect the circuit?

1. Capacitive Load: Tapered buffer -Tapered buffers isolate the preceding circuit from the large capacitive load and amplifies the circuit. -Each buffer and capacitor become larger by a tapering factor F -F = Cload/Cg/2.718^N -Number of buffers = ln(Cl/Cin) -Delay = buffers*to*F+to*F -Two conditions must be met: preceding circuit can drive tapered buffer, tapered buffer can drive large capacitive load. 2. Resistive load: Repeater insertion -Repeater insertion reduces the quadratic delay dependence on length t = .377RC(l^2) by cutting the circuit into smaller pieces. -The higher the interconnect delay compared to the gate delay, the more repeaters -There must also be a balance between the repeater output resistance and interconnect resistance. 3. Inductive load: repeater insertion, fewer than resistive load -If circuit is lossless (Rint=0) no repeater insertion -Inductive effects create a linear rather than quadratic relationship with delay and line length, this means less repeaters are needed. -Repeaters reduce coupling noise

What determines the transistor switching speed?

1. Channel length, distance between source and drain. 2. Velocity of the minority carriers.

What are the two technology scaling schemes and describe their pros and cons

1. Constant Voltage Scaling Pros -Between 2 um and 8 um -Used to avoid multiple power supply voltages -Reduces Delay Cons -Electric fields increase as technology is scaled creating hot carrier issues -Increased overall power consumption 2. Constant Electric Field Pros -Between .8 um and 130/90 nm -Reduced power consumption -Reduced hot carrier issues Cons -Cannot scale lower than 1 v threshold

In what three ways does temperature affect Power Dissipation?

1. Degraded mobility of the charge carrier, reducing circuit speed. 2. Reduction in threshold voltage, increasing the speed of the circuit. 3. Increase in leakage current.

What are the effects of inductance and explain its cause.

1. Delay 2. Waveform properties 3. Signal Integrity -Creates settling time violations -Mutual inductance injects noise into victim signal lines -If load and source is mismatched, a signal reaches steady state faster as it is reflected back and forth. 4. Switching Ldi/dt noise

What are different substrate biasing techniques and explain them.

1. Digital ground network 2. Dedicated ground network 3. Backside contact 4. Analog ground network

Describe leakage power consumption

1. Dominant source of power consumption 2. Reverse biased p-n junction leakage current. (Done in n+ wells) -There is still current flowing in reverse bias 3. Weak inversion, subthreshold leakage current. (Done in channel) -When Vgs is close in magnitude to Vt current flows 3. Gate leakage current (Done from gate) -If the oxide thickness is thin enough, carriers can leak from the gate through the barrier.

How can you control Vt?

1. Doping levels during manufacturing 2. Controlling Vth through substrate bias

What are the equations for energy removed from power supply in CMOS as well as Energy stored in Capacitors?

1. Evdd = CVdd^2 2. Ec = CVdd^2/2

Describe the two different techniques to determine substrate impedance.

1. Finite difference method: Represents the substrate as a three-dimensional mesh of lumped RC impedances discretizing the whole circuit. -It can become to tough to analyze computationally as it gets bigger. 2. Boundary element method: turns the substrate into a two-dimensional model which discretizes the ports. -Cannot consider nonuniform structures 3. Compact substrate models: Less accurate but more efficient.

What does current dependent on?

1. I = 1/2*un*eox/tox*W/L*(Vgs-Vt)^2 -Channel Length -Channel width -Threshold Voltage -Power Supply voltage -gate oxide thickness -depletion width -doping profiles -junction depths -Temperature

Derive dynamic power equation

1. I = Cdv/dt 2. Idt = Cdv 3. integrate from 0 to T and 0 to Vdd 4. IT = CVdd 5. I = CVdd/T = CVdd*f 6. P = V*I = CVdd^2f

When will a circuit exhibit inductive behavior?

1. If length of interconnect is longer than shortest signal wavelength. 2. If the damping factor is smaller than one, the circuit is under damped resulting in inductive behavior.

What are the four noise injection mechanisms?

1. Impact Ionization: If high electric field in the depletion region, current is injected into substrate 2. Ground noise coupling: Non-ideal ground has noise that couples to substrate 3. Power noise coupling through n-well ties: Power supply noise couples into the n-well ties then into the substrate 4. Capacitive coupling through source/drain junctions: Reverse biased p-n structures.

What are the four areas of modeling crosstalk?

1. Impedance Model: Higher resistance in victim and lower resistance in aggressor produce high coupling noise. -Saturation = high resistance -Linear = low resistance 2. Type of Input: Exponential input is more accurate but more complex, step input is more efficient but has greater error. 3. Interconnect Model: Cascade several lumped stages. 4. Aggressor number and location: Multiple aggressors can affect a victim, placement of these are key.

Techniques on how to reduce inductive coupling?

1. Increase wire width of aggressor since characteristic impedance is smaller -Increased delay, power and area 2. Shielding: Creates a closer current return path for interconnects 3. Gate sizing: -reducing the size of the aggressor reduces inductive coupling because there is less current injected -Increasing the size of the victim because it is better connected to ground and Vdd 4. Net reordering or wire swizzling so that sensitive lines aren't next to each other to cause coupling.

What are common techniques to reducing capacitive coupling noise and explain what it does and its drawbacks.

1. Increase wire width: Increases the ground capacitance which behaves as a filter reducing coupling noise. -Issue with this is increased area and delay due to more capacitance. -Another issue if the line has inductive coupling rather than capacitive coupling, it will increase noise. 2. Increase wire spacing: Reduces the coupling noise by decreasing coupling capacitance. -It is only effective right before the mutual inductance begins to dominate the coupling noise. -As line width becomes larger, inductive coupling begins to dominate due to the long range phenomenon. 3. Increase the wire width near the driver and decrease near the load: Near end end resistance sees more capacitance than far end, assign low resistance in the near and more in the far to reduce RC delay. -Hard to manufacture 4. Repeater staggering: Reduces not only delay but capacitive coupling noise. This is because coupling noise here is proportional to length of two parallel interconnects which in this case is broken up by repeaters. 5. Shielding: Power and ground line is placed between aggressor and victim isolating the lines from each other. -Inductive coupling also reduced due to return path being closer. 6. Gate sizing: -Reducing the size of the aggressor reduces coupling noise since driver is weaker -Slows down signal path -Increasing the size of the victim reduces coupling because it is better connected to ground -Uses more area 7. Net reordering or wire swizzling so that sensitive lines aren't next to each other to cause coupling.

What are problems that come with higher interconnect resistance?

1. Increased delay (RC constant) 2. Degradation in signal waveform 3. Greater clock skew 4. Higher voltage variation from IR drop

Why do we scale the gate oxide thickness? What is the issue with this?

1. Increases the drive current 2. Reduces the short-channel effects 3. Reduces the subthreshold slope -The problem is since the thickness is scaling but Vdd is not, E = Vdd/tox, the electric field gets larger. This increases tunneling of the carriers producing gate leakage current which degrades the device reliability.

Explain the different causes of noise in an a circuit? How can they be mitigated?

1. Interconnect noise: cross talk from switching noise transferred through coupling causes delay variations. -Increase distance between lines to reduce coupling -Create in-phase switching to eliminate coupling capacitance 2. Higher resistance in victim and lower resistance in aggressor produce high coupling noise. -Saturation = high resistance -Linear = low resistance 3. A farther return current path creates larger inductive coupling noise. 4. Glitch: When switching times of input signals are not aligned, a voltage spike occurs. It can either dissipate dynamically by turning on the transistor or statically by giving off subthreshold leakage.

What does interconnect capacitance depend on?

1. Length 2. Width 3. Size of t

Different types of a substrate?

1. Lightly Doped Substrate -High resistivity -For mixed-signal circuits -Uniform current flow 2. Epi type -High resistivity layer over low resistivity substrate -Reduced latch-up -Less tolerant to noise -less uniform current flow

When do we use a lumped model to simulate an interconnect? What is one of its problems? How can distributed interconnect help?

1. Local Interconnect 2. Gate oxide capacitance dominates over interconnect capacitance. 3. Has large error due to capacitance seeing all of the interconnect resistance 4. Cascade several lumped elements and capacitance sees less resistance.

What are the different ways of measuring inductance?

1. Loop flux (mutual inductance): Inductance caused by current flow in one loop on another loop. 2. Partial Inductance: Separating the inductance into a sum of its self and partial mutual inductance. 3. Net inductance: The contribution of a segment current by adding the partial self and mutual inductance.

Describe different ways of implementing low power CMOS design.

1. Multi power supply and threshold voltage -Lower the supply voltage on non-critical paths. -High threshold on non-critical path = less subthreshold leakage power -low threshold on critical path to increase speed. 2. Dynamic supply voltage scaling -Depending on the workload, modify the power supply and clock frequency to maximize or minimize throughput 3. Near threshold Computing -Sweet spot between energy consumption and speed 4. Low Swing Interconnect -Operate different circuit blocks at different voltage levels -Problem is degraded output voltage swing and low speed signal transfer 5. Adaptive Body Biasing -Forward body bias for dies that are too slow -Reverse body bias for dies that violate leakage constraint 6. Architecture voltage scaling -Use parallel architecture or Pipelining to reduce Vdd by eliminating hazards and races. 7. Arithmetic transformation -Reduce the number of operations needed to do something 8. Transistor Sizing -Larger width wastes area and power -Smaller width makes circuit too slow -Multithreshold CMOS and Adaptive body biasing reduce leakage power and the rest reduce dynamic power.

What are the five states of the CMOS inverter?

1. N cutoff Vgs < Vt, P linear Vds - small 2. N - saturated Vds -large, P linear Vds small 3. N saturated Vgs = Vds, P saturated Vgs = Vds, both Vds >Vgs-Vt 4. N linear Vds small, P saturated Vds large 5. N linear Vds small, P cutoff Vgs - Vt

What are different causes of delay uncertainty?

1. Noise: Unwanted energy degrading signal quality 2. Clock Jitter: Variation in the clock signal at the clock source due to sagging of supply voltage -Fix by using decoupling capacitance between power and ground 3. Process Parameter variations: Manufacturing errors 4. Environment: Temperature, radiation

What are the three power grid types?

1. Non-Interdigitated: power lines and ground lines on either halfs 2. Interdigitated: power and ground lines alternate uniformly 3. Paired: Power and ground lines are paired and uniformly distributed -Parallel currents should be spaced farther while anti-parallel should be placed closer to decrease inductance.

What are the three forms of damping?

1. Overdamped: Create a stable response of lower speed. Capacitive system 2. Critically damped: System response is at its fastest. 3. Underdamped: Produces overshoot and oscillates until it becomes steady.Inductive system

What are the three components of interconnect capacitance and what is the most significant?

1. Parallel Plate Capacitance (Area Component): C = (e/H)*W*L 2. Fringing Component: Line-to-ground, side to ground, top to ground. 3. Coupling Capacitance (Line to line): C = (e/Wspacing)*L*thickness -Coupling capacitance is most significant as the dimensions become smaller and more lines are close. It can generate lots of crosstalk.

Why is the effective resistivity not ideal and explain what causes this

1. Processing steps -A barrier is built around the copper interconnect to prevent copper from diffusing, this barrier adds resistance. -Surface and grain scattering: As dimensions become smaller, electrons experience more collisions increasing resistivity. 2. Operating Temperature -Higher temperature reduces the electron mean free path creating additional electron collisions increasing resistance. 3. Frequency -Skin Effect: At high frequencies, electrons flow near the surface of the interconnect. This reduces current density causing a rise in resistance. If the skin effect is comparable to the wire it effects the resistance more.

What are the three main design objectives in VLSI, related to Global Interconnect

1. Propagation delay: With smaller feature sizes, the number of interconnects increased exponentially. This means more delay 2. Power Consumption: Interconnect coupling capacitance dominates the gate load. A majority of the transient power is dissipated on these capacitive lines. 3. Signal Noise: Coupling capacitance degrades signal integrity. Creates delay uncertainty causing synchronization faults. Power and ground lines gain power supply noise.

What are the components of overall power dissipation in a circuit and explain each

1. Ptotal = Ptransient + Pstatic 2. Ptransient = Pdynamic + Pshort-circuit 3. Pstatic = Pdc +Pleakage 4. Pleakage = Psubthreshold + Pgate-leakage

What are techniques to reduce substrate noise?

1. Reduce switching noise -Decoupling capacitors between power and ground -Shielding to reduce reduce mutual inductance -Separate power and ground networks for analog and digital -Asynchronous circuit structures 2. Modify noise transfer medium -Guard rings -Deep N-well Isolates transistors from noisy substrate by creating a reverse bias open circuit -Higher resistivity substrate -Greater distance between aggressor and victim -Silicon on insulator: transistor has a floating body due to being on top of an insulator reducing noise. 3. Reduce sensitivity of the analog circuit -Differential signaling: epi has higher symmetry and therefor more noise reduction. Add a signal with its inverted signal and divide by 2 and this resists noise. -Higher common mode rejection ratio and power supply rejection

How does frequency effect interconnect impedance?

1. Skin Effect: Higher frequency means less impedance due to lower current density. 2. Proximity effect: Current concentrates on side closest to current return path, this is significant if the adjacent wire is carrying a high frequency. 3. At high frequencies, since resistance is so much higher, current return paths are determined by inductance paths.

Why does the threshold voltage not scale well?

1. Subthreshold leakage current 2. Difficult to control the manufacturing process

What are short channel effects and what do they effect and how can they be fixed?

1. Threshold voltage -Vt roll-off: Because of depletion charge induced by source and drain along with the bulk depletion charge, there is less threshold voltage created by the gate which means threshold voltage will be lower for the gate. It can be fixed by decreasing the gate insulator thickness to give the gate more control of the channel but it increases gate leakage and you simultaneously need to increase doping to maintain constant threshold voltage. Or by decreasing the junction depth but this increases junction resistance. -Drain Induced Barrier Lowering: If Vd is high enough, it can invert the depletion layer called punchthrough. If it isn't high enough and needs Vgate, Vgate will not have to be as high as Vt because the drain is already supplying some of the voltage. 2. Electron Drift Characteristics -Velocity Saturation: Maximum drift velocity of carriers when electric field is at its highest due to the drain voltage being higher and the channel length being smaller creating a larger lateral electric field. -Mobility Degradation: When the gate voltage is much higher than the bulk, the electric field becomes larger. As the electric field gets higher, the mobility becomes lower.

What does increasing doping concentration do to a transistor?

1. To get rid of short channel effects, which reduces the threshold voltage, the depletion layer must be reduced to keep up with the reduction of channel length. To reduce the depletion layer, an increased in doping concentration must happen. However, an increase in doping degrades the carrier mobility due to channel impurity scattering.

What does gate leakage depend upon?

1. Voltage across the gate -The electric field is at its maximum when the gate voltage creates an active region. 2. Number of free carriers -In the active region, there are more free carriers to leak through 3. Dielectric thickness -Increases number of carriers as well as increasing the electric field (E=V/tox) 4. Height of the tunneling barrier -The higher the barrier, the lower the probability of tunneling 5. Effective mass of the carriers -Holes need a higher barrier than electrons to prevent tunneling.

Why is it difficult to extract inductance?

1. difficult to determine current return paths 2. Inductance is a long range phenomenon 3. It is a function of frequency due to the skin and proximity effect 4. Takes a long time to analyze/simulate

What happens when Vgate is higher than Vt?

A large number of minority carriers are attracted to the silicon surface due to the vertical electric field. These minority carriers carry charge between the source and drain causing current to flow.

What are the advantages and disadvantages of using low Vdd and low Vt?

Advantage -High Speed -Lower Power Disadvantage -More standby power dissipation in low Vt -Difficult to achieve low Vt -Tough to test defective chips

Describe Channel Length Modulation

As Vds is increased, the depletion width increases due to a higher vertical electric field created by the drain and bulk voltage. This creates a shorter channel which means there will be greater drain current. This also means you need a higher gate voltage to invert the channel.

How does maximum frequency of interest increase as rise time becomes smaller?

As rise time becomes smaller than 50ps, frequency rapidly increases into the Ghz

Define Clock skew and its properties

Clock skew is when a clock signal arrives slightly before or after the original clock signal in another component. This causes delay uncertainty.

What is Cox?

Cox = eox/tox where eox = eo*er where eo = 8.854*10^(-12) and eo for silicon is 3.9.

Dry oxidation vs Wet oxidation

Dry oxidation uses oxygen to oxidize the silicon while wet means water vapor is used. Wet oxidation is faster but is less pure.

Do holes or electrons have a higher mobility and how does this relate to MOSFETS? What is the aspect ratio of a CMOS?

Electrons have a mobility of around 2 times an electron. Due to this, the P-mos needs a wider width than an N-mos so their switching speed stays similar. Aspect ratio is un/up = Wp/Wn

What are the two interconnect scaling techniques? Describe them.

Ideal: Aspect Ratio 1 -Global -Length = Sc -Resistance = Sc*S^2 (R = L/t*W) -Capacitance = Sc -Local -Length = 1/S -Resistance = S (R = L/t*W) -Capacitance = 1/S Constant Thickness: Aspect Ratio S -Global -Length = Sc -Resistance = SSc (R = L/t*W) -Coupling Capacitance = Sc*S -Ground Capacitance = Sc -Local -Length = 1/S -Resistance = 1 -Coupling Capacitance = 1 -Ground Capacitance = 1/S

Describe the Hot electron effect

In Nmos devices, if there is a high enough electric field, then electrons may gain enough kinetic energy to break the barrier between the gate and the substrate. This increases the threshold voltage. To reduce this effect you can create a lightly doped drain (LDD) which reduces the e field laterally.

Describe the issue of Latch-Up in CMOS and how it can be prevented.

Latch-Up happens due to the formation of two parasitic bipolar devices which create positive feedback path that can burn out the chip. To solve this you can: 1. Increase base width to reduce beta 2. Resistive shunting: use well plugs or dope the substrate higher 3. Trench Isolation: Deposit deep oxide to isolate devices from each other.

Linear vs Saturation region equations and when it happens in N Mos

Linear: Vgs-Vt<Vds -I = 1/2*u*eox/tox*W/L[2(Vgs-Vt)*Vds-Vds^2] Saturation: Vds>Vgs-Vt -i = 1/2*u*eox/tox*W/L(Vgs-Vt)^2 -Multiply by (1+lambda*Vds) if channel length modulation

Constant Voltage Scaling, scaling factors

Main: width, channel length and insulator thickness scaled by 1/S. Substrate doping concentration increases by S^2 1. Depletion layer scales by 1/S 2. Threshold voltage, subthreshold slope stays constant 3. Current scales by S 4. Capacitance and resistance scales by 1/S C = (W*L)*e/t and V = IR 5. Delay scales by 1/S^2 t = CV/I 6. Power scales by S P=IV 7. Power Density scales by S^3 P/WL

Constant e field Scaling, scaling factors

Main: width, channel length, gate insulator thickness and power supply all scale together by 1/S and Doping Concentration scales by S 1. Subthreshold slope, resistance and power density does not scale, V = IR and P/WL 2. Gate Capacitance scales by 1/S e*W*L/t 3. Delay scales by 1/S CV/I 4. Power scales by 1/S^2 P=IV 5. Current scales 1/S

What type substrate do N-Mos and P-MOS have?

N-Mos = P substrate P-Mos = N substrate

Short circuit power dissipation equation

P = Vdd*Ipeak*(tr+tf)*f/2

Components of leakage power in a MOSFET and how it can be reduced?

Pleak = K*10^(-Vt/S)*Vdd 1. Greater Vth 2. Reduce transistor size K 3. Reduce power supply voltage Vdd

What is propagation delay and the equation for voltage level delay.

Propagation delay is from when the input is 50% to when the output reaches 50%. The equation for V is 1-e^(-t/RC)

What are the pros and cons of replacing SiO2 with a higher permittivity dielectric?

Pros -Reduces gate leakage by allowing a constant thickness while also allowing the effects of a reduced SiO2 gate oxide. Ex. Good for performance, short channel effects and subthreshold leakage. Cons -Degradation of interface producing threshold voltage instability -Mobility degradation -Negative and positive bias temperature instability -Time dependent dielectric breakdown

How does dynamic noise margin differ from the static noise margin?

Static -Obtained through voltage transfer characteristics -Digital gates are low pass filters so less sensitive to high frequency Dynamic -Takes into account frequency, rise time, noise width

Static vs Dynamic characteristics and drawbacks for memory

Static: All outputs will stay steady as long as power supply is provided Drawback: Costs an extra transistor, more power and longer delay Dynamic: Stores charge value in capacitor and needs to be periodically refreshed. Drawback: Needs to be periodically refreshed, however it uses less power, area and is faster.

What is the primary source of energy dissipation in an idle circuit?

Subthreshold leakage current. Subthreshold leakage current is also a large factor in active mode power.

Minimum clock period between two registers equation

T = Tc-q + TLogic + TInt + Tsetup + Tskew

Define Clock to Q delay

The time it takes data to reach the output Q beginning when the clock triggers the register.

Define Setup skew and setup time

The time that is needed for the input to receive data before the clock triggers it to be sent. Setup time is the minimum setup skew needed.

Define hold skew and hold time

The time that the data signal must be stable at the D input after the clock signal triggers it to send. Hold time is the minimum hold skew needed.

What is critical for developing low power design methodologies and why?

Understanding the source of power consumption. This is important for Battery life, reliability, cooling requirements and contribution to global energy consumption.

Describe Depletion Region

When Vgate is lower than Vt, majority carriers are pushed into the substrate creating a depletion region between the source and drain.

What does a CMOS NOR logic circuit look like?

Y = !(A+B)

What does a CMOS NAND logic circuit look like?

Y = !(AB)

What does high-K and metal gate structures do for scaling?

high-K reduces the gate leakage current and eliminates short channel effects from high vertical electric fields. It allows a greater insulator thickness which reduces the leakage current. Metal gates enhance stability of characteristics of the high-K material but takes up more materials.

What is the equation for number of stages required in an interconnect model?

n>=5l(LC)^.5/t t = rise time

Pi model vs T model

pi model: Divides capacitance by two on either side of resistance t model: divides resistance by two on either side of capacitor

What is the electron mobility equation?

v = uE