Ch. 4: Introduction to Sequential Circuits

algorithmic state machine

_____ ____ ______ is constructed of three elements 1. state box 2. decision box 3. conditional output box

algorithm

a defined sequence of steps that produces a desired sequence of actions in response to the given inputs

state diagram

a graphical representation of the behavior of a sequential circuit in which the states of the circuit are represented by circles and the state transitions are shown by arrows

flip-flop

a memory element that has a control input called a clock where the clock input carries a signal to the flip-flop that triggers a state change in accordance with the excitation inputs

clock signal

a sequence of pulses most often occurring at a fixed rate, or frequency. they enable the memory elements of the circuit to change states

mealy model

a state machine where the output is a function of both the inputs and the present state

moore model

a state machine whose output is a function of only the present state

state table

all circuit input vectors are listed across the top (x), while all the state vectors are listed down the left side (y)

synchronous sequential circuits

all state changes are synchronized to a common signal, like a clock

0

applying a reset pulse will keep the latch in a rese state so q is ____

1

applying a set pulse will keep the latch in a set state so q is ___

state

each memory element stores one bit of binary that represents the _____ of the circuit

forbidden state

in a s-r latch S and R cannot both be 0 (or 1 for NAND implementation) because this can cause it to start oscillating, which creates instability, removing it's use as stagnant memory

excitation inputs

inputs that are used to "excite" or drive the circuit into a desired state

oscillating

memory cannot be _______

latch

memory element whose excitation inputs control the state of the device

hold time

period of time immediately following the enable signal transition during which D should not change

setup time

period of time immediately preceding the enable signal transition during which the excitation input must be stable

gated d-latch

q becomes equal to d while g (enable) is active

decision box

represents a state transition decision based on a test of one circuit input

state box

represents one state of the circuit and is therefore equivalent to one node of a state diagram

finite state machines

sequential logic circuits that have a finite number of possible combinations of state variable values

conditional output box

specifies outputs associated with state transitions for a given input in a Mealy circuit

asynchronous sequential circuit

state changes in these circuits are not synchronized to a clock signal, ad instead respond to any change of inputs

d latch

stores one bit, with an input d having the bit to be stored, an input e that when 1 enables storing the bit, and with the stored bit appearing on output q. aka delay or data latch

gated latch

the control signal can be thought of as opening a gate through which signals on the excitation inputs can propagate to the output

sequential circuit

the output of a ____ _____ depends on present inputs and previous outputs, that are retained by memory

feedback

the output of one gate is connected back into the input of another gate so as to form a closed loop

present state

the present input represents the ___ ____ of the circuit

reset

a latch excitation input that forces the state to be 0

set

a latch excitation input that forces the state to be 1

algorithmic state machine

a variation of a state diagram that is useful when designing system control units and other finite-state machines

gated s-r latch

when the gate is inactive, the state of the latch cannot change. when the gate is active, setting the pulse can output q to 1, while resetting outputs q to 0