CPE 233 Lab Questions
Moore-type FSMs are often considered "slower" than Mealy-type FSMs. Briefly explain what the notion of "slow" refers to in this case and briefly explain why Moore-types FSMs are "slower".
"Slow" means that a Moore FSM takes more time to react to an input compared to a Mealy FSM. Mealy FSMs allow outputs to change asynchronously in response to external inputs. Moore FSMs require a transition to a new state before the output can change.
Being that there are two add-type instructions (addi & add), briefly explain why there is only one "add" operation associated with the ALU.
"add" in the ALU performs a general addition between the two inputs. "addi" vs "add" as instructions will control whether one input is an immediate value or not, but the ALU itself treats the inputs the same.
In the term 2^m x s, what are the following denoted by: # of address lines, memory capacity in words, memory capacity in bits.
# of address lines = m memory capacity in words = 2^m memory capacity in bits = 2^m x s
Briefly explain whether a Mealy-type output can act like a Moore-type or Mealy-type output.
A Mealy-type output can act like either a Mealy or Moore-type output. Mealy outputs are based on either external inputs and the current state or simply just the current states (based on the desired functionality).
I have this strong desire to implement an instruction such as "add x3,x4,x5,x6", where the three rightmost operands are summed and the result is stored in the left-most operand. Briefly but completely describe the changes in hardware (to existing RISC-V Otter modules only) that I would need to implement such an instruction.
- ALU would need to take in one more operand to carry this out. - Another MUX would be required to enable differentiation of the newly inputted operand (i.e. register, I-type, etc.). That new MUX would then require changes to the DCDR outputs, accounting for a 3rd alu_src signal. - The reg file would also need to be altered to account for a 3rd register operand.
In your own words, describe the relationship between the programming model and the instruction set of a given computer.
A programming model is a high level view of the different hardware a programmer can use. An instruction set is what allows the programmer to implement the hardware.
The stack is a useful "mechanism" in MCUs and we refer to the stack as an "abstract data type". Define ADT in your own words and in the context of computer hardware.
Abstract data types are objects or mechanisms with defined behavior and description of what operations can be performed, but have no specifically stated implementation. In computer hardware, the data stored on the stack is held in memory, but the hardware only sees the pointer and the operations (push, pop) associated with the pointer address. The hardware doesn't need to know how or where the data is being held, only that pushing and popping will provide the appropriate values.
List at least two reasons why lead zero blanking is a great idea to use, particularly in embedded systems.
Any display indicating a value will have the possibility of displaying leading zeros, which aren't important to the value. Lead zero blanking, which replaces the zeros with blank spots, is good because Extra zeros can make the display harder to read Power can be saved by having those zero spots turned off
Briefly define the general purpose of assembler directives.
Assembler directives give the programmer control over the operation of the assembler, operating as messages from the programmer to the assembler. The RISC-V assembler has many readily available directives that allow the programmer to be more versatile in their overall program design.
What is the maximum number of different unique bits that you could configure the RISC-V MCU to output? Briefly but fully explain. Write an equation; don't generate the final number.
Inputs and outputs are both represented in the I/O memory, so they will have the same total number of port addresses. Total bits: (2^32 - 2^16) * 32.
What is the capacity of the MEMORY module? List the capacity in both bytes and words.
Byte Capacity: 2^16 x 8 Word Capacity: 2^14 x 32
Briefly explain why the state diagram listed in Figure 20 is only a "partial" state diagram. For this question, only consider the timing diagram associated with this experiment. This question has nothing to do with interrupts.
CU_FSM is designed to adjust control signals to other modules in the MCU based on what cycle the FSM is in. Since these outputs are dependent on what state the FSM is in, they are Moore outputs. Figure 20 has empty states, not including the control outputs of the FSM.
Assembly languages are not considered "portable". Briefly describe what this means and why this is the case.
Having "portable" code means that if something in the underlying hardware changes, the code will required little to no modification in order to work properly. Higher-level languages are generally portable, allowing them to be complied on different target machines. However, since assembly language uses mnemonics to represent instructions for a SPECIFIC computer architecture, it is generally non-portable.
The PC has two types of input signals: control signals and data signals, where we consider the clock input a type of control signal. List which inputs are data inputs, and which are control inputs.
Data Inputs: jar, branch, jal Control Inputs: reset, pcWrite, clk, pcSource
In your own words, provide a simple definition for digital design.
Designing a digital circuit to perform a function that solves a problem
Briefly explain whether the use of enumerated types in SystemVerilog increases the size of the synthesized design.
Enumerated types don't affect the size of the synthesized design because no additional hardware is added, and the enumeration is translated into the appropriate signals upon synthesization. Enumeration is similar to assembly code labels in that they are helpful to program readability but are converted by the software.
As you know, part of the interrupt architecture includes the RISC‐V MCU automatically masking the interrupts. This being the case, why then is there a need to keep the overall output pulse length of the interrupt relatively short?
Even though the MCU automatically disables interrupts, we want to enable interrupts once the ISR ends in order to continue processing unique interrupt signals. This means that the pulse length of any interrupt must be less than the time between being detected to interrupts being re-enabled after the ISR is complete. We don't want a single interrupt pulse to trigger multiple interrupts for the MCU.
Briefly explain why the PC advanced by 4 when it is executing instructions.
Every address represents 1 byte in memory, while each instruction is 4 bytes. The PC has to advance 4 addresses before reaching the next instruction.
There are five instruction types that include immediate value; list which of those types are sign-extended by the IMMED_GEN module.
I-type, S-type, B-type, J-type
List the accepted basic parts of a computer
I/O, Memory, Processor
Briefly describe why the IOBUS_ADDR is an output from the ALU and not from a register or directly from memory.
IOBUS_ADDR is the absolute memory address associated with load instruction outputs. Load instructions have immediate offset values, so the ALU is required to add the instructions' source register value (absolute address) and the offset (relative address) together in order to get the actual intended destination address.
Briefly but completely explain why, in general, keeping your ISRs as short as possible is the best approach.
ISRs should be as short as possible because, during its runtime, other interrupts get ignored. As the ISR gets longer, there is an increasing chance that any interrupt is not going to be detected, which can be bad considering interrupts are typically a priority in interrupt-driven programs.
Briefly but completely describe the major problem with the RISC-V MCU receiving an interrupt while the MCU is in the act of processing an interrupt. For this problem, consider the interrupts MASKED when the MCU receives the interrupt.
If an interrupt occurs while in the middle of an interrupt program such that interrupts are disabled, the new interrupt is completely ignored. This can be an issue considering how important that new interrupt might be. For example, if keeping track of how many interrupts are received is necessary for a program, an interrupt occurring while interrupts are disabled means that the program is negatively affected.
Briefly but completely describe the major problem with the RISC-V MCU receiving an interrupt while the MCU is in the act of processing an interrupt. For this problem, consider the interrupts UNMASKED when the MCU receives the interrupt.
If an interrupt occurs while in the middle of an interrupt program such that interrupts are enabled, program flow becomes unpredictable. Processing this new interrupt will overwrite the return address of the original interrupt and any registers used in the interrupt will have their data overwritten. Once the new interrupt is done, the program jumps back to the original interrupt, but then will have an incorrect return address when trying to "mret". This is similar to having nested subroutines where you don't save return addresses on the stack.
The default action for interrupts in the RISC-V Otter MCU is that they are masked upon entry to the ISR, and later unmasked upon exiting the ISR; this means that without intervention, the interrupts returned unmasked. Briefly describe the procedure of how programmers return from interrupts with the interrupts disabled.
If nothing is done by the programmer, interrupts return unmasked because the hardware sets the MPIE bit to 1 when processing an interrupt, then copies MPIE to MIE when returning from an interrupt program. This would make the MIE bit 1, meaning that interrupts are enabled. However, since we want to manually enable interrupts after leaving the interrupt program, programmers would clear the MPIE it before returning, so that the hardware copies 0 into the MIE, disabling it.
If the "memory" portion of RISC-V MCU memory changed from 2^16 x 8 to 2^10 x 8, what would be the new maximum number of unique input and/or output addresses that the hardware could use? Answer this problem with an equation. Read the problem very carefully.
If the memory portion of the MCU decreased to 2^10 byte addresses, the I/O memory would take up a larger section in memory (because the total memory doesn't change). The I/O address space would be: (2^32 - 2^10).
Briefly explain why the data output from the MEMORY module associated with the jal, jalr, and branch inputs produced junk on the outputs (unknown outputs) for this experiment.
In this lab, there was only 7 lines of assembly code in memory (first 7 addresses). When jump or branch, we go to much larger address where nothing is written, resulting in a blank data output.
Interrupt architectures generally always automatically mask interrupts upon receiving an interrupt. Briefly but completely describe why this is a good approach, and a better approach than attempting to rely on masking the interrupts under program control.
Instantly masking interrupts is better because you don't want one interrupt signal to create multiple interrupts. Masking the interrupt manually creates rooms for error and adds time from an interrupt triggering to interrupts being disabled. This makes it possible for the computer to process one interrupt signal as multiple different interrupts.
Briefly describe whether the "instruction memory" part of the MEMORY module is bit, byte, halfword, word, or maxword addressable. Fully explain your answer.
Instruction memory is word addressable. This is because instructions are the length of words. Even though we input a byte address into the MEMORY module, those bytes are "adapted" into words using each chunk of 4 bytes.
We generally consider interrupts "asynchronous" in nature. However, the RISC-V MCU processes everything synchronously. Briefly describe what it means for the interrupts to be asynchronous and how exactly the MCU processes them in a synchronous manner.
Interrupts being asynchronous means that they are processed and acted upon instantly after being received. Regardless of where you are in program flow, jumping to an interrupt program can happen at any point. The MCU processes them in a synchronous manner by checking interrupt status via FSM. Interrupts are detected at the end of the execute or writeback state, meaning that it has to synchronously line up with the end of an instruction.
Briefly explain the advantage of making an FSM, such as the one you used in this experiment, independent of external factors such as how much data the design will process.
It allows for more flexibility because the FSM can be parametrized, having the ability to be reused with different amounts of data.
Briefly but completely describe why the load-type instructions (lb,lbu,lh,lhu, and lw) require three cycles to execute.
Load-type instructions need an extra FSM state, the writeback state, because memory has a synchronous read. Every instruction needs one clock cycle to read the instruction from memory, then another cycle to execute the function. However, load-type instructions read from memory AGAIN and put the value in a register. They need one more cycle to read the memory address to be loaded.
Briefly describe how the MCU differentiates between load/store and Input/Output instructions. For this problem, we're not talking about the opcodes associated with those instructions.
Load/store instructions are associated with physical data memory, while I/O instructions are purely for I/O memory. These instructions look the same to the assembler, but the MCU differentiates them by checking the address, where anything above 0x0000FFFF is I/O memory while anything equal or below is data memory.
Briefly describe whether the MEMORY module in general is bit, byte, halfword, or word addressable. Fully explain your answer.
MEMORY module is byte addressable. Every address we feed into the memory represents bytes (each individual address in memory is one bytes of data). Even though it operates in words for instructions, it has to convert the individual bytes into words by grouping 4 at a time.
I simplified my design such that the included FSM contains one less state than the previous design iteration. Briefly explain whether I reduced the memory requirements for the design or not.
Memory requirements were not necessarily reduced. States are stored as bits in memory, i.e. 3 states are represented by 2 bits. Removing one or a couple states wouldn't have an impact on the size of needed memory space unless the required number of bits changes.
Briefly explain whether a Moore-type output can act like a Moore-type or Mealy-type output.
Moore-type outputs can only act like a Moore-type output. They are of synchronous nature, being tied to the states and the transitions between them. They cannot be changed asynchronously.
If the PC were to advance every clock cycle, could the RISC-V Otter memory output ever show the data associated with the current value on the PC's output? In other words, could the output of the memory ever be associated with the current output of the PC. Briefly but fully explain your answer in terms of the operating characteristics of the MEMORY module.
No, the MEMORY module is clock dependent. By the time the data has been written to the MEMORY module, a clock cycle has passed and the PC would already have output the next set of data.
Could you use the addi instruction to add an immediate value of 0x7421 to another register? Briefly explain why or why not.
No, the addi instruction's immediate width is 12 bits, while 0x7421 is 16 bits long.
Is it possible to have two of the same labels in an assembly language program? Briefly but completely explain. If this is possible, show an example in your explanation.
No, you can't use two labels with the same name in assembly. Although the labels can have different addresses/values, using those labels in jump and branch instructions won't work because the assembler has no way or knowing which label the instruction is referring to.
Can you write a RISC-V CPU assembly language program that "stops running"? Briefly explain your answer.
No, you cannot write an assembly language program that "stops running". This is because they are associated with "embedded systems", where one of the main characteristics of the program is to run, keep running, and never stop running unless you remove power from the underlying hardware. There are no specific instructions that explicitly direct the computer to "stop executing instructions".
Word on the street is that polling is bad because it makes your programs operate "less good". My RISC-V application uses a few different polling constructs; does this make me a bad programmer? Briefly but completely explain.
Not necessarily, because the "correct" method for input processing depends on the program. Polling does occupy the MCU, and there can be a large delay between status checks based on program size, but this isn't an issue if there aren't any other important tasks for the MCU to do and the priority of input processing isn't very high. On the other hand, polling is bad if there are important tasks while stuck in the polling and/or you need to process inputs quickly.
Briefly describe the difference between port mapped I/O and memory mapped I/O.
Port mapped I/O and memory mapped I/O refer to the way input and output memory is stored. Port mapped I/O: -accesses external devices using unique ports IDs -has a separate address space from data memory -has specific IN-type and OUT-type instructions to address those external ports. Memory mapped I/O: -uses memory access instructions to handle I/O -addresses in the I/O memory space correspond to individual external devices -loading/storing from memory using that "special address" is equivalent to inputting or outputting data to a particular external device -each I/O device has its own unique address similar to port address in port mapped I/O -shares the address space with the data memory.
What is the minimum execution time that an ISR requires? This is the time from when the MCU switches to the interrupt state to when the processor begins executing the next intended instruction, which was scheduled to be executed before the interrupt processing started. Provide a concise answer with adequate description. Assume the interrupts return from the ISR in the disabled state.
Since the ISR returns with interrupts disabled, there has to be an instruction to clear the MPIE bit to prevent MSTATUS from being set to 1. This requires 2 instructions, with an additional "mret" to return from the ISR. This will take 6 clock cycles. Considering it takes one clock cycle to go from the interrupt state to the fetch state, an interrupt will take a minimum of 7 CLOCK CYCLES from the time it's registered to the time it's done being processed.
Program control instructions rely on labels in the code to be encoded and subsequently work properly. If you look at the machine code for a given program, it contains no labels. Briefly explain how the machine code gets away with not encoding labels.
Program control instruction use labels to tell the program where to jump to, but machines code just takes in relative addresses when doing jumps and branches so it doesn't need labels.
We all know the stack for its push and pop operations, but there are no push and pop instructions in the RISC-V ISA. Show the two versions of how we implement both push and pop operations using the RISC-V ISA (show two sets of code for each the push and pop operations).
Pushing into x8: addi sp, sp, -4 sw x8, 0(sp) OR sw x8, -4(sp) addi sp, sp, -4 Popping into x8: addi sp, sp, 4 lw x8, -4(sp) OR lw x8, 0(sp) addi sp, sp, 4
List the six RISC-V OTTER MCU instruction formats.
R-type, I-type, S-type, B-type, U-type, J-type
Difference between RAM and ROM
RAM: - read and write - volatile (data lost on power down) ROM: -read only -non-volatile (data not lost on power down)
We often consider the ISR code as having a "higher priority" than the non‐interrupt code. Briefly but fully explain this concept.
Regardless of where the program is in non-interrupt code, after an interrupt, the ISR code will "instantly" take over. This means that the ISR code has a higher priority, since it can take the place of a non-interrupt code in program flow at any point.
Briefly explain why stack overflow and underflow are major issues in assembly language programs.
Since the boundaries of different memory segments are arbitrary (i.e. there's no actual barrier between the two segments), it's possible for the stack to start overwriting other areas of memory if the program pushes too much, i.e. the stack pointer progresses into the data segment of memory and begins overwriting important data after every new push. Stack underflow can also occur when the program tries to pop off the stack when there's nothing on the stack, which can result in a breakdown of the desired behavior.
If Moore-type FSMs are slower, briefly explain why all FSMs design are not Mealy-type FSMs.
Since they have synchronous outputs following state transitions, Moore FSMs might be more useful when a circuit needs to adhere to strict timing constraints. They can maintain a stable output regardless of any momentary input fluctuation.
Briefly describe what a t-cycle is in the context of an FSM.
T-cycles are the (clock) cycles an FSM will repeat through in order to execute a program. For an FSM specifically, these t-cycles are just states, where each cycle represents one state and transitions to the next cycle at every clock edge.
I just added 34 new instructions to the RISC-V instruction set to support the application I'm working on. Is the RISC-V MCU still a RISC-V architecture or not? Briefly but fully explain.
Technically yes, but it depends on the complexity of the instructions. The RISC-V ISA was intended to be modular and extendable. Assuming the 34 instructions are custom, the MCU is still considered RISC-V if the instructions are RISC-V ISA compliant: - need to adhere to the defined encoding and format of the existing (original) instructions - uphold the load/store model - don't conflict with existing instructions Despite needing changes to the hardware, the fundamental structure of the MCU will remain RISC-V modeled.
Briefly describe at least two limitations of the RISC-V MCU ALU.
The ALU has no status signals regarding the result of its operations. As a result, there's a risk of things like overflowing the 32-bit width when adding, forcing the programmer to be aware of value maxes. Also, the ALU is limited in its mathematical operations and can't do things like multiplication and division.
Briefly describe whether the FSM used in the RISC-V OTTER MCU is a Mealy or a Moore-type FSM.
The FSM used is a Mealy-type FSM. This is because the outputs rely on the both the state and an external input (opcode). The outputs of the INIT, FETCH, and WRITEBACK states are constant, but the outputs of the EXECUTE state rely on the opcode to represent what instruction is being read, assigning each output to its proper value.
If the RISC-V Otter MCU hardware did not automatically mask the interrupt, there could be a big problem if the MCU could only mask the interrupts under program control. For this question, briefly but completely describe the problem.
The MIE bit must be instantly masked in hardware after receiving an interrupt because the FSM will continue to check for interrupts even while in an interrupt program. If attempting to mask interrupts using instructions under program control, it's likely that the interrupt signal will still be on by the next execution cycle before you can disable interrupts. This increases the likelihood of one interrupt signal triggering multiple interrupts, ruining functionality.
State whether the RISC‐V MCU is a RISC or CISC processor. Support your statement with at least three characteristics regarding those two types of computer architectures.
The RISC-V MCU is a RISC processor. Instructions in our RISC-V MCU are simple, performing one operation at a time, while the ISA of a CISC processor has more complex mathematical operations that require multiple steps. Our MCU's instructions also all have the same clock time, which represents RISC in contrast to the CISC variable clock time based on the instructions complexity. Our RISC-V system clock is relatively fast, while CISC processors will typically have a slower clock.
Briefly describe whether the RISC-V OTTER wrapper registers the input data (as in input/output) or not.
The RISC-V Wrapper does not register the input data. The MCU registers the inputs in the memory module.
What is the maximum number of different unique bits that you could configure the RISC-V MCU to input? Briefly but fully explain. Write an equation; don't generate the final number.
The RISC-V memory has 2^32 addresses total, but 2^16 of those addresses are physical memory, which isn't I/O. Also, each address has 32 bits, so the total number of bits is: (2^32 - 2^16) * 32.
Briefly but completely explain why it is "really hard" to see the outputs of the universal seven-segment display module on the simulator's timing diagram output even though the module has a valid data input.
The SSEG has many internal clock dividers. These clock dividers are used for multiplexing, sending multiple pieces of display information to the output at the same time. Even though the output on the physical board looks good, the simulator isn't capable of accounting for this clock division, resulting in unexpected/weird outputs.
Briefly explain why the two LSBs of the PC's output are not connected to the memory module.
The addresses in memory are BYTE-ORIENTED, the 2 LSBs of the address will remain unchanged when advancing through instructions. Adding '4' to the address will add '1' to the 3rd bit in the address, leaving the 2 LSBs untouched (automatically adjusted my MEMORY module to convert bytes into words).
My homework assignment is to implement 25 new pseudoinstructions. Briefly describe what "entity" I'll be using to complete this assignment.
The assembler is what translates pseudoinstructions into base instructions, so you would need to alter the assembler to recognize and convert those new pseudoinstructions.
You wrote assembly code for this experiment. Briefly but completely explain whether this code was software, firmware, or Delaware.
The assembly code was firmware. It was simulated to be built into the hardware's memory, a single-purpose embedded system. This instruction memory is read-only, and runs permanently in the hardware.
Briefly describe who or what decides on the number of t-cycles a given computer architecture uses.
The computer hardware establishes the lower limit for the number of cycles, but the designers of the computer architecture decide the properties of the hardware, therefore controlling the number of t-cycles. Our hardware forces us to have 3 total t-cycles because reading from memory is synchronous. Our computer has to fetch and execute every instruction, so it's stuck spending the first cycle reading the instruction and the second cycle carrying out the function. The synchronous reading also requires one extra cycle for writeback for load instructions, since we have to read from memory after executing.
How much memory do the control units in this experiment contain? (BEFORE INTERRUPTS)
The control units contain 2-bits of memory. This comes strictly from the FSM because it has 4 states (init, fetch, execute, writeback). There is no memory contribution from the decoder control unit because it is a combinatorial circuit.
You used a debounce module in this experiment. This module won't catch all possible signals, however. What is the minimum signal duration that this debounce is guaranteed to pass along as a valid signal (as opposed to noise)? State your answer in system clock cycles. Fully explain your answer; you'll need to look at the Verilog model for the debounce to answer this question.
The debounce inout has to be stable for 128 clock cycles before the debouncer passes it along as a valid signal. R_count is an internal count which gets reset when the input is different from the input on the previous clock cycle. The data width for R_count is 8 bits, and the output is driven when the 8th bit is 1, meaning the input has to not change for 2^7 clock edges.
Briefly describe what (or who) determines the number of instruction formats a given instruction set contains.
The designer of the ISA determines the number of instruction formats a given instruction set contains. Rest of the computer is built around how those instructions are formatted.
The design of the RISC-V MCU ISA intentionally shares as many fields as possible in the six different instruction formats. Briefly explain the reason why the ISA designers did this.
The designers did this to minimize hardware and complexity. By sharing as many fields as possible, you won't need as many modules that depend on the format of the instruction. For example, the source registers in R-type, S-type and B-type are in the same location, allowing the hardware to "not care" what the type is when extracting those addresses.
Briefly but completely state and explain in your own words the two main aspects of the modern digital design paradigm.
The digital design paradigm consists of MODULAR and HIERARCHICAL aspects. Modular means making individual modules that perform and solve a smaller part of the solution. Hierarchical is combining the functions of those unique modules into a higher-level module which solves the entire solution.
Based on the state diagram in Figure 23, estimate (in terms of clock cycles) how long the interrupt signal could be asserted but not having the MCU enter the interrupt signal. Briefly but completely explain your estimate. Assume the interrupt is unmasked.
The interrupt signal could be on for less than threes cycles for the MCU to not detect it. The FSM only goes to the ISR once the current instruction is completed. If the interrupt signal begins at the start of an instruction, it will be processed after three clock cycles (normal and load instructions).
Briefly explain what attribute of the RISC-V MCU is preventing you from executing all 2-cycle instructions in one clock cycle.
The memory having a synchronous read forces all instructions to take at least 2 clock cycles. The FSM sends the signal to read the next instruction, but has to wait a whole clock cycle before getting the instruction because of the synchronous read.
For the RISC-V MCU, there is only one state associated with the interrupt cycle, which means that the FSM only requires one clock cycle to complete the interrupt cycle. Briefly but completely describe in general what dictates how many states (or clock cycles) a given MCU requires for the interrupt cycle. This question considers "states" and "clock cycles" as the same thing.
The number of clock cycles a given MCU requires for the interrupt cycle depends on how much the device allows one to do with interrupts. Devices that allow for more complex interrupt instructions would in turn require more clock cycles for the instructions to complete.
Which signal(s) in the control units represent the memory elements for the control unit.
The present state of the FSM represents the memory elements for the control unit because it signifies whatever state the FSM is currently in (with states being the memory in FSM).
There is obviously no "stack" module in the RISC-V MCU architecture diagram. Where exactly is the stack then on the RISC-V MCU?
The stack is stored in data memory. Using the stack involves traversing addresses in relation to the initialized starting address (which is address 0xFFFF in our RISC-V OTTER). The "location" of the stack is kept track of using "sp" (the x2 register), where it marks the address of the most recently added value.
What is the official term for the item the stack pointer is pointing at in the RISC-V MCU hardware?
The stack pointer points to the top of the stack, i.e. the address of the most recent value to be pushed onto the stack.
If the RISC‐V Otter MCU hardware did not automatically mask the interrupt, it would be problematic to do so under program control. Briefly describe how you could "add some hardware" to the RISC‐V Otter MCU that would ensure that not disabling interrupts upon acting on an interrupt (and thus relying on disabling interrupts under program control) could actually work.
The problem would be that it takes too much time to manually disable interrupts, so that a single interrupt signal could trigger multiple times. You could add one-shot hardware such that an interrupt will only be on for 3 clock cycles, which is enough to always be detected but too short to detect twice. This would ensure the interrupt always being off by the time the ISR starts, so there can be a larger time before needing to disable interrupts (to within reasonable time expectation for the next interrupt) such that you can manually disable interrupts in program control.
Can I possibly use the RISC-V to implement a program that utilizes 40 stacks? If so, briefly but completely explain how this can be done using the ISA and not changing hardware. Assume the amount of memory is not an issue for this problem.
The single existing stack is arbitrary in terms of location and size because we implement it by simply storing data in sequential addresses while keeping track of its location. It is theoretically possible to have as many stacks as memory size allows, since the only binding characteristic is the stack pointer which would need to be kept track of. The stack pointer is typically registered (in x2) and there are only 31 usable registers, but stack pointers could be stored in memory assuming the programmer can keep track of them properly.
Briefly explain why this experiment asked you to include the dump file associated with the assembly language program in the lab submission.
The test bench outputs of the memory will represent the machine code of instructions from the dump file as the PC steps through them. Including the dump file makes it easier to confirm that the memory module is outputting the proper instructions in the proper order.
We use the stack for "general data storage", but we typically use the stack to store information in two scenarios. What are those two scenarios and what information does the stack store?
The two scenarios are for saving return address lines for subroutine calls and also saving data values in registers that are being changed to a different value temporarily.
Despite not mentioning the topics much in this course, setup and hold times are important in digital design. Your experiment worked, so briefly describe how this experiment handled meeting setup and hold time issues.
The wrapper clock divides so the signal has more time to be stable.
Why is it that we need to match call/return instruction pairs (meaning the order they are called in matters) but we don't need to follow a similar approach with push/pop pairs. Briefly but fully explain.
There must be a return instruction after a call instruction because a subroutine would end up nowhere and never finish its task without it. With push and pop pairs, all you need is the specification of the locations within the stack of where one is pushing and popping instructions. The order doesn't matter because you can push and pop at anytime, one does not have to come before the other.
You can use either the jal or jalr instruction to call subroutines, but you can only use the jalr instruction to return from subroutines. Briefly explain why this is the case.
They both work when calling subroutines because they both will take an immediate value as the address destination and store the return address in some designation register (x1 by default). Only jalr works when returning because the return needs to reference the register storing the return address. jal only takes an immediate value in its address input, meaning it can't be used to access the address to return to (the next address prior to calling into the subroutine).
What is the significance of this value: -559038737?
This value is 'DEADBEEF' in hex, an odd value that can be easily identified in a simulation. This is a good 'default' value for something like a case statement. (if used in the ALU and alu_fun is a value that doesn't correspond to a specified operation, the output would be DEADBEEF, telling the human debugging my hardware that there is no operation set for that specific alu_fun value)
The problem described in the previous problem can be avoided, thus making it possible to disable interrupts under program control without compromising the overall operation of the MCU. Describe how the situation can be avoided when the MCU acts on an interrupt.
Using a one-shot signal hardware module can make it possible to disable interrupts under program control by shortening any interrupt signals so they aren't long enough to register more than once. The minimum pulse width to ensure the FSM will catch an interrupt is 3 clock cycles, so de-actuating after 3 clock cycles means that a signal can't be caught more than once, allowing a delay before disabling interrupt detection.
Describe whether you implemented your circuit using a Mealy or Moore-type FSM. Briefly state the reasons why you choose one FSM model over the other.
We used a Mealy FSM because we needed an asynchronous CLR, setting the counters to 0 during the clock transition.
You can typically use assembly language to make a given program written in a higher-level language run faster. Briefly but fully explain this concept.
When writing in a higher-level language, you write in more abstract pseudocode and expect the compiler to fill in the blanks when converting it to machine code. This might create unnecessary code that takes extra time and slows down the program. However, when you write in assembly language, you are telling the compiler EXACTLY what you want the program to do, making the conversion to machine code more direct. The compiler will have to do less "fill in work" and the programmer has more control over the efficiency.
If you were not able to use a LUT for this experiment, briefly but completely describe the program you would need to write in order to translate a given BCD number into its 7‐segment display equivalent.
Without a lookup table, you would need a lot of IF statements, one for each BCD number and its SSEG equivalent. This could turn into a CASE statement, checking each case of a given BCD value to see if it matches each "beq" statement, then branch to the associated label where it sets the display to its correct value.
Based on your circuit design in this experiment, can you determine how many clock cycles after the button press your design requires to complete the assigned task? If so, how many clock cycles does your design require to generate the requested result? If not, explain why it is not possible to calculate the number of clock cycles.
Yes, it required 48 clock cycles. It took 16 cycles to evaluate ROM, 16 cycles to display bottom RAM, 16 cycles to display top RAM (each module has 16 addresses).
Briefly explain whether the RISC-V Otter can operate on both signed and unsigned data.
Yes, the RISC-V Otter's instruction set contains instructions to cater to both signed and unsigned data. When loading into memory, bytes and halfwords are sign-extended to protect their values.
Did the universal seven-segment display device used in this experiment employ lead zero blanking or not? Briefly but completely answer this question in such a way as I know that you know what lead zero blanking is.
Yes, the SSEG uses lead-zero blanking. We could tell because the leading digit on the display WASN'T a '0' when displaying numbers less than 4 digits. It instead left the lead zeros blank.
Can you use the same I/O port address for both inputs and outputs in the same complete RISC-VMCU implementation? Briefly explain.
Yes, you can use the same addresses for inputs and outputs. The MCU has different hardware for input and output, so the output will ignore the input, and the input ignores the output.
Is it possible to have two or more labels in an assembly language program with the same numerical value? Briefly but completely explain. If this is possible, show an example in your explanation.
Yes. A label's associated value depends on the next instruction in the sequence of code. Every time there's an instruction, the address increments. A label with no instruction immediately after it will be assigned the address of the next instruction. As a result, the two labels could have the same value if the next instruction for BOTH labels is the same. LOOP1: LOOP2: mv x10, x15 (both labels correspond to that instruction)
I wrote an interrupt service routine that always calls a single subroutine, though it calls that subroutine multiple times in a non‐nested manner. Briefly but fully explain whether I should store the return address before my ISR makes those subroutine calls.
You should store the return address before the ISR makes a subroutine call in case the MCU jumps back to the ISR while in the subroutine. It's important to save the previous ra and store it so that after the ISR's subroutine call, the main program can execute back to normal.
Here is a quote from this experiment: "If you write your program in such a way that your program requires a stack"... So you often have a choice of when you use a stack or not. Briefly explain what determines whether your program requires a stack or not.
Your program needs a stack when there are subroutines where you write into registers. The main purpose of the stack is to preserve context, which is important when the calling code has important register values and the subroutine uses those registers in its operation. If you don't push the altered registers onto the stack at the start, you run the risk of ruining functionality of the main program. It is also necessary when using nested subroutines, because each subroutines return address needs to be preserved in the correct order. Without the stack, a nested subroutine will overwrite the main subroutine's return address.
In computerland, we typically increase the bit-width of data in two ways. List those two ways and describe what type of data they are used on.
Zero-padding is used to increase the bit-width of unsigned data by adding zeros to the left of the existing value, preserving the value. Sign-extending is used with signed data by repeating the signed bit to the left of the existing value, which preserves the value of the data once 2s complemented.
In assembly language-land, we refer to instructions that do nothing as "nops" (pronounced "know ops"). In academia, we refer to "nops" as administrators. The nop instruction in RISC-V MCU is pseudoinstruction. Show at least four different ways you can implement a nop instruction in RISC-V assembly language.
add x10, x11, x0 sub x10, x11, x0 andi x10, x11, -1 or x10, x11, x0 xor x10, x11, x0
There are five non-nop instructions in the sample program. Each of these instructions includes a comment that contains an "equation of importance", which you used in this experiment to prove that your hardware was working correctly. For this question, completely and explicitly explain how we formed that desired value on the right side of the equation relative to the given program. *LOOK AT LAB FOR REFERENCE*
jal - the jal instruction expects an output of 8, associated with the address it's feeding the PC, because it is jumping to the "dog" label, storing that return address in x0. Since the "dog" label is on the third placeholder instruction, the expected output is 8. jalr - the jalr instruction expects an output of 4 (and a PC input of 4) because it wants to jump to the address calculated by adding the immediate value of -8 and the value in register x20, storing that return address in x0. Since x20 = rs1 and rs1 = 12, the output is 4 (-8+12). beq - the beq instruction expects an output of 4 because it branches to the "cat" label if the value in x10 equals x10. Since that condition is always true, it branches to "cat", the label for the second placeholder instruction, producing an expected address result of 4. sw - the sw instruction expects an output of 12 because it is trying to add the value of x20 and the immediate value, storing it in x10. Since the output we care about is what value is being outputted from the IMMED_GEN, it will simply be the immediate value that the instruction takes, i.i the offset of 12. lui - the lui instruction expects an output of 0x000FF000 because it is trying to load an immediate value into x0. Since the immediate value is 255, and 255 is equivalent to 0x000FF000, the output from the IMMED_GEN module is 0x000FF000.
Why does there need to be different inputs associated with the jal and jalr instructions?
jal and jalr have different functions. jal uses an immediate value as a signed offset that will modify the current PC value. jalr also has an offset, but the instruction uses that offset to modify an address in a register to form the absolute address. The new absolute address in the jal is a function of the current PC value, while the absolute address in jalr is not.
Sometimes the "li" pseudoinstruction causes the assembler to generate two instructions and sometimes one instruction. Briefly describe why this is the case and list the two different instructions.
li is a pseudoinstruction for addi and lui. If the immediate value in li is 12 bits or less, the pseudoinstruciton is only represented by an addi (addi has an immediate value of 12 bits). For immediate values larger than 12 bits, the value passed into li will need the lui instruction to add the remaining 20 bits into the destination register.
Describe a situation where a NOP instruction or a NOP-type instruction would be useful.
nop takes the typical 2 cycles while making no changes to the MCU, meaning it can be used as a time delay. This can be helpful for debugging in a simulator, allowing you to leave the MCU in a specific state for longer and making it more noticeable.
The RISC-V MCU has 32 "general purpose" registers. Briefly describe why RISC-V MCU programmers should never use registers x1 and x2.
x1 is by default the return address for when the subroutine is called. This value is necessary to control program flow when using subroutines and should never be overwritten. x2 is the default for the stack pointer. The stack's functionality relies on x2 storing the proper location of the stack in memory.
