DIGI ELECS COMPILATION 2
One way to convert BCD to binary using the hardware approach is: a) By using MSI IC circuits b) By using a keyboard encoder c) By using an ALU d) By using UART
Answer: a Explanation: One way to convert BCD to binary using the hardware approach is MSI (medium scale integration) IC circuits.
One way to convert BCD to binary using the hardware approach is ___________ a) With MSI IC circuits b) With a keyboard encoder c) With an ALU d) UART
Answer: a Explanation: One way to convert BCD to binary using the hardware approach is MSI IC (i.e. medium scale integration) circuits.
How many NOT gates are required to implement the Boolean expression: X = AB'C + A'BC? a) 2 b) 3 c) 4 d) 5
Answer: a Explanation: Since in the given expression two inputs are complemented. So, we require two NOT gate at the input. A NOT gate is a basic gate which accepts a single input and produces a single output, which is the inverted version of the input.
What is backplane in LCD? a) The ac voltage applied between segment and a common element b) The dc voltage applied between segment and a common element c) The amount of power consumed d) For adjusting the intensity of the LCD
Answer: a Explanation: The ac voltage applied between segment and a common element is called the backplane(bp). In which each segment is driven by an EX-OR gate.
The addition of two decimal digits in BCD can be done through ____________ a) BCD adder b) Full adder c) Ripple carry adder d) Carry look ahead
Answer: a Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in addition by the user converted into binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.
The binary subtraction of 0 - 0 = ? a) Difference = 0, borrow = 0 b) Difference = 1, borrow = 0 c) Difference = 1, borrow = 1 d) Difference = 0, borrow = 1
Answer: a Explanation: The binary subtraction of 0 - 0 = 0. Thus, it's difference is 0 as well as it's borrow.
The BCD number 101011 has _______ priority. a) Even b) Odd c) Both even and odd d) Undefined
Answer: a Explanation: The given BCD number 101011 has even priority because it has even number of 1's (i.e. 4).
The number of logic gates and the way of their interconnections can be classified as ____________ a) Logical network b) System network c) Circuit network d) Gate network
Answer: a Explanation: The number of different levels of logic gates is represented in a fashion which is known as a logical network.
Let the input of a subtractor is A and B then what the output will be if A = B? a) 0 b) 1 c) A d) B
Answer: a Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the output.
Let A and B is the input of a subtractor then the output will be ___________ a) A XOR B b) A AND B c) A OR B d) A EXNOR B
Answer: a Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference output of a subtractor is given by AB' + BA' and this is the output of a XOR gate. So, the final difference output is AB' + BA'.
How many types of parity bits are found? a) 2 b) 3 c) 4 d) 1
Answer: a Explanation: There are two types of parity bits, namely even parity and odd parity. In even parity, a 1 bit is added in order to make a group of data bits have even number of 1s. While, in odd parity, a 1 bit is added in order to make a group of data bits have odd number of 1s.
Total number of inputs in a half adder is __________ a) 2 b) 3 c) 4 d) 1
Answer: a Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.
What is ripple carry adder? a) The carry output of the lower order stage is connected to the carry input of the next higher order stage b) The carry input of the lower order stage is connected to the carry output of the next higher order stage c) The carry output of the higher order stage is connected to the carry input of the next lower order stage d) The carry input of the higher order stage is connected to the carry output of the lower order stage
Answer: a Explanation: When the carry output of the lower order stage is connected to the carry input of the next higher order stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.
How many basic binary subtraction operations are possible? a) 1 b) 4 c) 3 d) 2
Answer: b Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible. 0 - 0 = 0 0 - 1 = 1 ( Borrow 1) 1 - 0 = 1 1 - 1 = 0
What control signals may be necessary to operate a 1-line-to-16 line decoder? a) Flasher circuit control signal b) A LOW on all gate enable inputs c) Input from a hexadecimal counter d) A HIGH on all gate enable circuits
Answer: b Explanation: A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder because enable pins are usually, active-low pins.
How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol? a) A bubble indicates active-HIGH b) A bubble indicates active-LOW c) A triangle indicates active-HIGH d) A triangle indicates active-LOW
Answer: b Explanation: A bubble indicates active-LOW in a decoder always. Enable pin of the decoder is usually active-LOW and is triggered on input being at 0.
Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________ a) Determine sign and magnitude b) Reduce propagation delay c) Add a 1 to complemented inputs d) Increase ripple delay
Answer: b Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It reduces the propagation delay by making the hardware more complex. The ripple carry design is converted in such a way that carry over a group of bits of the adder becomes 2-level logic.
One that is not the outcome of magnitude comparator is ____________ a) a > b b) a - b c) a < b d) a = b
Answer: b Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. In a digital comparator, only 3 outputs are possible (i.e. A = B, A > B, A < B). So, a - b is incorrect option.
In a multiplexer the output depends on its ____________ a) Data inputs b) Select inputs c) Select outputs d) Enable pin
Answer: b Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.
What are the two types of basic adder circuits? a) Sum and carry b) Half-adder and full-adder c) Asynchronous and synchronous d) One and two's-complement
Answer: b Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.
The summing outputs of a half or full-adder are designated by which Greek symbol? a) Omega b) Theta c) Lambda d) Sigma
Answer: d Explanation: The summing outputs of a half or full-adder are designated by "sigma" which is a Greek symbol. This same symbol is used to signify the Minterms in case of an SOP expression.
LCDs operate from a voltage ranges from ___________ a) 3 to 15V b) 10 to 15V c) 10V d) 5V
a
The direction of electric field in an LCD is determined by ___________ a) the molecule's chemical structure b) Crystalline surface structure c) Molecular Orbital Theory d) Quantum Cellular Automata
a
The full form of LCD is ____________ a) Liquid Crystal Display b) Liquid Crystalline Display c) Logical Crystal Display d) Logical Crystalline Display
a
All the comparisons made by comparator is done using ____________ a) 1 circuit b) 2 circuits c) 3 circuits d) 4 circuits
a Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. Because, all the input is compared to each other, therefore it is possible only by using 1 circuit.
Electro-optical effect is produced in ___________ a) LED b) LCD c) OFC d) OLED
b
In 7 segment display, how many LEDs are used? a) 8 b) 7 c) 10 d) 9
b
TTL 74LS85 is a _____________ a) 1-bit digital comparator b) 4-bit magnitude comparator c) 8-bit magnitude comparator d) 8-bit word comparator
b
A code converter is a logic circuit that _____________ a) Inverts the given input b) Converts into decimal number c) Converts data of one type into another type d) Converts to octal
c
LCDs operate from a frequency ranges from ___________ a) 10Hz to 60Hz b) 50Hz to 70Hz c) 30Hz to 60Hz d) None of the Mentioned
c
The first LCDs became commercially available in ___________ a) 1950s b) 1980s c) 1960s d) 1970s
c
The output sum of two decimal digits can be represented in ____________ a) Gray Code b) Excess-3 c) BCD d) Hexadecimal
c
Which of the following expressions is in the product-of-sums form? a) (A + B)(C + D) b) (AB)(CD) c) AB(CD) d) AB + CD
Answer: Explanation: (A + B)(C + D) represents the product-of-sums form.
A truth table with output columns numbered 0-15 may be for which type of decoder IC? a) Hexadecimal 1-of-16 b) Dual octal outputs c) Binary-to-hexadecimal d) Hexadecimal-to-binary
Answer: a Explanation: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2n outputs. A truth table with output columns numbered 0-15 may be for Hexadecimal 1-of-16. Because, hexadecimal occupies less space in a system.
In a comparator, if we get input as A>B then the output will be ____________ a) 1 b) 0 c) A d) B
Answer: a Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. If A > B, it means that it satisfies one of the condition among three. Hence the output will be 1.
If two numbers are not equal then binary variable will be ____________ a) 0 b) 1 c) A d) B
Answer: a Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. In a digital comparator, only 3 outputs are possible (i.e. A = B, A >B, A < B). Other than this, the output will be 0.
How many inputs are required for a digital comparator? a) 1 b) 2 c) 3 d) 4
Answer: a Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. Thus, there are two inputs required for a digital comparator (i.e. A & B).
The serial format for transmitting binary information uses __________ a) A single conductor b) Multiple conductors c) Infrared technology d) Fiber-optic
Answer: a Explanation: A conductor accepts the whole data and arranges it in a serial manner, which is transmitted as binary information. In serial transmission, data is transmitted bit by bit while in parallel transmission data is transmitted simultaneously.
A digital multiplexer is a combinational circuit that selects ___________ a) One digital information from several sources and transmits the selected one b) Many digital information and convert them into one c) Many decimal inputs and transmits the selected information d) Many decimal outputs and accepts the selected information
Answer: a Explanation: A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line depending on the status of the select lines. That is why it is also known as a data selector.
A digital system consists of _____ types of circuits. a) 2 b) 3 c) 4 d) 5
Answer: a Explanation: A digital system consists of two types of circuits and these are a combinational and sequential logic circuit. Combinational circuits are the ones which do not depend on previous inputs while Sequential circuits depend on past inputs.
The simplified expression of full adder carry is ____________ a) c = xy+xz+yz b) c = xy+xz c) c = xy+yz d) c = x+y+z
Answer: a Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.
The carry propagation delay in 4-bit full-adder circuits ___________ a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed b) Is normally not a consideration because the delays are usually in the nanosecond range c) Decreases in direct ratio to the total number of full-adder stages d) Increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
Answer: a Explanation: A full adder is a digital circuit with 3 inputs and two outputs SUM and CARRY. The carry propagation delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are performed.
Which error detection method consists of just one redundant bit per data unit? a) Simple parity check b) Two-dimensional parity check c) CRC d) Checksum
Answer: a Explanation: A parity checker is an error detection method used for the purpose of detecting errors that may have been incorporated during transmission. Simple parity check method consists of just one redundant bit per data unit. It is again classified as even parity and odd parity.
A procedure that specifies finite set of steps is called ____________ a) Algorithm b) Flow chart c) Chart d) Venn diagram
Answer: a Explanation: A procedure that specifies finite set of steps is called algorithm, While a flowchart is a pictorial representation of the algorithm.
What is a parity bit? a) An error detection is achieved by adding an extra bit b) After addition, the carry is found c) Bit generated during data transmission d) After addition, the total number of bits
Answer: a Explanation: A simple form of error detection is achieved by adding an extra bit to the transmitted word. The additional bit is known as parity bits.
An identify comparator is defined as a digital comparator which has ____________ a) Only one output terminal b) Two output terminals c) Three output terminals d) No output terminal
Answer: a Explanation: An Identity Comparator is a digital comparator that has only one output terminal for when A = B either "HIGH" A = B = 1 or "LOW" A = B = 0.
Which of the following is an important feature of the sum-of-products form of expressions? a) All logic circuits are reduced to nothing more than simple AND and OR operations b) The delay times are greatly reduced over other forms c) No signal must pass through more than two gates, not including inverters d) The maximum number of gates that any signal must pass through is reduced by a factor of two
Answer: a Explanation: An important feature of the sum-of-products form of expressions in the given option is that all logic circuits are reduced to nothing more than simple AND and OR operations. Sum Of Product means it is the sum of product terms containing variables in complemented as well as uncomplemented forms.
The hexadecimal number (4B)16 is transmitted as an 8-bit word in parallel. What is the time required for this transmission if the clock frequency is 2.25 MHz? a) 444 ns b) 444 s c) 3.55 s d) 3.55 ms
Answer: a Explanation: Because the clock pulse of 4-bit transmits the data of 8-bit word in parallel mode and this transmission is done at 2.25 MHz frequency. We know that: f=1/t and we can find the time required for this transmission by the clock pulse. Therefore, time = (1/2.25) = 0.4444 us = 444.44 ns ~ 444ns.
Code is a symbolic representation of ___________ a) Discrete information b) Continuous information c) Decimal information into binary d) Binary information into decimal
Answer: a Explanation: Code is a symbolic representation of discrete information. Codes can be anything like numbers, letter or words, written in terms of group of symbols.
Controlled buffers can be useful __________ a) To control the circuit's output into the bus b) In comparison of component's output with its input c) In increasing the output from its low input d) All of the Mentioned
Answer: a Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match the output of one of several components. By placing a controlled buffer between each component output and the bus, you can control whether that component's output is fed onto the bus or not.
Controlled buffers can be useful ____________ a) To control the circuit's output into the bus b) In comparison of component's output with its input c) In increasing the output from its low input d) All of the Mentioned
Answer: a Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match the output of one of several components. By placing a controlled buffer between each component output and the bus, you can control whether that component's output is fed onto the bus or not.
Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line? a) Data Selector b) Data distributor c) Both data selector and data distributor d) DeMultiplexer
Answer: a Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is __________ a) Ex-NOR gate b) OR gate c) Ex-OR gate d) NAND gate
Answer: a Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR produces output for even number of 1's or all 0s, while EXOR produces output for odd number of 1's.
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is ____________ a) Ex-NOR gate b) OR gate c) Ex-OR gate d) NAND gate
Answer: a Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR produces output for even number of 1's or all 0s, while EXOR produces output for odd number of 1's.
Each "0" entry in a K-map square represents: a) A HIGH for each input truth table condition that produces a HIGH output b) A HIGH output on the truth table for all LOW input combinations c) A LOW output for all possible HIGH input conditions d) A DON'T CARE condition for all possible input truth table combinations
Answer: a Explanation: Each "0" entry in a K-map square represents a LOW output for all possible HIGH input conditions. Thus, it represents a Maxterm.
Each "1" entry in a K-map square represents: a) A HIGH for each input truth table condition that produces a HIGH output b) A HIGH output on the truth table for all LOW input combinations c) A LOW output for all possible HIGH input conditions d) A DON'T CARE condition for all possible input truth table combinations
Answer: a Explanation: Each "1" entry in a K-map square represents a HIGH for each input truth table condition that produces a HIGH output. Thus, it represents a minterm.
Which one is a basic comparator? a) XOR b) XNOR c) AND d) NAND
Answer: a Explanation: Generally, an XNOR outputs high for even number of 1s or all 0s and outputs low for otherwise. Thus, an XNOR gate is a basic comparator, because its output is "1" only if its two input bits are equal.
The primary use for Gray code is ___________ a) Coded representation of a shaft's mechanical position b) Turning on/off software switches c) To represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery d) To convert the angular position of a shaft on rotating machinery into hexadecimal code
Answer: a Explanation: Gray code is useful because only one bit changes at a time, which is implemented easily in Coded representation of a shaft's mechanical position. In Gray Code, every sequence of successive bits differs by 1 bit only.
Half subtractor is used to perform subtraction of ___________ a) 2 bits b) 3 bits c) 4 bits d) 5 bits
Answer: a Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.
Which IC is used for the implementation of 1-to-16 DEMUX? a) IC 74154 b) IC 74155 c) IC 74139 d) IC 74138
Answer: a Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.
The Boolean expression Y = (AB)' is logically equivalent to what single gate? a) NAND b) NOR c) AND d) OR
Answer: a Explanation: If A and B are the input for AND gate the output is obtained as AB and after inversion we get (AB)', which is the expression of NAND gate. NAND gate produces high output when any of the input is 0 and produces low output when all inputs are 1.
If A and B are the inputs of a half adder, the carry is given by __________ a) A AND B b) A OR B c) A XOR B d) A EX-NOR B
Answer: a Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.
If A, B and C are the inputs of a full adder then the carry is given by __________ a) A AND B OR (A OR B) AND C b) A OR B OR (A AND B) C c) (A AND B) OR (A AND B)C d) A XOR B XOR (A XOR B) AND C
Answer: a Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).
It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of ___________ a) Inputs b) Outputs c) Selection lines d) Enable lines
Answer: a Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of inputs.
Which statement below best describes a Karnaugh map? a) It is simply a rearranged truth table b) The Karnaugh map eliminates the need for using NAND and NOR gates c) Variable complements can be eliminated by using Karnaugh maps d) A Karnaugh map can be used to replace Boolean rules
Answer: a Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth table having a specific number of cells or squares, where each cell represents a Maxterm or a Minterm.
If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is _______ a) Indeterminate b) 42 c) Even d) Odd
Answer: a Explanation: Odd parity bit is 1 when the group of data bits consist of even number of 1s. So to make the group of data bits have odd number of 1s, 1 extra bit is added. If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is indeterminate because it is applicable only for 6-bit symbol.
The full subtractor can be implemented using ___________ a) Two XOR and an OR gates b) Two half subtractors and an OR gate c) Two multiplexers and an AND gate d) Two comparators and an AND gate
Answer: b Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR gate.
A serial subtractor can be obtained by converting the serial adder by using the _____________ a) 1's complement system b) 2's complement system c) 10's complement d) 9's complement
Answer: b Explanation: A serial subtractor can be obtained by converting the serial adder by using the 2's complement system. 9's complement and 10's complement are used for decimal numbers while adders deal with binary numbers.
Which error detection method can detect a single-bit error? a) Simple parity check b) Two-dimensional parity check c) CRC d) Checksum
Answer: b Explanation: A single-bit error can be detected by using two-dimensional parity check method. Since, it converts the 4-bit number into 8-bit and count the number of one's.
The selector inputs to an arithmetic/logic unit (ALU) determine the __________ a) Selection of the IC b) Arithmetic or logic function c) Data word selection d) Clock frequency to be used
Answer: b Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values such as NOT, AND and OR and any logical operations.
The selector inputs to an arithmetic/logic unit (ALU) determine the ____________ a) Selection of the IC b) Arithmetic or logic function c) Data word selection d) Clock frequency to be used
Answer: b Explanation: An ALU performs basic arithmetic and logic operations and stores it in the accumulator. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values such as NOT, AND and OR and any logical operations.
Comparators are used in ____________ a) Memory b) CPU c) Motherboard d) Hard drive
Answer: b Explanation: Comparators are used in central processing unit (CPUs). Because all the arithmetic and logical operations are performed in the ALU(Arithmetic Logic Unit) part of the CPU.
Which error detection method involves polynomials? a) Simple parity check b) CRC c) Two-dimensional parity check d) Checksum
Answer: b Explanation: Cyclic Redundancy Check(CRC) involves parity check polynomials. In the even parity case of CRC, the 1-bit is generated by checking the polynomial x+1.
The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as: a) A Karnaugh map b) DeMorgan's second theorem c) The commutative law of addition d) The associative law of multiplication
Answer: b Explanation: DeMorgan's Law: ~(P+Q) <=> (~P).(~Q) Also, ~(P.Q) <=> (~P)+(~Q).
Serial communication can be sped up by __________ a) Using silver or gold conductors instead of copper b) Using high-speed clock signals c) Adjusting the duty cycle of the binary information d) Using silver or gold conductors instead of copper and high-speed clock signals
Answer: b Explanation: For any serial data transmission there is required of continuously data supply and if the input supply (i.e. high speed clock signals) in a high amount the speed of serial communication can be increased. In serial communication, data is transmitted bit by bit. So the use of high speed clock pulses would make the process faster.
Which of the following combinations of logic gates can decode binary 1101? a) One 4-input AND gate b) One 4-input AND gate, one inverter c) One 4-input AND gate, one OR gate d) One 4-input NAND gate, one inverter
Answer: b Explanation: For decoding any number output must be high for that code and this is possible in One 4-input NAND gate, one inverter option only. A decoder is a combinational circuit that converts binary data to n-coded data upto 2n outputs.
For subtracting 1 from 0, we use to take a _______ from neighbouring bits. a) Carry b) Borrow c) Input d) Output
Answer: b Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during addition process.
Full subtractor is used to perform subtraction of ___________ a) 2 bits b) 3 bits c) 4 bits d) 8 bits
Answer: b Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.
If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be __________ a) 0 b) 1 c) Floating d) High Impedance
Answer: b Explanation: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step (i.e 0 - 1 - 1 = 0, borrow = 1).
What are carry generate combinations? a) If all the input are same then a carry is generated b) If all of the output are independent of the inputs c) If all of the input are dependent on the output d) If all of the output are dependent on the input
Answer: b Explanation: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate combinations.
If the number of n selected input lines is equal to 2^m then it requires _____ select lines. a) 2 b) m c) n d) 2n
Answer: b Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines.
By which properties, the orientation of molecules in a layer of liquid crystals can be changed? a) Magnetic field b) Electric field c) Electromagnetic field d) Gallois field
Answer: b Explanation: In LCD, the electric field is induced by a small electric voltage applied across it; Due to which the orientation of molecules in a layer of liquid crystals can be changed.
In which operation carry is obtained? a) Subtraction b) Addition c) Multiplication d) Both addition and subtraction
Answer: b Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 - 1 = 1 (borrow 1).
The flag bits in an ALU is defined as ___________ a) The total number of registers b) The status bit conditions c) The total number of control lines d) All of the Mentioned
Answer: b Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag bits. It is so called because they tend to represent the status of the respect flags after any operation.
What is the indication of a short to ground in the output of a driving gate? a) Only the output of the defective gate is affected b) There is a signal loss to all load gates c) The node may be stuck in either the HIGH or the LOW state d) The affected node will be stuck in the HIGH state
Answer: b Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load gates. This results in information being disrupted and loss of data.
With surface-mount technology (SMT), the devices should __________ a) Utilize transistor outline connections b) Mount directly c) Have parallel connecting pins d) Require holes and pads
Answer: b Explanation: Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is called a surface-mount device (SMD). In the industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board for components not suited to surface mounting such as large transformers and heat-sinked power semiconductors.
What is Manchester carry chain? a) Is a chain of controlled inverter b) Variation of a carry-lookahead adder c) Variation of a full-adder d) Variation of a ripple carry adder
Answer: b Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower the transistor count. However, the carry generating logic depends on the logic to generate the carries in the past.
The basic building blocks of the arithmetic unit in a digital computers are ____________ a) Subtractors b) Adders c) Multiplexer d) Comparator
Answer: b Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
The basic building blocks of the arithmetic unit in a digital computers are __________ a) Subtractors b) Adders c) Multiplexer d) Comparator
Answer: b Explanation: The basic building blocks of the arithmetic unit in digital computers are adders. Since a parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
Let A and B is the input of a subtractor then the borrow will be ___________ a) A AND B' b) A' AND B c) A OR B d) A AND B
Answer: b Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A' AND B).
The design of an ALU is based on __________ a) Sequential logic b) Combinational logic c) Multiplexing d) De-Multiplexing
Answer: b Explanation: The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be broken into identical stages connected in cascade through carries.
The output of a subtractor is given by (if A, B and X are the inputs). a) A AND B XOR X b) A XOR B XOR X c) A OR B NOR X d) A NOR B XOR X
Answer: b Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.
How many select lines are required for a 1-to-8 demultiplexer? a) 2 b) 3 c) 4 d) 5
Answer: b Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.
The inverter can be produced with how many NAND gates? a) 2 b) 1 c) 3 d) 4
Answer: b Explanation: The inverter can be produced with the help of single NAND gate, because we can send a single input twice through the same NAND gate together, thus producing the inverted version of the input as output. It works as an inverter.
The odd parity output of decimal number 9 is ___________ a) 0 b) 1 c) 1001 d) 0011
Answer: b Explanation: The odd parity output of decimal number 9 is 1 because the BCD number for 9 is 1001 and it has even number of 1's.
In a multiplexer, the selection of a particular input line is controlled by ___________ a) Data controller b) Selected lines c) Logic gates d) Both data controller and selected lines
Answer: b Explanation: The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources.
The output of a full subtractor is same as ____________ a) Half adder b) Full adder c) Half subtractor d) Decoder
Answer: b Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C), respectively.
How many AND, OR and EXOR gates are required for the configuration of full adder? a) 1, 2, 2 b) 2, 1, 2 c) 3, 1, 2 d) 4, 0, 1
Answer: b Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.
How many types of digital comparators are? a) 1 b) 2 c) 3 d) 4
Answer: b Explanation: There are two main types of Digital Comparator available and these are: Identity Comparator & Magnitude Comparator. Identity Comparator checks only the equality of the inputs and thus has one output terminal. While Magnitude Comparator checks for greater than, less than as well as equality of the inputs, and thus has 3 output terminals.
How many outputs are required for the implementation of a subtractor? a) 1 b) 2 c) 3 d) 4
Answer: b Explanation: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.
Reflected binary code is also known as ___________ a) BCD code b) Binary code c) ASCII code d) Gray Code
Answer: d Explanation: The reflected binary code is also known as gray code because one digit reflected to the next bit. In Gray Code, every sequence of successive bits differs by 1 bit only.
The carry propagation can be expressed as ________ a) Cp = AB b) Cp = A + B c) All but Y0 are LOW d) All but Y0 are HIGH
Answer: b Explanation: This happens in parallel adders (where we try to add numbers in parallel via more than one adders). A carry propagation occurs when carry from one adder needs to be forwarded to other adder and that second adder is holding the computation (addition) because carry from first adder has not come yet. So, there is a slight delay for second adder and this is known as carry propagation.
A magnitude comparator is defined as a digital comparator which has ____________ a) Only one output terminal b) Two output terminals c) Three output terminals d) No output terminal
Answer: c Explanation: A Magnitude Comparator is a digital comparator which has three output terminals, one each for equality, A = B greater than, A > B and less than A < B.
One way to make a four-bit adder to perform subtraction is by ___________ a) Inverting the output b) Inverting the carry-in c) Inverting the B inputs d) Grounding the B inputs
Answer: c Explanation: A adder is a digital circuit which adds bits along with a carry bit from a previous stage, thus producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input end. So, for subtraction to be performed, all the Bs terminal should be inverted.
A basic multiplexer principle can be demonstrated through the use of a ___________ a) Single-pole relay b) DPDT switch c) Rotary switch d) Linear stepper
Answer: c Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since its behaviour is similar to the multiplexer. There are around 10 digits out of which one is selected one at a time and fed to the output.
Internally, a computer's binary data are always transmitted on parallel channels which is commonly referred to as the __________ a) Parallel bus b) Serial bus c) Data bus d) Memory bus
Answer: c Explanation: A process consists of 3 types of buses: Control Bus, Data Bus and Address Bus. A computer's data is always in the binary form which is stored in the bus that transmits the data on any channels. It doesn't matter that it's in parallel or serial.
BCD adder can be constructed with 3 IC packages each of ____________ a) 2 bits b) 3 bits c) 4 bits d) 5 bits
Answer: c Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.
What is the frequency of a clock waveform if the period of that waveform is 1.25sec? a) 8 kHz b) 0.8 kHz c) 0.8 MHz d) 8 MHz
Answer: c Explanation: By using the formula of frequency, we can find the frequency of clock waveform. Time period(t) of the waveform is = 1.25microseconds f=1/t Where 't' is the time taken by the clock waveform; f=(1/1.25) so, f=0.8 MHz.
Procedure for the design of combinational circuits are: A. From the word description of the problem, identify the inputs and outputs and draw a block diagram. B. Draw the truth table such that it completely describes the operation of the circuit for different combinations of inputs. C. Simplify the switching expression(s) for the output(s). D. Implement the simplified expression using logic gates. E. Write down the switching expression(s) for the output(s). a) B, C, D, E, A b) A, D, E, B, C c) A, B, E, C, D d) B, A, E, C, D
Answer: c Explanation: Combinational circuits are the ones which do not depend on previous inputs and depends only on the present values. The given arrangement A, B, E, C, D is the right sequence for the designing of the combinational circuits.
Controlled inverter is also known as ____________ a) Controlled buffer b) NOT gate c) Both controlled buffer and NOT gate d) Controlled gate
Answer: c Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used between output and a bus so that one can control whether the output is fed to the bus or not.
Controlled inverter is also known as _____________ a) Controlled buffer b) NOT gate c) Both controlled buffer and NOT gate d) Controlled gate
Answer: c Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used between output and a bus so that one can control whether the output is fed to the bus or not.
What is the function of an enable input on a multiplexer chip? a) To apply Vcc b) To connect ground c) To active the entire chip d) To active one half of the chip
Answer: c Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low, indicating it is active either when it is connected to VCC or GND respectively.
Which gates are ideal for checking the parity bits? a) AND b) NAND c) EX-OR d) EX-NOR
Answer: c Explanation: Exclusive-OR gates are ideal for checking the parity of a binary number because they produce an output when the input has an odd number of 1's. Therefore, an even-parity input to an EX-OR gate produces a low output, while an odd parity input produces a high output. While, in case of AND, it produces high output when all inputs are 1 else low. Whereas, NAND, does the opposite, by producing low output when all inputs are 1 else high.
For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is ___________ a) The same as if the carry-in is tied LOW since the least significant carry-in is ignored b) That carry-out will always be HIGH c) A one will be added to the final result d) The carry-out is ignored
Answer: c Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to the final result as a result because carry-in gives output as 1.
The difference between half adder and full adder is __________ a) Half adder has two inputs while full adder has four inputs b) Half adder has one output while full adder has two outputs c) Half adder has two inputs while full adder has three inputs d) All of the Mentioned
Answer: c Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.
Which of the examples below expresses the commutative law of multiplication? a) A + B = B + A b) A • B = B + A c) A • (B • C) = (A • B) • C d) A • B = B • A
Answer: d Explanation: The commutative law of multiplication is (A * B) = (B * A). The commutative law of addition is (A + B) = (B + A).
What is the major difference between half-adders and full-adders? a) Full-adders are made up of two half-adders b) Full adders can handle double-digit numbers c) Full adders have a carry input capability d) Half adders can handle only single-digit numbers
Answer: c Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.
Half-adders have a major limitation in that they cannot __________ a) Accept a carry bit from a present stage b) Accept a carry bit from a next stage c) Accept a carry bit from a previous stage d) Accept a carry bit from the following stages
Answer: c Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.
If A and B are the inputs of a half adder, the sum is given by __________ a) A AND B b) A OR B c) A XOR B d) A EX-NOR B
Answer: c Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.
If A, B and C are the inputs of a full adder then the sum is given by __________ a) A AND B AND C b) A OR B AND C c) A XOR B XOR C d) A OR B OR C
Answer: c Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.
If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and __________ a) An underflow condition b) A neutral condition c) An overflow condition d) One indication
Answer: c Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and an overflow condition.
In a combinational circuit, the output at any time depends only on the _______ at that time. a) Voltage b) Intermediate values c) Input values d) Clock pulses
Answer: c Explanation: In a combinational circuit, the output at any time depends only on the input values at that time and not on past or intermediate values.
In a sequential circuit, the output at any time depends only on the input values at that time. a) Past output values b) Intermediate values c) Both past output and present input d) Present input values
Answer: c Explanation: In a sequential circuit, the output at any time depends on the present input values as well as past output values. It also depends on clock pulses depending on whether it's synchronous or asynchronous sequential circuits.
In serial addition, the addition is carried out __________ a) 3 bit per second b) Byte by byte c) Bit by bit d) All bits at the same time
Answer: c Explanation: In serial addition, the addition is carried out bit by bit.
What distinguishes the look-ahead-carry adder? a) It is slower than the ripple-carry adder b) It is easier to implement logically than a full adder c) It is faster than a ripple-carry adder d) It requires advance knowledge of the final answer
Answer: c Explanation: It is faster than ripple carry adder as it reduces the propagation delay by converting the ripple carry in such a way that the carry over a group of bits of the adder becomes 2-level logic.
Carry lookahead logic uses the concepts of ___________ a) Inverting the inputs b) Complementing the outputs c) Generating and propagating carries d) Ripple factor
Answer: c Explanation: Look Ahead Carry Adder is a type of digital circuit which reduces the propagation delay. Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this.
Looping on a K-map always results in the elimination of __________ a) Variables within the loop that appear only in their complemented form b) Variables that remain unchanged within the loop c) Variables within the loop that appear in both complemented and uncomplemented form d) Variables within the loop that appear only in their uncomplemented form
Answer: c Explanation: Looping on a K-map always results in the elimination of variables within the loop that appear in both complemented and uncomplemented form.
What does minuend and subtrahend denotes in a subtractor? a) Their corresponding bits of input b) Its outputs c) Its inputs d) Borrow bits
Answer: c Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called minuend and B as subtrahend.
A D flip-flop is used in a 4-bit serial adder, why? a) It is used to invert the input of the full adder b) It is used to store the output of the full adder c) It is used to store the carry output of the full adder d) It is used to store the sum output of the full adder
Answer: c Explanation: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be added to the next significant position of the numbers in the registers.
Why is the Gray code more practical to use when coding the position of a rotating shaft? a) All digits change between counts b) Two digits change between counts c) Only one digit changes between counts d) Alternate digit changes between counts
Answer: c Explanation: The Gray code is more practical to use when coding the position of a rotating shaft because only one digit changes between counts that is reflected to the next count.
Why XOR gate is called an inverter? a) Because of the same input b) Because of the same output c) It behaves like a NOT gate d) It behaves like a AND gate
Answer: c Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is true, the output is the inversion of the other. When one input is false, the output is the non-inversion of the other.
The enable input is also known as ___________ a) Select input b) Decoded input c) Strobe d) Sink
Answer: c Explanation: The enable input is also known as strobe which is used to cascade two or more multiplexer ICs to construct a multiplexer with a larger number of inputs. Enable input activates the multiplexer to operate.
What is one disadvantage of the ripple-carry adder? a) The interconnections are more complex b) More stages are required to a full adder c) It is slow due to propagation time d) All of the Mentioned
Answer: c Explanation: The main disadvantage in using this type of adders is that the time delay increases as for each adder to add the carry should be generated in the previous adder, and for that to add the carry from the one before is required. However, this disadvantage is taken care of in Carry Look Ahead adder in which the ripple carry is converted in such a way that the carry over a group of bits of the adder becomes 2-level logic.
Which is the major functioning responsibility of the multiplexing combinational circuit? a) Decoding the binary information b) Generation of all minterms in an output function with OR-gate c) Generation of selected path between multiple sources and a single destination d) Encoding of binary information
Answer: c Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.
The systematic reduction of logic circuits is accomplished by: a) Symbolic reduction b) TTL logic c) Using Boolean algebra d) Using a truth table
Answer: c Explanation: The systematic reduction of logic circuits is accomplished by using boolean algebra.
Which of the following statements accurately represents the two BEST methods of logic circuit simplification? a) Actual circuit trial and error evaluation and waveform analysis b) Karnaugh mapping and circuit waveform analysis c) Boolean algebra and Karnaugh mapping d) Boolean algebra and actual circuit trial and error evaluation
Answer: c Explanation: The two BEST methods of logic circuit simplification are Boolean algebra and Karnaugh mapping. Boolean Algebra uses the Laws of Boolean Algebra for minimization of Boolean expressions while Karnaugh Map is a pictorial representation and reduction of the Boolean expression.
How many NOT gates are required for the construction of a 4-to-1 multiplexer? a) 3 b) 4 c) 2 d) 5
Answer: c Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and x3 are the inputs and C1 and C0 are the select lines and M is the output. The diagram of a 4-to-1 multiplexer is shown below:
How many shift registers are used in a 4 bit serial adder? a) 4 b) 3 c) 2 d) 5
Answer: c Explanation: There are two shift registers are used in a 4-bit serial adder, which is used to store the numbers to be added serially. Serial addition takes place bit by bit.
Why do we use gray codes? a) To count the no of bits changes b) To rotate a shaft c) Error correction d) Error Detetction
Answer: c Explanation: Today, Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems.
When performing subtraction by addition in the 2's-complement system ____________ a) The minuend and the subtrahend are both changed to the 2's-complement b) The minuend is changed to 2's-complement and the subtrahend is left in its original form c) The minuend is left in its original form and the subtrahend is changed to its 2's-complement d) The minuend and subtrahend are both left in their original form
Answer: c Explanation: When performing subtraction by addition in the 2's-complement system, the minuend is left in its original form and the subtrahend is changed to its 2's-complement. It is then added to the minuend. If the result has carry, then it's dropped and that's the final answer. Else, if the result has no carry, then the result is again converted to it's 2's complement form and that's the final answer with a 'negative' sign.
When performing subtraction by addition in the 2's-complement system: a) The minuend and the subtrahend are both changed to the 2's-complement b) The minuend is changed to 2's-complement and the subtrahend is left in its original form c) The minuend is left in its original form and the subtrahend is changed to its 2's-complement d) The minuend and subtrahend are both left in their original form
Answer: c Explanation: When performing subtraction by addition in the 2's-complement system, the minuend is left in its original form and the subtrahend is changed to its 2's-complement. It is then added to the minuend. If the result has carry, then it's dropped and that's the final answer. Else, if the result has no carry, then the result is again converted to it's 2's complement form and that's the final answer with a 'negative' sign.
How many select lines would be required for an 8-line-to-1-line multiplexer? a) 2 b) 4 c) 8 d) 3
Answer: d Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is selected and fed to the output.
3 bits full adder contains ____________ a) 3 combinational inputs b) 4 combinational inputs c) 6 combinational inputs d) 8 combinational inputs
Answer: d Explanation: 3 bits full adder contains 23 = 8 combinational inputs.
Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder? a) To decrease the cost b) To make it smaller c) To slow down the circuit d) To speed up the circuit
Answer: d Explanation: A Carry Look Ahead (CLA) Adder is a type of adder that reduce the propagation delay. A fast Carry Look Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be implemented on any types of chip and have the capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit full-adder.
How many inputs are required for a 1-of-16 decoder? a) 2 b) 16 c) 8 d) 4
Answer: d Explanation: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2n outputs. Here, number of outputs = 16. 16 = 24 = 2n. Thus, number of inputs is 4.
Which error detection method uses one's complement arithmetic? a) Simple parity check b) Two-dimensional parity check c) CRC d) Checksum
Answer: d Explanation: A checksum is an error detection method used for the purpose of detecting errors that may have been incorporated during transmission. The checksum can be generated simply by adding bits. Hence, one's complement arithmetic uses checksum
A circuit that compares two numbers and determine their magnitude is called ____________ a) Height comparator b) Size comparator c) Comparator d) Magnitude comparator
Answer: d Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. A circuit that compares two numbers and determine their magnitude is called magnitude comparator.
The purpose of a Digital Comparator is ____________ a) To convert analog input into digital b) To create different outputs c) To add a set of different numbers d) To compare a set of variables or unknown numbers
Answer: d Explanation: A comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3, .... An, etc) against that of a constant or unknown value such as B (B1, B2, B3, .... Bn, etc) and produce an output condition or flag depending upon the result of the comparison.
One multiplexer can take the place of ___________ a) Several SSI logic gates b) Combinational logic circuits c) Several Ex-NOR gates d) Several SSI logic gates or combinational logic circuits
Answer: d Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. Since many operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex.
What can a relay provide between the triggering source and the output that semiconductor switching devices cannot? a) Total isolation b) Faster c) Higher current rating d) Total isolation and higher current rating
Answer: d Explanation: A relay provides total isolation and higher current rating between the triggering source and the output that semiconductor switching devices cannot provide. This is why relays are used to drive high watt appliances at offices or other buildings.
In parts of the processor, adders are used to calculate ____________ a) Addresses b) Table indices c) Increment and decrement operators d) All of the Mentioned
Answer: d Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.
Decimal digit in BCD can be represented by ____________ a) 1 input line b) 2 input lines c) 3 input lines d) 4 input lines
Answer: d Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.
Which of the following is correct for full adders? a) Full adders have the capability of directly adding decimal numbers b) Full adders are used to make half adders c) Full adders are limited to two inputs since there are only two binary digits d) In a parallel full adder, the first stage may be a half adder
Answer: d Explanation: By using maximum of two half adders we can make a full adder for the first stage of a Parallel Full adder.
3 bits full adder contains ________ a) 3 combinational inputs b) 4 combinational inputs c) 6 combinational inputs d) 8 combinational inputs
Answer: d Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM. Three bits full adder requires 23 = 8 combinational circuits.
What is the first thing you will need if you are going to use a macro-function? a) A complicated design project b) An experienced design engineer c) Good documentation d) Experience in HDL
Answer: d Explanation: HDL stands for Hardware Description Language. In order to use a macro function, one needs to have experience in HDL for representing the structure and behaviour of digital circuits.
If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____ result. a) Input, zero b) Output, one c) Input, one d) Output, zero
Answer: d Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero result.
Why is parallel data transmission preferred over serial data transmission for most applications? a) It is much slower b) It is cheaper c) More people use it d) It is much faster
Answer: d Explanation: Parallel data transmission preferred over serial data transmission for most applications because it is much faster as bits are transmitted simultaneously, whereas in serial data transmission, bits are transmitted one by one.
The main disadvantage of Manchester carry chain is ___________ a) Ripple factor b) Propagation delay c) Capacitive load d) Both propagation delay and capacitive load
Answer: d Explanation: Propagation delay is the measure of time taken by the output to go to the next state when the input is altered. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead.
All logic operations can be obtained by means of __________ a) AND and NAND operations b) OR and NOR operations c) OR and NOT operations d) NAND and NOR operations
Answer: d Explanation: Since the logic gates NOR and NAND are known as universal logic gates, therefore it can be used to design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be obtained by implementation of these gates.
Which of the following expressions is in the sum-of-products form? a) (A + B)(C + D) b) (A * B)(C * D) c) A* B *(CD) d) A * B + C * D
Answer: d Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied first and then it is added: A * B + C * D.
The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and ________ if a high order carry is generated. a) Addend, minuend b) Minuend, subtrahend c) Addend, minuend d) Augend, addend
Answer: d Explanation: The carry look ahead adder is based on the principle of looking at the lower order bits of the augend and addend if a high order carry is generated. A carry look ahead adder is a type of adder which reduces the propagation delay.
In most applications, transistor switches used in place of relays? a) They consume less power b) They are faster c) They are quieter and smaller d) All of the Mentioned
Answer: d Explanation: Transistors are of less consuming power, faster, quieter, smaller and its implementation is too easy. So, in most applications transistor switches are more preferred. And also, transistors can be current-controlled or voltage-controlled depending on our choice.
One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output's relation with the inputs? a) The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses b) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses c) The exclusive-OR output is a 15 s pulse followed by a 40 s pulse d) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
Answer: d Explanation: When both the input pulses are high or low X-OR output is low. But when one of the input is high and another is low or vice-versa, output is high. In this problem for the first 20uS one input is high and another is low. So, obviously output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15) first input is still high and second one is low so output is high.
