ELEN 333 Final

testbench contains statements to:

-apply inputs to the DUT - ideally to check that the correct outputs are produced - input and desired output patterns are called test vectors

synchronous sequential circuit and composition rules

-has a finite set of states -has a clock input who's rising edges indicate a sequence of times at which state transitions occur 1. every circuit element is either a register or a combinational circuit 2. at least one circuit element is a register 3. all registers receive same clock signal 4. every cyclic path contains one or more register

rules of bubble pushing

1. begin at output and work towards inputs 2. push an output bubble back, putting a bubble on all inputs 3. if there is an input and output bubble on same line, they cancel 4. bubble pushing switches AND gates to ORs and OR gates to ANDs

rules of finding implicants in K-map

1. must be all 1's 2. must use fewest, largest circles possible 3. each circle must span a rectangular block that is a power of 2 (1, 2, 4) 4. circles can wrap around 5. a 1 can be circled multiple times

carry propagate adder (CPA) common implementations? symbol

2 N-bit inputs, A and B, and a carry-in, Cin, to produce an N-bit result, S, and a carry-out Cout A, B, C, S are busses rather than bits common implementations: ripple-carry adders, carry-lookahead adders, and prefix adders

D flip-flop - draw schematic, symbol, and truth table

2 back to back D latches controlled by complementary clocks D flip-flop copies D to Q on rising edge of clock, and remembers its state at all other times

SR latch - draw the schematic, symbol, and truth table inputs and outputs?

2 cross-coupled NOR gates 2 inputs, S & R, and 2 outputs Q & Q' S sets (makes it true) and R resets (makes it false)

1-bit half adder symbol and truth table and equation

2 inputs, A and B, and 2 outputs S and Cout built from 1 XOR and 1 AND gate S = A XOR B Cout = A AND B

D latch - draw the schematic, symbol and truth table inputs and outputs?

2 inputs, D & CLK, and 2 outputs, Q and Q' data controls what next state is and clock input controls when state changes

bistable element examples?

2 stable states fundamental building block of memory cross-coupled inverters SR latch D latch D flip flop

1-bit full adder symbol and truth table and equation

3 inputs, A, B, Cin, and 2 outputs, S and Cout S = A XOR B XOR C Cout = AB + ACin + BCin

measuring delay

50% point of the input signal to the 50% point of the output

<= and :=

<= is a non-blocking assignment, evaluated concurrently, made to outputs and signals := is a blocking assignment evaluated in the order that appear in the code, made to variables (used in full adder, but p and g must be declared as variable and not signal)

mealy machine be able to sketch a mealy FSM

A state machine whose output is determined by both the current state of machine and current inputs

moore machine be able to sketch a moore FSM

A state machine whose output is determined only by the current state of the machine.

logic gates are built from:

CMOS transistors, which behave as electrically controlled switches

amount of information measured in bits

D = log(base 2)N bits

decoder

N inputs and 2^N outputs

NOT, AND, and OR gates

NOT inverts the value, AND returns 1 when both values are 1, OR returns 1 when either values are 1

dynamic power

P = 1/2CV^2f

static power

P = I * V

full adder equation

S = A XOR B XOR Cin Cout = AB + ACin + BCin

XOR, NAND, NOR, XNOR gates

XOR returns true for odd values(+ inside a circle), NAND inverts the values of AND, NOR inverts the values of OR, XNOR inverts the values of XOR

delay

a <= b and not c after 4 ns;

module

a block of hardware with inputs and outputs

illegal value x

a circuit node has an unknown or illegal value represented by x usually happens when a node is being pushed to high and low at the same time

astable circuit

a circuit with no stable states (ring oscillator)

bit swizzling

a collection of operations used to operate on a subset of a bus or to join together busses

schematic

a diagram of a digital circuit showing the elements and wires that connect them together

one hot encoding

a separate bit of state is used for each state only one bit is "hot" (true) at any time

ring oscillator

a sequential circuit with 0 inputs and 1 output that changes periodically period of ring osc. depends on propagation delay of inverter

Finite State Machine (FSM)

a synchronous sequential circuit with k registers that can be in one of a finite number of states be able to draw the diagram

enabled flip-flop draw symbols

adds the input EN to determine if data is loaded on the clock edge when EN is true, enabled flip flop behaves like an ordinary D flip flop when EN is false, enabled flip flop ignores clock and retains its state

testbench

an HDL module used to test another module - simulation source tested module is called device under test (DUT) or unit under test (UUT)

register know schematic and symbol

an N-bit register is a bank of N D flip-flops that share a common CLK input all bits of the register are updated at the same time

prime implicants

an implicant that cannot be combined with any other implicants to form a new implicant with fewer literals the implicants in a minimal equation must be all prime implicants

asynchronous vs. synchronous

async: no clock, occurring immediately, can use any voltage, can use any kind of feedback sync: easier design, all digital systems are sync.

why do we use gray code?

because it allows adjacent entries to only differ in one variable

case statements

begin process (input variable) begin case data is when X"0" => output <= "11111110"; ... end case; end process; end;

if statements

begin process (input variable) begin if input(3) = '1' then output <= "11111110"; elsif input(2) = '1' then output <= "11111011"; ...else output <= "0000000"; end if; end process; end;

how to use an output as an input in VHDL

buffer v : buffer STD_LOGIC;

ripple-carry adder (RCA)

chains together N full adders slow when N is large carry ripples through the carry chain

multiplexer

chooses an output from several inputs based on value of a select signal 2^N-1 mux size: N = number of inputs(a,b,c = 3)

race condition

circuit that fails when certain gates are slower than others when outputs are fed back to inputs the output of the circuit depends on the delays through certain gates

arithmetic/logical unit (ALU)

combines a variety of mathematical and logical operations into single unit performs addition, subtraction, magnitude comparison, AND/OR operations

complement, literal, true form

complement is the inverse of the variable literal is the variable or its complement true form is A, A' is complementary

CMOS

complementary metal-oxide semiconductor processes provide both types of transistors, and are used to build the majority of all transistors fabricated today

state variables

contains all information about the past necessary to explain future circuit behavior

critical path & short path

critical: the longest path; determines expected circuit duration short: shortest path with least gates

structural modeling

describes how module built from different pieces: application of hierarchy

functional specification

details next state and value of each output for each possible combination of current state and input values

comparator

determines whether 2 binary numbers are equal, or if one is greater or less than the other

digital compared to analog

digital: all values in the system represented by a series of digits analog: represents data by measurement of a continuous physical variable, as voltage or pressure

Carry lookahead adder

divides adder into blocks and provides circuitry to quickly determine carry-out of block as soon as carry-in is known it looks ahead across blocks rather than wait to ripple through all full adders inside block use generate (G) and propagate (P) signals that describe how block/column determines carry out

hierarchy

dividing a system into modules, then further subdividing each of these modules until the pieces are easy to understand

binary encoding

each state represented by a binary number

regularity

ensuring uniformity among modules so that common modules can be reused many times

prefix adder

extends the generate and propagate logic of CLA to perform addition even faster

powers of 2

find greatest 10th power, then find the constant with the remaining: 2^36 => 2^30 = billion 2^6 = 64

simplest synchronous sequential circuit

flip-flop also FSM and pipelines

modularity

giving modules well-defined functions and interfaces, so that they connect together easily without side effects

N-bit binary counter

has clock and reset inputs and an N-bit output, Q; reset initializes to 0

abstraction

hiding details when they are not important

don't cares

indicated by x in a truth table can be either 0 or 1 output value is unimportant allow for more logic minimization

floating value z

indicates the circuit node is being driven neither high nor low node is said to be floating, high impedance, or high z not the same as logic 0

how to break a cyclic path

inserting a register somewhere in the path

discipline

intentionally restricting your design choices so you can work more productively at a higher level of abstraction

fundamental building blocks of sequential circuits?

latches and FFs

a D latch is __________ a D FF is ____________

level-sensitive edge-triggered

3 parts of VHDL

library use clause - required: IEEE.STD_LOGIC_1154 entity declaration - lists the module name and its inputs and outputs architecture body - defines what the module does

an element with N stable states conveys _________ of information

log base 2 (N) bits

cyclic paths

loops in which outputs are fed directly back to inputs these are sequential circuits

resettable flip flop know schematic and symbols

made by D flip flop and AND gate adds RESET input when reset is false, resettable FF behaves like an ordinary FF when reset is true, resettable FF ignores clock and resets output to 0

minterm/maxterm

minterm is a product involving all inputs corresponding to a 1 output: ABC (SOP) maxterm is a sum involving all inputs corresponding to a zero output: A+B+C (POS)

behavioral modeling

models that describe what a module does

nMOS and pMOS

nMOS turn on when the gate is 1 pMOS turn on when the gate is 0

cross-coupled inverters

one input is the other's output no inputs - two outputs impractical because user has no inputs to control state

in D latch, when clk = 0, latch is ______ when clk = 1, latch is ______

opaque/closed transparent/open

sequential logic

output values depend on both current and prior input values its output cannot be determined simply by looking at it - has memory

calculating propagation and contamination

propagation: sum of prop. delay time x number of gates contamination: sum of cont. delay time x number of gates

static discipline

requires that, given logically valid inputs, every circuit element will produce logically valid outputs

rising/falling edge

rising - transition from low to high falling - transition from high to low

logic gates

simple digital circuits that take one or more binary inputs and produce a binary output

a test bench is ____________ but not ____________

simulatable but not synthesizeable

transparent

state of a latch in which data flows through to output as if it were just a buffer

opaque / transparent

state of a latch in which data is blocked from flowing through to output, so output retains its old value

metastable

state of the circuit if both outputs were between 0 and 1

in a State Transition Diagram circles represent __________ arcs represent __________

states transitions

FFs can be _____________ and _______________ resettable

synchronously - reset themselves only on rising edge of CLK asynchronously - reset themselves as soon as the RESET is true

delay of adder equation

t(ripple) = N * t(FA) t(FA) is the delay of a full adder

contamination delay

tcd, minimum time from when an input changes until any output starts to change value 60 ps

product/implicant

the AND of >=1 literals

noise margin

the amount of noise that could be added to a worst case output such that the signal can be a valid input / how much noise it can tolerate 1st gate is the driver and 2nd gate is the receiver NML = VIL - VOL NMH = VOH - VIH VOL<VIL VOH>VIH

simulation

to catch bugs / human mistakes

propagation delay

tpd, maximum time from when an input changes until the outputs reach their final value 100 ps

synthesis

transforms textual description of an HDL module into logic gates

a D latch is _____________ when CLK = ___.

transparent 1 allows input D to flow through to output Q

using a signal

use before begin in architecture signal p : STD_LOGIC;

glitches / hazards

when a single input transition causes multiple output transitions can avoid glitch by adding another gate, circle another overlapping implicant in k-map

unity gain points

where the slope of V(Y)/V(A) = -1