IT150 FINAL EXAM 2

spatial

A form of locality where accesses tend to cluster.

AC

A register that contains data read from the memory or data to be written in memory.

transistors

The 2nd generation of computer is known to use __________.

virtual memory

The page table is found at the ___________

victim block

The term used for an evicted block is __________.

pipelining

Parallel execution of smaller steps in CPU is called _________.

12 90 34

Show how the 129034₁₆ value would be stored by machines with 24-bit words using big endian format.

71 98 00

Show how the 9871₁₆ value would be stored by machines with 24-bit words using little endian format.

8K

Suppose a computer cache has 2¹³ words of main memory and a cache of 64 blocks, where each cache block contains 32 words using direct mapping scheme, how many blocks of main memory are there?

16K

Suppose a computer using set associative cache has 2¹⁶ words of main memory and a cache of 64 blocks, and each cache block contains 8 words. If this cache is 4-way set associative, how many blocks of main memory will there be?

4 bits

Suppose a computer using set associative cache has 2¹⁶ words of main memory and a cache of 64 blocks, and each cache block contains 8 words. If this cache is 4-way set associative, what is the size of the set field?

2048

Suppose that a 256M x 64 main memory is built using 512k × 16 RAM chips and memory is word-addressable. How many RAM chips are necessary?

5th bit

Suppose we are working with an error-correcting code that will allow all single-bit errors to be corrected for memory words of length 7. We have already calculated that we need 4 check bits, and the length of all code words will be 11. Code words are created according to the Hamming Algorithm presented in the text. We now receive the following code word: 1 0 1 0 1 0 1 1 1 1 0; Assuming even parity is there an error? If so, where is the error?

94.44%

A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Assume time for the cache is 30 ns and the time required to fill a cache slot from main memory is 313 ns. Compute the hit ratio for a program that loops 3 times from locations 100₁₀ to 123₁₀ in main memory.

9-2-3

A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.

distributed arbitration using collision detection

A bus arbitration in which each device is allowed to make a request for the bus, which is type used by Ethernet.

3.33ns

A bus operating at 300MHz has a cycle time of ____________.

8.01

A nonpipelined system takes 500ns to process a task. The same task can be processed in a 5-segment pipeline with a clock cycle of 60ns. Determine the speedup ratio of the pipeline for 100 tasks.

index

An addressing mode in which the effective address of the operand is generated by adding the value in the address field to that of the contents of a register.

paging

An approach in virtual memory in which the memory is divided into equal-sized pages

SKIPCOND

An instruction that uses bits in position 10 and 11 in the address field to determine what comparison to perform on AC.

2²⁴-1

Assume a 2²⁴ byte-addressable memory, how many address lines will it have?

data, control, address

Bus consist of ___ , _______ and ______ lines.

19-5

Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of 64K bytes of data and blocks of 32 bytes. Show the format of a 24 bit memory address for fully associative.

11 bits: 5 for chip select and 6 for address on the chip

Given a memory of 2048 bytes consisting of several 64 Byte x 8 RAM chips. Assuming byte-addressable memory, which of the following seven diagrams indicates the correct way to use the address bits?

45

How many bits are required to address 1G X 256K main memory assuming it is a byte-addressable memory

0

How many operand does the operation CLEAR requires?

equal

ISO comes from the greek word isos meaning __________

188

If the miss rate is 94% and the total number of CPU access to memory is 200, how many hits were made?

hit

In a simpler term, when the valid bit is 1, it is a _________.

page number and offset fields

In virtual memory, the field format of a virtual address contains

page fault

It occurs when a logical address requires that a page be brought in from disk

endianess

It refers to computer architecture's byte order

Moore's Law

It states that the numbers of transistors on a chip will double after every 18-24 months.

0

Let a = 1.0 × 2⁹, b = − 1.0 × 2⁹ and c = 1.0 × 2¹. Using the floating-point model described in the text (the representation uses a 14-bit format, 5 bits for the exponent with a bias of 16, a normalized mantissa of 8 bits, and a single sign bit for the number), perform the equation, paying close attention to the order of operations: (b + a) + c =

ABxCDxEFx++

The expression A x B + C x D + E x F has a postfix equivalent to __________

registers

The memory on top of the memory hierarchy is the __________

7 bits

The memory unit of a computer has 128K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 28 addressing modes; a register address field to specify one of 100 registers; and a memory address field. How large must the register field be?

0111 to 1000, or +7 to -8

Using a "word" of 4 bits, list all of the possible signed binary numbers and their decimal equivalents that are representable in Two's complement.

1010101100010

Using the CRC polynomial 10010, compute the CRC code word for the information word, 101010110

content addressable memory

_______ is another term used to describe cache memory

non-maskable

____________ interrupts are high-priority interrupts that cannot be ignored.