Post-Midterm/Final Quizzes
Which of the following best describes an exception?
A sudden change to the CPU control flow
All of the following are valid Y86 status codes:
AOK HLT ADR INS
Which property allows a two's complement adder to do subtraction as well with only minimal modification?
B - A = B + ~A + 1
What is NOT true of storage trends over the past three decades?
DRAM access times have improved by a factor of about 25
What technology is used for flash memory (e.g. SSDs)?
EEPROM
A register file with two read ports and one write port has ____ inputs and ____ outputs
Five inputs and two outputs
What effect does the following instruction have? addq %rcx, %rax
It adds the value in %rcx to the value in %rax and stores the result in %rax, sets the condition codes and increments the PC by 2
When does a clocked register's value change?
It depends on how the circuit is designed.
What is generally true of the body of a short machine code loop?
It exhibits both good spatial locality and good temporal locality
Which of the following is true of the HCL/boolean expression "(a && b) || (!a && !b)"?
It is true if and only if a == b
Which statement is true of the SEQ Y86 CPU hardware design described in section 4.3?
It never needs to read back any state updated by an instruction in order to finish processing that instruction.
What effect does the following instruction have? irmovq $256, %rsp
It sets RSP to 256 and increments the PC by 10
Which memory elements are typically shared by all cores on a CPU?
L3 cache and main memory
What is NOT an advantage of SSDs over traditional disk drives?
Less expensive per byte
What happens during the memory stage of a rmmovq instruction?
Memory is written at the location specified by the effective address.
Match the address translation symbol on the left with the appropriate description on the right. N: VPO: TLBI: PPO: CT: P:
N: number of addresses in virtual address space VPO: virtual page offset (bytes) TLBI: translation lookaside buffer index PPO: physical page offset (bytes) CT: cache tag P: page size (bytes)
What happens during the decode stage of a jmp instruction?
Nothing.
What does it mean if the SUP bit is set in a page table entry?
Only kernel-mode processes can access the page
What best describes thrashing?
Pages are continuously swapped in and out of main memory.
What is NOT a common type of device controller that communicates with the CPU and main memory via the I/O bus?
RAM controller
What input values should never be used for an S-R latch?
S and R set to 1 at the same time.
A cache can be defined by the following tuple (S, E, B, m). S: E: B: m:
S: the number of sets E: the number of lines per set B: the number of bytes per block m: the number of address bits for accessing the cache
following statements are true about the technologies that SRAM and DRAM use to store information:
SRAM relies on transistors and DRAM relies on capacitors.
What is NOT an advantage of using virtual memory to manage process address spaces?
Simplified memory access
Following is true about the memory hierarchy in a computing system:
Storage devices get cheaper, larger, and slower as we move from higher to lower levels
Which arithmetic instructions are included in Y86-64?
Subtraction Addition Bitwise AND
S-R latches and D flip-flops both store a bit. What kind of input is required by a D flip-flop that is not required in a S-R latch?
The D flip-flop requires a clock input.
What happens when the R bit is set to 1 (and the S bit is set to 0) in an S-R latch?
The output is set to 0
What happens when the S bit is set to 1 (and the R bit is set to 0) in an S-R latch.
The output is set to 1
The minimum time that the input to a memory device must be valid before the clock edge is called
The set up time.
What happens during the execute and write back stages of a pushq instruction?
The stack pointer is decremented.
What is the meaning of R[RSP]?
The value of %rsp
What is the meaning of M8[PC + 1]?
The value of eight bytes in memory at address PC + 1
What is the meaning of M1[PC]?
The value of one byte in memory at address PC
Match each virtual page descriptor to its meaning. Unallocated: Cached: Uncached:
Unallocated: Not yet created by the VM (Virtual Memory) system Cached: Allocated and currently residing in physical memory Uncached: Allocated but not currently residing in physical memory
Given a 32-bit virtual address space and a 24-bit physical address, determine the number of bits in each of the following assuming a page size of 2KB: VPN: VPO: PPN: PPO:
VPN: 21 VPO: 11 PPN: 13 PPO: 11
A nonlocal jump is
a jump that does not adhere to standard calling conventions
A cache memory is _______
a small, fast buffer for larger, slower memory.
An address space is
an ordered collection of non-negative integer addresses.
Which of the following instructions does NOT require an eight-byte immediate value or destination address?
andq
A disk's capacity is most closely dependent upon its
areal density
When a requested data object is not present in a cache, this is called a _______
cache miss
Which of the following Y86-64 instructions decrements the stack pointer?
call
When a working set cannot fit in a cache, the cache is experiencing a _________
capacity miss
Which of the following Y86-64 instructions does NOT modify the stack?
cmovle
Which component for a digital system computes functions on bits?
combinational logic
Consider the following y86-64 code: iterate: subq %rbx, %rcx jne end addq %rsi, %rbx jmp iterate end: halt Which, if any, dependencies exist in this code.
control and data dependency
Consider the following y86-64 code: irmovq $50, %rax addq %rax, %rbx mrmovq 100(%rbx), %rdx Which, if any, dependencies exist in this code.
data dependency
Which two stages of execution read from or write to the register file?
decode and write back
When a device writes to main memory without involving the CPU, it is called
direct memory access
During which stage of execution for a jle instruction does the CPU determine whether or not the branch should be taken?
execute
What is the central characteristic of the internal design of sequential circuits?
feedback
During which stage of execution does the CPU determine that an irmovq will use %rsi?
fetch
What is the correct order for the stages of executing a single Y86 instruction?
fetch, decode, execute, memory, write back, PC update
If a program accesses the same location many times in a short period of time, that program exhibits
good temporal locality
Which of the following instructions will set the processor status code to something other than AOK?
halt
Consider the following data as if it were an instruction memory: 0x020: 30 f5 20 00 00 00 00 00 00 00 What is the disassembled instruction that starts at 0x020? Note there may be more than one instruction, just consider the first one. What value will be in valE after this instruction completes the execute stage? What is the address of the PC after this instruction executes?
irmovq $32, %rbp 32 0x02a
The time required in a computing system to execute a single instruction (or particular sequence of instructions) is called its
latency.
Increasing cache block size:
makes programs with higher spatial locality run faster
Which metric measures the amount of time lost to a cache miss?
miss penalty
In Y86-64, which instruction moves a value from a memory location into a register?
mrmovq
Which combinational circuit component is used to select between one of several possible inputs?
multiplexor
If a program accesses (in rapid succession) many values that are at random locations in memory, that program exhibits
no locality
Consider the following data as if it were in instruction memory: 0x24: 10 90 00 00 What is the disassembled instruction that starts at 0x24? Note there may be more than one instruction, just consider the first one. What is the address in the PC after this instruction executes? What is the disassembled instruction that starts at 0x26? Note there may be more than one instruction, just consider the first one. What is the address in the PC after this instruction executes?
nop 0x025 ret (maybe) 0x027 (3/4)
Match the following cache class with the appropriate description: direct-mapped cache four-way set associative cache fully associative cache two-way set associative cache
one line per set four lines per set all cache lines map to the same set two lines per set
In the context of virtual memory, a DRAM cache miss is called a
page fault
A page table is an array of
page table entries
A disk controller maintains associations between logical blocks and
physical sectors
Consider the following data as if it were in instruction memory: 0x22: b0 1f 00 00 What is the disassembled instruction that starts at 0x22? Note there may be more than one instruction, just consider the first one. What is the address in the PC after this instruction executes?
popq %rcx 0x24
Suppose a Y86-64 machine code instruction is two bytes long and its hex encoding is 20 45. What is the corresponding assembly code?
rrmovq %rsp %rbp
The time that it takes for a disk arm to position itself over the correct track in order to read data is called the
seek time
Fully associative caches ________ work better on a program than a direct-mapped cache.
sometimes
In a CPU, the frequency is the inverse of
the clock cycle time
The minimum time during which the input must be valid after the clock edge is called
the hold time
In a D flip-flop, "D" corresponds to
the input to the flip-flop
The number of instructions that can be executed per unit of time in a computer system is called the
throughput
Address translation can be accelerated using
translation lookaside buffers
A conflict in a caching system is when:
two lines currently in use in a program map to the same set in a direct-mapped cache two lines currently in use in a program map to the same line in the cache
For a ret instruction, which internal field of the Y86 processor is used to update the PC?
valM
Virtual memory requires address translation, which converts
virtual addresses to physical addresses.
A "stride-1 reference pattern" describes memory accesses that
visit every element of an array in order
The valid bit in a cache indicates:
whether or not the line has meaningful information
Which cache write policy will delay as long as possible before propagating updates to lower levels of the memory hierarchy?
write-back
What is the output of the following circuit for the given inputs (more than one is possible)? x x1-------------|\ y x1-(NOT)--[AND]-(NOT)-x1 x x1-(NOT)-----|/ https://w3.cs.jmu.edu/lam2mo/cs261_2019_08/images/quiz4_2_circ.png
x=0, y=1, z=1; f(x,y,z) = 1 x=1, y=0, z=0; f(x,y,z) = 0 x=1, y=1, z=0; f(x,y,z) = 1
Which of the following is true of the following logic gate? x0 []--|\ (AND)--z x1 []--|/ https://w3.cs.jmu.edu/lam2mo/cs261_2018_08/files/and_gate.png
z is true if and only if both x1 and x0 are true.
Which of the following is true of the following logic gate? x0 []--|\ (OR)--z x1 []--|/ https://w3.cs.jmu.edu/lam2mo/cs261_2018_08/files/or_gate.png
z is true if either x1 or x0 are true.
What is the HCL/boolean formula for the following circuit? Note that the small circles ("bubbles") mean NOT even though the full gate (with the triangle buffer) is not drawn. a --(NOT)-----|\ b ----------[AND]-(OR)-x1 c --(NOT)-----|/ [branch before the (NOT)]: a -(NOT)----|\ b -(NOT)-[AND]-(OR)-x1 c -(NOT)----|/ **connects to same (OR) after [AND]** https://w3.cs.jmu.edu/lam2mo/cs261_2016_08/images/circuit01.png
(!a && b && !c) || (!a && !b && !c)
What is the HCL/boolean expression for "a XOR b"?
(a && !b) || (!a && b)
Which of the following circuits are equivalent (more than one answer is possible)?
(a && (b || c)) and (a && b || a && c) !(x && y) and (!x || !y)
Implementing a write to a register file requires:
- A clock signal to trigger the action - A decoder to determine the register number - The input data to the register
Which are true of a pipelined system?
- A pipelined system can increase throughput - Ideal pipelining requires uniform partitioning
What is true of combinational circuits?
- Circuits may not contain loops - Circuits may not contain gates - A gate may have more than two inputs - Gate inputs must be connected to a primary input, a memory output, or the output of another gate - The output of a gate may be connected to inputs for multiple gates.
Which of the following options are considered a characteristic of a RISC (Reducted Instruction Set Computer)?
- No instructions with a long execution time. - Fixed-length encodings - Implementations artifacts exposed to machine-level programs.
Implementing a read from a register file requires:
- The output data from the register - A multiplexor to select the output of the register to read
All of the following are differences between Y86-64 and x86-64:
- Y86-64 has fewer data types - Y86-64 has only 3 condition codes - x86-64 uses %r15 as a general purpose register - x86-64 has the scaled index addressing mode
Consider the instruction "rmmovq %rax, 4(%rsp)". If %rax is 2 and %rsp is 0xee0, what is the value of valE after the execute stage?
0xee4
What is the output value of the circuit ((x || !x) || (y && !y))?
1
Assume that X = 5 and Y = 7. For the ALU described in section 4.2 (see figure 4.15), what would be the output if the operation control signal is set to 0? 0 -> X+Y
12
What is the little endian hex encoding of the following Y86-64 assembly instruction "rmmovq %rdi, 0x1234(%rbp)"?
40753412000000000000
Assume that X = 5 and Y = 7. For the ALU described in section 4.2 (see figure 4.15), what would be the output if the operation control signal is set to 2? 2 -> X&Y
5
