1.4 Muxes and Decoders

Implementing a truth table

1. Analyze outputs (specifically 0s or specifically 1s) 2. draw diagram of values and inverted values of inputd

4 to 1 mux

4 inputs and two inverted selects connected to 4 AND gates For each AND gate, it's connected to the input and the values of all selects, inverted or normal (00,01,10,11) Each AND output is fed into a 4-input OR gate

Sequential logic circuits

Has concept of "state", where we store information, and that state impacts the output

Structure of a mux

Internally organized as b n-to-1 mux circuits Only outputs one data input at a time (all other individual AND gate outputs are 0)

Combinational logic circuits

Outputs depend on the present value of the inputs No sense of history, only the current

2 to 4 decoder

Two inputs with four AND gates, with all patterns of inverters A, B = 00 -> Out0 is 1 A, B = 01 -> Out1 is 1 A, B = 10 -> Out2 is 1 A,B = 11 -> Out 3 is 1

CMOS combinational logic

Use NOT, NAND, and NOR instead of AND and OR

Using multiple muxes

Use b muxes for b bits Same select input for all

Decoder

Useful fro recognizing a particular bit pattern of 1s and 0s Widely useful in memory

Multiplexer

a.k.a. Mux, selector Takes a number of different inputs and selects one for the output, using a bit called a select

Muxes' selects

n inputs -> ceiling of log(base 2)n select inputs (rounds up to nearest integer) Select chooses the specific data input (based on number: if s = 0, then it'll choose data input 0) Data inputs are numbered in increasing fashion from the bottom of the mux to the top

Decoder inputs and outputs

n inputs, 2^n outputs Only one output is 1 at a time (all others are 0) Each input pattern produces a unique output