CEA Chapter 1, CEA Chapter 2, CEA Chapter 3

Réussis tes devoirs et examens dès maintenant avec Quizwiz!

system interconnection

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. a. system interconnection b. CPU interconnection c. peripheral d. processor

protocol

A __________ is the high-level set of rules for exchanging packets of data between devices. a. bus b. protocol c. packet d. QPI

hierarchical

A __________ system is a set of interrelated subsystems. a. secondary b. hierarchical c. complex d. functional

system bus

A bus that connects major computer components (processor, memory, I/O) is called a __________. a. system bus b. address bus c. data bus d. control bus

system bus

A common example of system interconnection is by means of a __________. a. register b. system bus c. data transport d. control device

False

A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS). a. True b. False

True

A computer must be able to process, store, move, and control data. a. True b. False

False

A key characteristic of a bus is that it is not a shared transmission medium. a. True b. False

True

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet. a. True b. False

False

A microcomputer architecture and organization relationship is not very close. a. True b. False

True

A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology. a. True b. False

software

A sequence of codes or instructions is called __________. a. software b. memory c. an interconnect d. a register

False

A vacuum tube is a solid-state device made from silicon. a. True b. False

True

A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points. a. True b. False

hardware failure interrupt

A(n) _________ is generated by a failure such as power failure or memory parity error. a. I/O interrupt b. hardware failure interrupt c. timer interrupt d. program interrupt

program interrupt

A(n) _________ is generated by some condition that occurs as a result of an instruction execution. a. timer interrupt b. I/O interrupt c. program interrupt d. hardware failure interrupt

all of the above

ARM processors are designed to meet the needs of _________. a. embedded real-time systems b. application platforms c. secure applications d. all of the above

peripheral

An I/O device is referred to as a __________. a. CPU b. control device c. peripheral d. register

False

An I/O module cannot exchange data directly with the processor. a. True b. False

I/O mechanisms

Architectural attributes include __________ . a. I/O mechanisms b. control signals c. interfaces d. memory technology used

True

At a top level, a computer consists of CPU, memory, and I/O components. a. True b. False

True

Backward compatible means that the programs written for the older machines can be executed on the new machine. a. True b. False

True

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. a. True b. False

True

Both the structure and functioning of a computer are, in essence, simple. a. True b. False

False

Changes in computer technology are finally slowing down. a. True b. False

True

Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures. a. True b. False

architecture

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. a. organization b. specifics c. design d. architecture

False

Computer organization refers to attributes of a system visible to the programmer. a. True b. False

True

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. a. True b. False

rapid

Computer technology is changing at a __________ pace. a. slow b. slow to medium c. rapid d. non-existent

True

Computers are classified into generations based on the fundamental hardware technology employed. a. True b. False

True

Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components. a. True b. False

fetch cycle

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. a. execute cycle b. fetch cycle c. instruction cycle d. clock cycle

lane

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time. a. lane b. path c. line d. bus

False

Historically the distinction between architecture and organization has not been an important one. a. True b. False

True

IBM's System/360 was the industry's first planned family of computers. a. True b. False

True

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. a. True b. False

True

Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip. a. True b. False

True

Interfaces between the computer and peripherals is an example of an organizational attribute. a. True b. False

False

Interrupts do not improve processing efficiency. a. True b. False

architectural

It is a(n) _________ design issue whether a computer will have a multiply instruction. a. architectural b. memory c. elementary d. organizational

organizational

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. a. architectural b. memory c. mechanical d. organizational

False

It is not possible to connect I/O controllers directly onto the system bus. a. True b. False

True

John Mauchly and John Eckert designed the ENIAC. a. True b. False

clock tick

One increment, or pulse, of the system clock is referred to as a _________. a. clock tick b. cycle time c. clock rate d. cycle speed

True

Program execution consists of repeating the process of instruction fetch and instruction execution. a. True b. False

Transistors

Second generation computers used __________. a. integrated circuits b. Transistors c. vacuum tubes d. large-scale integration

False

System software was introduced in the third generation of computers. a. True b. False

first

The ENIAC is an example of a _________ generation computer. a. first b. second c. third d. fourth

vacuum tubes

The ENIAC used __________. a. vacuum tubes b. integrated circuits c. IAS

World War II

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________. a. the Civil War b. the French-American War c. World War I d. World War II

True

The IAS is the prototype of all subsequent general-purpose computers. a. True b. False

True

The IAS operates by repetitively performing an instruction cycle. a. True b. False

False

The Intel x86 evolved from RISC design principles and is used in embedded systems. a. True b. False

routing

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. a. link b. protocol c. routing d. physical

all of the above

The TL supports which of the following address spaces? a. memory b. I/O c. message d. all of the above

transaction layer

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. a. transaction layer b. root layer c. configuration layer d. transport layer

main memory

The _________ stores data. a. system bus b. I/O c. main memory d. control unit

ENIAC

The _________ was the world's first general-purpose electronic digital computer. a. UNIVAC b. MARK IV c. ENIAC d. Hollerith's Counting Machine

address lines

The __________ are used to designate the source or destination of the data on the data bus. a. system lines b. data lines c. control lines d. address lines

instruction register

The __________ contains the 8-bit opcode instruction being executed. a. memory buffer register b. instruction buffer register c. instruction register d. memory address register

integrated circuit

The __________ defines the third generation of computers. a. integrated circuit b. vacuum tube c. transistor d. VLSI

control unit

The __________ interprets the instructions in memory and causes them to be executed. a. main memory b. control unit c. I/O d. arithmetic and logic unit

speed metric

The __________ measures the ability of a computer to complete a single task. a. clock speed b. speed metric c. execute cycle d. cycle time

I/O

The __________ moves data between the computer and its external environment. a. data transport b. I/O c. register d. CPU interconnection

ALU

The __________ performs the computer's data processing functions. a. Register b. CPU interconnection c. ALU d. system bus

True

The basic function of a computer is to execute programs. a. True b. False

data bus

The data lines provide a path for moving data among system modules and are collectively called the _________. a. control bus b. address bus c. data bus d. system bus

True

The hierarchical nature of complex systems is essential to both their design and their description. a. True b. False

all of the above

The interconnection structure must support which transfer? a. memory to processor b. processor to memory c. I/O to or from memory d. all of the above

False

The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables. a. True b. False

words

The memory of the IAS consists of 1000 storage locations called __________. a. opcodes b. wafers c. VLSIs d. words

True

The method of using the same lines for multiple purposes is known as time multiplexing. a. True b. False

True

The number of bits used to represent various data types is an example of an architectural attribute. a. True b. False

instruction

The processing required for a single instruction is called a(n) __________ cycle. a. execute b. fetch c. instruction d. packet

True

The textbook for this course is about the structure and function of computers. a. True b. False

False

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit. a. True b. False

multicore

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. a. multicore b. GPU c. data channels d. MPC

False

The variety of computer products is exhibited only in cost. a. True b. False

all of the above

The von Neumann architecture is based on which concept? a. data and instructions are stored in a single read-write memory b. the contents of this memory are addressable by location c. execution occurs in a sequential fashion d. all of the above

False

The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University. a. True b. False

True

There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer". a. True b. False

True

Timing refers to the way in which events are coordinated on the bus. a. True b. False

John von Neumann

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. a. John Maulchy b. John von Neumann c. Herman Hollerith d. John Eckert

data communications

When data are moved over longer distances, to or from a remote device, the process is known as __________. a. data communications b. registering c. structuring d. data transport

False

When data are moved over longer distances, to or from a remote device, the process is known as data transport. a. True b. False

False

With asynchronous timing the occurrence of events on the bus is determined by a clock. a. True b. False

Pentium

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel. a. Core b. 8080 c. 80486 d. Pentium

Organizational

_________ attributes include hardware details transparent to the programmer. a. Interface b. Organizational c. Memory d. Architectural

Registers

_________ provide storage internal to the CPU. a. Control units b. ALUs c. Main memory d. Registers


Ensembles d'études connexes

LENB 3135 Chapter 19 Study Questions

View Set

Perry- Chapter 48: Musculoskeletal or Articular Dysfunction

View Set

unit 8 The media phrasal verbs exercises

View Set