Chapter 6

Intel x86 indirect addressing modes

- Based relative and index relative addressing Like indirect (operand in memory), except a fixed offset is added to address in register to yield effective address - based indexed addressing Like indexed, except address values from two registers plus a fixed offset are added to yield effective address

Ways to reduce pipeline issues

- Improve compiler techniques to reduce impact of branches and resource conflicts - branch prediction: cpu guesses the instruction flow probabilistically - implicit or explicit parallelism

How do Instruction sets affect computer architecture?

3 - flexible but need more bits for instructions 2- faster but not as exact 1 - some contents may be implied 0 - use Entries from stack and push back

How many general purpose registers does c86 family have?

4: AX, BX, CX, DC 16 bit registers. Can access a chunk (byte) (modern is 32 to 64 bit word)(AH high byte, AL is low byte)

How many address registers for x86 family

4: BP (base pointer), DI (destination index), SI (Source Index), SP (stack pointer) (BP,DI,SI support general kinds of addressing modes)(SP used to access stack)

How many segment registers in x86 family?

4: CS code segment, DS data segment, ES extra (data) segment, SS stack segment Registers point to segment in memory for code, data, and stack

Source file is

Assembly code (input to assembler)

ISA and three views

view of processors functional resources and capabilities (not hardware) - intel x86 (prototypical CISC), variable length (bytes) and execution types (complex control and decoding). Philosophy - bring ISA closer to high level instructions and reduce assembly language instructions. Less instructions means less fetching - MIPS architecture - Java Virtual Machine (software ISA)

Stack

Abstract data type serves as collection of elements with two principal operations (push and pop)

Transfer control instructions

Alters the instruction execution sequence (jump) -jump or call a subroutine in a way that allows a return -save return address on stack -jump 8 bytes ahead -jump if loop -Return: back to original instruction routine

Pipeline instruction execution is like

An assembly line (production is increased by stating next instruction after that step is done) DONT need additional hardware, just unique hardware K- pipelining ideally has an instruction being completed every cycle where k is the number of total instructions (reality: Branches, halts, interrupts slow it down)

Basic data path and control 8086

Bus interface unit (BIU) - segments registers and instruction pointer on BIU because used to generate actual addresses going out to memory Execution Unit (EU) - stack pointer and general purpose registers are on EU bc they are associated with arithmetic and data operations. Compiler sets up registers and high level language would set up variables. Compiler generates instructions for processor to perform as one or various machine code instruction

CISC vs RISC for computer architect

CISC - how do we realize complex programs with less more complex powerful instructions (reduces memory - can be expensive as processors gainsmore functionality). Tied closet to high level languages RISC - reset on evolution of tech. Look at operations that are heavily executed to focus on instructions to do simply and quickly (GPU). Less control hardware (logic), higher clock rates used, lower execution times (cache used). Mapping more clever in ISA. More real estate (more silicon/transistors, which means more registers and more data, less pulling data from memory)

Basic steps to execute an instruction (Non-Pipelined)

CPU performs each step with a clock to sequence steps: - fetch, - decode - determine operation from opcode - Calculate operand address (determine addresses for operands based on addressing modes and values - fetch operands from memory or cache - execute - store result

Different instruction types

Data movement - move without altering (move,exchange, load) Arithmetic - add or increment (how is data represented?: fixed integer vs floating point, number of bits, compliment system, carry out, overflow (corrupted sign bit)) Boolean logic - perform bitwise operations Bit manipulation - manipulate individual bits or full register set (logical - shift 0, arithmetic - multiply or divide by 2 left or right, rotate - wraps bit around) Input/output - transfer data from register to output or transfer from input to register; control I/O, Interrupts Transfer control (jump) Special purpose (something unique in processor)

Instruction formats

Different ISAs supports different instruction formats due to: - hardware philosophies, what tasks to be completed - hardware and performance trad offs (silicon types , marketing competitive reasons - support for instruction set compatibility (x86 family long lived BC you don't want people to start over and have to rewrite or compile everything

Input/Output instructions addressing

Direct mapped uses dedicated I/O piers to specify IO locations (x86 allows scheme). Special address spaces for processor and registers Memory mapped I/O puts IO interface into normal memory address space (like writing or reading from memory) make cpu think port is normal register (address is only unique thing

Superpipelining

Divide instruction execution into larger number of stages (lots of step to execute one instruction - fine grained). Higher probability of resource contention and higher penalty of branch

How do general purpose registers access main memory?

Extra clock cycles and external access (more signaling to memory bus)

MIPS ISA overview

Fixed length instructions Execution is fixed for given type of instruction Relatively simple functionality for each instruction (unlike x86 CISC long instruction) Means more storage for instruction needed, but control structure is simpler, so MIpS can use control logic for other things (more registers, cache) Load store architecture- most instructions just reference registers (not in memory) (load and store are special instructions that move data) 32 general purpose registers - means you can a lot of data operands in registers and not in memory Summary: Easy to decode and has lots of registers

Three sets of x86 registers

General purpose (mostly data) Address registers Special purpose registers (flags, instruction point) - flag registers hold condition codes from ALU (sign flag), exception bits (overflow flag), and other misc functions -16 bit instruction pointer registers - points to next instruction within current code code segment

Orthogonality

Generally different instructions types have different rules for operands. With Orthogonality you can use same addressing modes and operands types for all operations (move R same as Add R). Same operands would be AVAILABLE for different instruction type. Lack of Orthogonality would be utilized for efficiency in ISA. Efficient (Lacks redundancy) and flexible (uniformity in addressing modes available)

How do you minimize contention in superscalar architecture?

Get a good compiler

What design factors driving ISA?

How much storage? (Embedded?) - number of bits per instruction, number of instructions to represent program How much processing is required (how much hardware and time) to execute instructions? (RISC vs CISC) How effectively can compilers utilize the ISA?

Super scalar architecture

ILP; provide parallel execution of different instructions, so multiple instructions can be executed at same time. Processor improve ordering to increase utilization of multiple pipelines. Used in modern pc's. (Duo core processors use program level parallelism)

Immediate vs direct load example

Immediate loads directly from operand of instruction Direct loads from value of memory location Syntax can tell us which addressing mode we are using (#)

Where are operands stored?

In CPU, stack, accumulator Register, general purpose registers

Direct addressing mode

Instruction contains address of operand rather than value (Load location 800 to register r1)

Immediate Addressing Mode

Instruction contains the operand value - operand value must be known adding -4 to R4 immediately

Two types of parralelism

Instruction level - multiple instructions executed at same time. Same stage is active for two or more instructions Program level - two or more programs are executed in parallel (work together) ILP left for compiler (requires some level of programmer specification) ILP and PLP can be used separately

Register addressing mode

Instruction refers Register and the register contains value. Add #5 to R1 (contents of register 1)

Register Indirect addressing mode

Instruction specified register and that register contains memory address of operand. Same dynamic movement as fist indirect addressing mode. Unlike memory indirection, requires just one access to memory

Based or Indexed Addressing

Instruction specifies operand and register. Take contents of register and add to that sum operand and register contents specify memory address of Operand

IETF

Internet Engineering Task Force, which focuses on the Net's evolution and operation. Set standards for internet

Protected Mode

Introduced to the x86 family to protect areas of processor from malicious code: Flat memory model (no segments) Privileged instructions and protection (offer protections to memory blocks) (only activated when executed in processor)(bright back to OS has privileges reinstated)

Java bytecodes

Java bytecodes seen in mnemonic or binary form All byte codes are ONE byte in length - some instructions require additional following bytecodes for immediate data Stack based (0-operand implied) instructions - no explicit operands specified as part of instructions (stack oriented processor) a push and pop off stack to perform (push means element moves from variable to stack, pop means push element off stack to variable)

Java programming cycle*****

Java compile-time environmental Java source (java file - high level program) Java compiler generates Java bytecode (class file like assembly language - can mnemonic or binary (look at line assembly or look at like machine code) Java runtime environment Merge bytecode file combine with other bytecode files to realize API (graphical functions, IO ops, networking ops) Bring all together in class loader Execution engine

J type MIPS

Just for jumps 26 bit target of Jump

On chip features for protected address mode

Large flat address space (64 terabytes) Memory management Multitasking (multiple programs can run at same, OS swaps them out) Protection - application level code cannot go in effect memory of other applications or of Os

Two approaches to how bytes are stored by pointing to MSB or LSB

Little endian - LSB (base address +0) (x86 architecture) Big endian - MSB (base address +0) (Motorola, MIPS support both, network byte order in the internet) Example: store 12345678 at location 500: 500 = 78... 503 = 12 or 500 = 12...503 = 78

Instruction length tradeoffs in ISA

Long instructions means more bits to encode more ops and operands and larger possible number But simpler instructions may mean more bits (smaller) since instructions are more and smaller. Traded off in program storage and program execution. Differentiated base on: instruction length, number and locations of operands, how memory accessed

Example of move instructions

MOV CL, AH (Move AH to CL - 8 bits) MOV CL, 30H (move immediate data 30H to CL - 8 bits) MOV CX, AX (move ax to CX - 16 bits) MOV CX, 0F34H (move immediate data 0F34H to CX - 16 bits)

Object file is

Machine code (output)

Approaches to accessing memory

Memory to memory - allow bring in operands form memory process then write back to memory (flexible but high delay to access to external memory) Register memory - at least one operand that is general purpose register (read to or write from) and mix in memory Load store architecture - RISC do operations only between registers (Register to register) move something from memory and use data in register over course of multiple instructions rather than putting it back right away (all instructions except for load and store are not slowed down)

Instructions can be represented as

Mnemonics (assembly language instructions) Binary codes (machine instructions)

Motivation for addressing modes

Modes used to references memory locations and operands jn different ways 1. Efficiency and clarity in coding at Assembly level (less instructions) 2. Efficiency at machine language level - faster times

What differentiates instruction sets?

Number of bits or variables per instruction Number of operands allowed per instructions References to operands and sources - register to memory, register to register (stack, AC, general registers) Operands May be of different lengths

Indexed Addressing

Operand specifies block of memory and register is incremented to index into block (long op and short register)

Instructions have

Operation to be performed (opcode) Operands - used as inputs and outputs for operation to be performed (values added or sent to location)

What if a value is first stored as little endian and then read as Big?

Processor with big endian ISA will the number will be backwards. Solution: converter - hton and then ntoh

Three instruction formats (MIPS)

R (register) I (Immediate) J (Jump) All instructions are 32 bits long Have 6 but opcode with 26 bits depending on type

Indirect addressing mode

Refer to address of the address of a pointer in memory that refers to operand. Uncommon BC it requires two acccess points for memory which is slower. Can change value of bits to another location. Pointer address has to be known, but the operand can be changed at any time before execution (dynamically update)

I type instructions set MIPS

Reference two (1 destination, 1 source) registers and an immediate operand (16 bit data) Functions: arithmetic, logic ops, conditional jumps (w immediate data (16 bits) indicating branch offset)

Intel x86 addressing modes

Register addressing - operand in Register, instruction specifies Register Immediate addressing - instruction contains operand data Direct addressing - operand is in memory, instruction specifies memory location, (if operand inside data segment just considered 16 bit offset), if refernce outside current segment, instruction needs to be longer (specify register value and offset - 32 bit address) Register indirect - operand in data memory, address of operand is contained in register, instruction specifies register that contains operand address

Based Addressing

Register specifies block of memory (base) and operand provides offset in base (long register m, short operand)

Real Mode

Segmented memory module: Code segment Data segments stack segment Extra segment No Supervisory mode - any code can access any part of memory (not protected from malicious code or back coding)

R type instruction set MIPS

Three operand instrcution set (2 source and 1 destination 5 but registers) Function: arithmetic and logical ops Shift amount - applied to shift operation Function operator (like sub opcode - this is an Rtype instruction)

Special purpose instructions

Tied to specifics of processors, memory systems, or control structure - set addressing base register to hexadecimal 7F00000

VLIW architecture

Very long instruction word architecture - one instruction executed at a time. But a lot is going (registers be added, these registers are being moved). Burden is on the compiler to maximize use of resources

JVM overview

Virtual (realized in software which executes in some other processor and operating system (Instead of running on a chip we run on top of OS) - implements an ISA in software (runs on another processor with different ISA) - Java source code compiled into java bytecode and then executed on JVM - provides common platform for development (don't have worry about different instruction sets and operating system environments) - protected environment - protecting host system from java program - protected environment for java program