Computer organisation and architecture

What are subroutines and why are they used?

Subroutines are useful for frequently used sections of a program Write (and debug) a subroutine once, and use that program code whenever it is needed Reduces program size Improves readability

What is cache?

"90% of memory accesses within only 2 Kbytes" So store those 2 Kbytes in a small, fast "cache" memory If data required by CPU is in the cache (a "cache hit"), big speed improvement Cache is small to limit cost Note that "cache" means "hiding place" - transparent to programmer

What is moore's law?

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years." - Gordon Moore (co-founder of Intel), Electronics, Volume 38, No. 8, April 1965 Now more commonly expressed as "The number of transistors on a memory chip doubles every 18 months"

What does the operation of a DMA look like?

1. DMA transfer requested by I/O 2. DMAC passes request to CPU 3. CPU initialises DMAC i) Input or Output, ii) Start address → DMAC Address Reg, iii) Number of words to transfer → Count Reg, iv) CPU enables DMAC 4. DMAC requests use of system buses 5. CPU responds with DMA Ack when it's ready to surrender buses

What are the five categories of instructions that make up the 68008 instruction set?

1. Data Movement 2. Arithmetic 3. Logical 4. Branch 5. System Control

What are the different addressing modes in 68008?

1. Data or Address Register Direct 2. Immediate Addressing 3. Absolute Addressing 4. Address Register Indirect - five variations 5. Relative Addressing

What is the interrupt handling sequence?

1. External device signals interrupt INTERRUPT RESPONSE 1. CPU completes current instruction 2. Push PC onto Stack 3. Push Status Register(s) onto Stack 4. Load PC with address of Interrupt Handler RETURN FROM INTERRUPT 1. Pop PC from Stack 2. Pop Status Register(s) from Stack 3. Load PC with popped return address Context switch Cont

Explain the status register:

16 bit - Consists of two 8-bit registers Various status bits that are set or reset upon certain conditions arising in the arithmetic and logic unit (ALU)

How many bits can an octal symbol represent?

3

How many bits can a hex symbol represent?

4

Explain the program counter:

A 32-bit register that keeps track of the address at which the next instruction will be found In simple terms, it points to the next instruction in memory When the current instruction has been read, the PC is incremented to point to the next instruction.

What is a flip-flop circuit?

A circuit whose outputs are fed back to inputs

What is a combinatorial logic circuit?

A logic circuit whose output is a logical function of its input

What is a sequential logic circuit?

A logic circuit whose outputs are logical functions of its inputs and its current state / memory

What is a word?

A word is a fixed-sized piece of data handled as a SINGLE unit by the instruction set or the hardware of the processor. The number of bits in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture.

Explain the address registers in the 68008

A0 - A6 Used as POINTER REGISTERS in the calculation of operand addresses A7 - Additionally used by the processor as a system stack pointer to hold subroutine return addresses etc... Operations on addresses do not alter status register Condition Code Register (CCR) ALU has capacity to incur changes in status

Explain the stack pointer:

A7 - The stack pointer is used as a pointer into an area of memory called the system stack. Points to the next free location The stack is a Last In First Out (LIFO) structure The stack provides temporary storage of essential processor state, e.g., return addresses and registers, during subroutine calls and interrupts You will meet this use of the stack again in many different contexts A0-A6 may also used by programmer as stack pointers for temporary storage of registers, e.g., arithmetic calculations

What are the seven logic gates?

AND, OR, EX-OR, NOT, NAND, NOR and EX-NOR

What are the advantages of interrupts?

Advantages Fast response No wasted CPU time / battery power

What is a de-multiplexer?

Allow an input to appear on any one of the outputs (note that this is the reverse of a multiplexer

What is the role of the ALU?

Arithmetic Logic Unit (ALU) - Performs mathematical and logical operations. Also ALU has capacity to incur changes in status code register

How does error detection using parity work?

At our transmitter a message, e.g., 7 bits, is encoded Compute parity (P) and append parity to message Send modified message across channel At our receiver the message, now 8-bits including parity, is decoded Compute parity (Q) from data bits of received message Compare computed parity Q with received parity P in message and flag ERROR if these are not consistent

Comparison of SRAM against DRAM:

Both are volatile - power must be continuously applied Dynamic memory cells are generally simpler and more compact Allows greater memory cell density (more cells per unit area) Cheaper to produce than equivalent SRAM memory Refresh circuitry incurs one-off cost that is only compensated for by larger memory capacities SRAM are typically provide better read and write times than DRAM Cache memory (on and off chip) is often implemented as SRAM, whilst DRAM is commonly used for main memory

What are the disadvantages of polled I/o?

Busy-wait polling wastes CPU time and consumes power Imagine you have a power constrained device, would this be where you want to spend your power? Polling when interleaved with other tasks can lead to a significantly delayed response to device Not a problem for some I/O situations but a serious issue if you're working in a hard real-time context But sometimes it is good enough

What are the fundamentals of a CPU operation?

CPU continuously performs instruction cycle Computational instructions are retrieved from memory, decoded to form recognisable operations and executed to impact the current state of a CPU Commonly known as the fetch-execute cycle or the fetch-decode-execute cycle Instruction cycle takes place over several CPU clock cycles Recall the significance of clocks in sequential logic circuits Fetch-decode-execute cycle relies on interaction of several CPU components, including ALU and CU

What is the effect of an interrupt input?

CPU normally executes instructions sequentially, unless a jump or branch is made An interrupt input can force CPU to jump to a service routine Can therefore make it appear (to humans) that the CPU is performing two or more tasks "simultaneously"

What are the properties of two's complement?

Can represent more negative numbers than positive The range is asymmetric 10002TC = -8 01112TC = +7 For N bits, the range is -2N-1 to (2N-1-1) Unique zero Signed magnitude has both +0 and -0

What is computer organisation?

Computer organisation concerns the structure and properties of a computer system, as viewed form the perspective of a hardware engineer

How does RTL explain fetch?

Contents of Program Counter transferred to MAR address buffers and the Program Counter is incremented 2. MBR loaded from external memory (R/W line set to Read) 3. Opcode transferred to Instruction Register from MBR 4. Instruction is decoded 1. [MAR] ← [PC] 2. [PC] ← [PC] +1 3. [MBR] ← [MS([MAR])] (R/W set to Read) 4. [IR] ← [MBR] 5. CU ← [IR(opcode)]

What is the role of the control unit (CU)?

Control Unit (CU) - Decodes program instructions and handles logistics for the execution of decoded instructions

What are the different direct memory access modes of operation?

Cycle Stealing DMAC uses the system buses when they are not being used by the CPU - usually by "grabbing" available memory access cycles not used by the CPU Burst Mode DMAC requires system buses for extended transfer of large amount of data at high speed and "locks" the slower CPU out of using the system buses for a fixed time or until the transfer is complete or the CPU receives an interrupt from a device of greater priority

Explain 68008 data registers:

D0 - D7, 32 bit registers, store frequently used values / intermediate results ON CHIP Strictly speaking we would only need one register on chip - the advantage of many data registers is that fewer references to external memory are required Registers can be treated as long, word or byte Long - 32-bits Word - 16-bits (lowest 16 bits) Byte - 8-bits (lowest 8 bits)

Why use direct memory access?

DMA is used where large amounts of data must be transferred at high speed Control of the system buses is surrendered by the CPU to a DMA Controller (DMAC). The DMAC is a dedicated device that controls the three system buses during the data transfer. The DMAC is optimised for one operation, i.e., data transfer. The CPU is more general purpose, it both transfers data and is a processor of information. DMA-based I/O can be more than 10 times faster than CPU-driven I/O

How does "decode" work in a CPU?

Decode - Retrieved instruction / operation code / opcode decoded - Read effective address to establish opcode type

What is a decoder?

Decoder has, e.g., binary input pins, and one output pin per possible input state Activate one output pin corresponding to current input state Consider decoding 2 inputs to 4 unique outputs

What are the two viable options of achieving subtraction?

Design a dedicated subtractor circuit Create a representation for negative numbers (A and B can be negative) and extend the adder

What is the relation between digital logic and noise?

Digital logic gives us a high degree of noise immunity Immunity collapses once the noise reaches a certain magnitude - our aim is to not let this happen

What are the disadvantages of interrupts?

Disadvantages All data transfers still controlled by CPU More complex hardware and software

Why is a memory hierarchy important?

Economics! Small sequential loops, subroutines, operations on arrays, tables and other structures mean that the locations in memory which will be accessed is somewhat predictable Temporal locality - If a particular memory location is referenced, it is likely that the same location will be referenced again in the near future Spatial locality - If a particular memory location is referenced, it is likely that nearby memory locations will be referenced in the near future Reasonable assumption - It has been shown that 90% of memory accesses are within ± 2 kilobytes of previous PC position

Logic integrated circuits (LIC):

Elementary logic gates and functions can be obtained in small ICs, e.g., the 7400 series, though programmable devices allow much larger circuits to be created inside a single chip There are many types of programmable logic device Programmable Array Logic (PAL) - The first popular programmable device was one-time programmable Programmable Logic Array (PLA) - Device contains an AND array, which feeds an OR array, providing a sum of products in hardware Field Programmable Gate Array (FPGA) - One of several modern possibilities, which can contain millions of gates, i.e., enough for an entire processor

What is an encoder?

Encode a set of inputs into a defined representation on the outputs (note that this is the reverse of a decoder) Multiple input pins, only one of which should be active at a time Smaller number of output pins Circuit puts code, e.g., binary, of currently active input onto output pins Consider encoding 4 inputs to 2 outputs Does the encoder shown below have active high or active low inputs? Encoders are often used as simple input circuits - though this is limited because you couldn't have 2+ keys held down

Where do errors in a computer system occur?

Errors occur within a computer system, e.g., in system memory, and in the communication between systems, e.g., in the transmission of messages

How does "execute" work in a CPU?

Execute - CU signals functional CPU components - May result in changes to data registers, PC, ALU, I/O, etc...

How does "fetch" work in a CPU?

Fetch - Instruction retrieved from memory location held by PC - Retrieved instruction stored in IR - PC incremented to point to next instruction in memory

What is IEEE floating point?

Floating point representation trades precision for range Extending range at the expense of reducing precision IEEE Standard 754 is widely used and specifies levels of binary precision Single precision (using 32 bits) Double precision (using 64 bits) Quad precision (using 128 bits) For example, single precision uses 1 bit for the sign (s), 8 bits for the exponent (e) and 23 bits for the mantissa (m)

What factors influence the choice of memory technology?

Frequency of access Access time Capacity required Cost, e.g., cost per bit

What are addressing modes used for and why are they needed?

In 68008 systems data can be located in a data register, within the instruction itself or in external memory Addressing modes have expressive power Provide data directly Specify exactly where data is Specify how to go about finding data They are needed to organise data and to tell the compute where they can find the data

What is an instruction register?

Instruction Register (IR) - Contains most recent instruction fetched

What does Post-Incrementing Address Register Indirect mean?

Means take the contents of address register A0, use this number as the address at which the data will be found. Move this data to register D3 and increment A0 General form: move (Ai)+, <ea> Amount by which address register is incremented depends on the type of data being moved, i.e., 1 for bytes, 2 for words, 4 for long words

What does Address Register Indirect with Offset mean?

Means take the contents of address register A1, add to this number a (16-bit two's complement) constant and use this result as the address at which the data will be found. Move this data to register D3 General form: move d16(Ai), <ea> This is where d16 is a 16-bit two's complement number

What is the memory address register?

Memory Address Register (MAR) - Contains address of the region of memory to be read or written, i.e., location of data to be accessed

What is the memory data register?

Memory Data Register (MDR) - Contains data fetched from memory or data ready to be written to memory

Why is cache important?

Memory size is increasing according to Moore's Law Memory access speed is improving much more slowly

I/o mechanisms synthesis:

Memory-mapped input and output devices can be accessed in the same way as RAM, at special address locations Polled I/O is a technique for scheduling input and output, where the CPU repeatedly checks if this is necessary I/O devices are usually much slower than the CPU, so handshaking techniques must be used to coordinate CPU and device to synchronise the transfer of data Interrupts are a way to avoid polled I/O by diverting the CPU to a special I/O routine - quickly and only when necessary If necessary, a DMA controller can be used instead of the CPU to transfer I/O data into/from memory - this can be faster than the CPU but at additional hardware cost Which technique to use? Depends on amount of data, required transfer speed, budget, power, physical size, complexity - this is computer system design

What is the motivation behind synchronisation?

Most I/O devices are much slower than the CPU Several factors to consider Read - Is there data to be read from the device? Write - Is the device ready to accept data? Consider a simple printer that takes a finite amount of time to print a character This time very much greater than the processor instruction time

What is a multiplexer?

Multiplexer - Output is a selected input.

Why is overflow a bad thing in transmitting messages?

Naively exceeding the capacity of a bus may mean that an incorrect message could be transmitted or that an additional message must be transmitted to account for the overflow

What is noise and where does it arise from?

Noise is unwanted information It comes in various forms, but is always present, and is one of the limiting factors in computer systems Noise arises from the physical properties of devices Thermal noise Noise of electronic components Noise of transmission circuits Magnetic media also have a classic form of noise due to random alignment of magnetic fields. Decreased area to store a bit means noise gets worse, making errors likely

What is the difference bteween new and old hard disks?

Older drives have a constant number of sectors per track, which meant that, due to constant angular velocity, bit density is lower on outer tracks Most Recent disks are zoned (10-30 zones), with more sectors in the longer (outer) tracks Many tracks per zone More sectors gives higher capacity Graphic shows a disk with 5 zones

How many bits can a decimal symbol represent?

One decimal symbol requires ≈ 3.3 bits, so hex and octal are more convenient than decimal when describing values on a bus

How is data organisated on a hard disk?

One track contains many sectors Each sector is separated by an inter-sector gap. Sector contains preamble to allow head to be synchronised before read/ write, data and ECC

What is an optical disk?

Originally designed to hold music Max 74 mins - Beethoven's Ninth Symphony! Spiral is 3.5 miles long if unwound 6,000 tracks/cm Data encoded as "pits" and "lands" 15,000 pits and lands/cm

How the 6522 VIA performs handshaking:

PCR 1000xxxx "CB2 handshake output mode" "CB1 Interrupt Flag set by negative transition on CB1" When PRINTER_READY is asserted, i.e., goes high to low VIA sets IFR4, which can be later read by CPU VIA sets DATA_VALID high, i.e., invalid When CPU writes a value to ORB VIA sets DATA_VALID to low (i.e., valid) In this example, the CPU will repeatedly poll IFR to see if PRINTER_READY - we are not (yet) using interrupt

What is parity?

Parity adds an extra bit There are two types of parity system. Even parity system - The value of the extra bit is chosen to make the total number of logic 1s an even number Odd parity system - Make the total number of logic 1s odd Parity bit value can be computed in software or hardware

What can a 1-bit full adder do that a half adder can't?

Performs the addition of three bits Two significant bits and a previous carry

What are the disadvantages of memory-mapped I/o?

Portions of memory address space must be reserved Less of a concern as 64-bit processors, hence address spaces, have come to market Still relevant where 16-bit (and sometimes 32-bit) processors are used, e.g., embedded and legacy systems

What is a program counter?

Program Counter (PC) - Tracks the memory address of the next instruction to be executed

What are the most common forms of main store?

RAM (Random Access Memory) Two main technologies Static RAM (SRAM) Dynamic RAM (DRAM) SRAM use a flip-flop as storage element for each bit DRAM for each bit, use the presence or absence of charge in a capacitor to denote a 1 or 0 Capacitor charge leaks away over time - requires periodic refreshing (more complex) but is cheaper than SRAM so is more commonly used

How does a hard disk work?

Record data by magnetising a thin film of ferromagnetic material on a disk As well as its operations, the general structure of a hard disk can give us insight into performance issues

What is RTL used for?

Register transfer language is used to describe the operations of a microprocessor as it is executing instructions

Explain the performance of a hard disk:

Seek times - time to move arm to correct track Typically about 5ms between different tracks Typically below 1ms for consecutive tracks Rotational latency Constant angular velocity, i.e., motor spins at constant speed Drives available with rotational speeds of 5400 RPM, 7200 RPM or 10800 RPM Average delay (half a rotation) = 3 to 6ms Sector read time is about 0.013ms, which means that seek time and rotational latency dominate access time. Formatting (preambles, ECC etc...) reduces capacity by about 15%

What are the common applications of de-multiplexers?

Share one communication line between multiple senders Requires both MUX and DE-MUX Serial to parallel conversion A control for multiple lights In a gambling machine you might connect a processor to A and S and connect Y outputs to lights, such that the processor runs in a rapid loop addressing each light sequentially

What are the advantages of Polled I/o?

Simple software A looping construct paired with some known checks Simple hardware Support for notion of "ready" is all that is required

What are the advantages of memory mapped I/o?

Simpler than many alternatives Particularly compared to port I/O (where a dedicated class of instructions are defined for performing I/O) CPU requires less internal logic, which can help make the design and fabrication of a CPU cheaper Use of general purpose memory instructions All addressing modes supported by a CPU are available to I/O

What are the common applications of multiplexers?

Source selection control Home stereo, e.g., send iPod, CD or radio to speakers - note that this is analogue not digital Share one communication line between multiple senders Requires both MUX and DE-MUX Parallel to serial conversion Parallel input on X, clock signal on S, serial output on Y Circuit that can be configured to produce any truth table relationship between S inputs and Y output Set up the truth table required on X inputs

How is a stack used for sub-routine calls?

Subroutine Call (JSR) Saves (pushes) the contents of the PC on the stack Puts start address of subroutine in PC Return from Subroutine (RTS) Restores (pops) the return address from the stack and puts it in PC So the stack stores where to return from a subroutine A subroutine can call another subroutine - we have multiple return addresses on the stack in this case

What are some examples of interupts for I/o?

Switches can be connected to IRQ If using multiple switches we can OR them all together to form IRQ and then check the individual switch states within the service routine A hard drive can generate an interrupt when data, requested some time earlier, is ready to read A timer can generate an interrupt every 100ms and the service routine can then read an sensor input A printer can generate an interrupt when it is ready to receive the next character to print, as we will see

What is a 1-bit half adder used for?

The 1-bit half-adder performs the addition of two bits Can be extended to form a 1-bit full-adder

What is the motivation between direct memory access? (DMA)?

The CPU is a bottleneck for I/O Programmed I/O techniques, as in all the examples we've seen so far, are slowed down by the CPU DMA avoids the CPU bottleneck, thus speeding up the transfer of data to memory

What is data or address register direct?

The address of an operand is specified by either a data register or an address register

What is the designer's dilemma?

The designer's dilemma Desire low cost and high capacity - leads to choice of cheap per bit, high capacity and slow access time Desire high performance - leads to choice of expensive per bit, low capacity and fast access time To solve the problem we choose both by organising memory into a hierarchy

What is immediate addressing?

The operand forms part of the instruction and remains constant throughout the execution of a program

What is absolute addressing?

The operand specifies the location in memory explicitly, meaning that no further processing required Absolute addressing does not allow position independent code because a program will consistently use the same memory address

What is the Programmer's Model of 68008 CPU?

The programmer's model is a commonly used abstraction, invariably used by assembler programmers, of the internal architecture of a processor 68008 processor has identical instruction set to the 68000 processor, but has smaller external buses Internal registers are 32-bits wide Internal data buses are 16-bits wide 68008 has an 8-bit external data bus (16-bit on 68000) 68008 has 20-bit external address bus (24-bit for 68000)

What are the two aspects to the 68008 instruction set?

There are two aspects to the 68008 instruction set: Instructions - The commands that tell the processor what operations to perform Addressing Modes - The ways in which the processor can access data or memory locations, i.e., the ways in which addresses may be calculated by the CPU

Why might data transmissions fail and what can we do about it?

These are considered to occur at random, usually due to noise We could send the message three times and take a vote Very expensive Observation that, if the probability of an error in the channel is low, the probability of two errors close together is even lower Thus, we can add a "parity" bit to the message every so often, which "summarises" a property of the message that we can check to determine whether the message has been altered Much cheaper and adequate in many situations

How is two's complement formed?

To form the bit pattern for a negative number in two's complement: Take the representation of the positive number Invert the bits, ensuring there are enough bits for the MSB to be the sign Add 1, ignoring any overflow What is the two's complement bit pattern for -9? +910 = 10012 Ensure enough bits: 000010012 Invert: 111101102 Add 1: 111101112 -910 = 111101112TC

Error parity example

Transmitter and receiver have been designed to use even parity Message: 100 0101 Transmitter computes P=1 Transmits: 1100 0101 An error in the channel changes one bit Received: 1101 0101. Receiver notes received P=1 Receiver uses the data bits (101 0101) to compute Q=0 Receiver compares received P and computed Q. An error has been detected, thus receiver will ask for retransmission

How does RTL explain fetch and execute?

We can represent complex actions, such as adding a constant byte to D0 1. [MAR] ← [PC] 2. [PC] ← [PC] +1 3. [MBR] ← [MS([MAR])] (R/W set to Read) 4. [IR] ← [MBR] 5. CU ← [IR(opcode)] 6. [MAR] ← [PC] 7. [PC] ← [PC] +1 8. [MBR] ← [MS([MAR])] 9. ALU ← [MBR] + D0 10. [D0] ← ALU

Can an interrupt be neseted?

Yes, see diagram in book

What is pipelining?

a form of computer organization in which successive steps of an instruction sequence are executed in turn by a sequence of modules able to operate concurrently, so that another instruction can be begun before the previous one is finished.

What is address register indirect?

move (A0), D3 Means take the contents of address register A0 and use this number as the address at which the data will be found. Move this data to register D3 General form: move (Ai), <ea> Remember <ea> is an effective address and can be Dj, (Aj), etc..

What is relative addressing?

move d16(PC), D3 Code like this contains no absolute addresses, i.e., it uses only addresses relative to the current program counter, and therefore can be placed anywhere in memory This addressing mode can be used to write "position independent code" Be careful - small addressing errors can have big consequences

What does Pre-Decrementing Address Register Indirect mean?

move.b -(A0), D3 Means decrement the contents of address register A0, and use this number as the address at which the data will be found. Move this data to register D3. General form: move -(Ai), <ea> Amount by which the address register is decremented depends on the type of data being moved

What does indexed addressing mean?

move.l $1F(A0, A1), D3 Means add the contents of address register A0 to A1, add to this the (8-bit two's complement) hex constant 1F and use this number as the address at which the data will be found. Move this data to register D3. General form: move d8(Ai, Xj), <ea> Xj can be an address or data register, d8 is an 8-bit two's complement constant