Computer Organization Ch4

A 16-bit ISA has the following format: <OPCODE><DR><SR0><SR1> where DR is the Destination register and SR0 and SR1 are source registers. If the ISA defines 16 registers then the maximum number of opcodes support by this format is ________.

16

The Von Neumann model consists of ________ parts

5

For a particular 16-bit ISA, the LDR instruction has the following format: <Opcode = 0110><DR><BaseReg><OFFSET>. If there are 4 registers, the number of bits available to specify the offset is ________.

8

________ Instructions are used to change the sequence of instruction execution.

Control

JMP is an example of a/an

Control Instruction

LDR is an example of a/an

Data Movement Instruction.

Control Instructions change the value of PC in the

EXECUTE phase.

Memory is ALWAYS accessed in the following phase of an instruction cycle

FETCH

The sequence of an Instruction cycle is:

FETCH -> DECODE -> EVALUATE ADDRESS -> FETCH OPERANDS -> EXECUTE -> STORE RESULT

During what phase is the PC incremented so that during the next instruction cycle, the next instruction will be processed.

FETCH phase

All computer instructions MUST execute all six phases of the instruction cycle.

False

For the LC-3 ISA, the LDR instruction requires an Execute phase.

False

Normally, the value in the Program Counter remains unchanged as a result of carrying out the Fetch phase of the instruction cycle.

False

Some instructions do not require the Fetch phase.

False

The Evaluate Address phase can be executed before the Instruction Decode phase.

False

The Processing unit interacts with memory using the Memory Status Register and the Memory Data Register.

False

The function of the Instruction Register is to point to next instruction to be processed.

False

The ________ is the smallest unit of work specified in a computer program, such that either the whole unit must be carried out or none of it must be carried out. We refer to such a unit as an "atomic" unit of work

Instruction

The sequence of six phases that process an instruction is called the ________ ________.

Instruction Cycle

To read the contents of a memory location, we first place the address of that location in the ____________. (please use abbreviation)

MAR

In the FETCH phase, an instruction is transferred from ________ to the Instruction Register.

Memory

The Decode phase of the Instruction Cycle examines the ________ part of the instruction.

Opcode

An instruction is made up of two parts: the opcode and the ________.

Operand

ADD is an example of a/an

Operate instruction

For the LC-3 ISA, the ADD instruction does not require an EVALUATE ADDRESS phase.

True

If the instruction at address x4000 is being processed then it is possible that the next instruction to be processed is at address x5000.

True

Most ISA's provides some small temporary storage very close to the ALU to allow the results to be temporarily stored.

True

The Instruction Decode phase is required of all instructions.

True

The time required to access registers is less than the time required to access memory.

True

The Program Counter contains the ________ of the next instruction to be processed.

address

Typically the size of each register is ________ the size of values processed by the ALU.

identical to

The control unit has a/an ________ ________ that points to next instructions to be processed

program counter