CS 309 Exam 2 Chapter 3

With literal addressing a ___ is used to mark the addressing mode as literal. There is no effective address. The data is part of the instruction.

#

How does C++ handle overflows?

Has the ability to detect and throw an overflow exception but you still have to handle it

the program can affect but not directly accessed - Program Counter (PC) can be controlled by the programmer but only by execution of branch instructions. Stack Pointer, CCR.

special purpose register

If you what to subtract with literal addressing you have to use the _____________instruction. SUB r2, r3 #34

subtract

Based on a calculation or the value of a register branch or do not branch to a certain location.

conditional behavior

In some assemblers if the literal is not valid (too big) it will automatically define a memory location for you and assign the value to that location. The instruction is also changed from literal addressing to ___________.

direct

So: LDR r1, 1234 // would get the data from memory location 1234 and take those contents and put them into r1. This is called __________ _____________. Important- The ARM does not support direct addressing. In RTL notation, [r1] <-- [1234]

direct addressing

[R0] <- [1234] RTL notation. This is a _____________ _____________ mode instruction. The effective address is part of the instruction. More on this later. Note: ARM does not support direct addressing.

direct addressing

How does assembly handle overflows?

doesn't handle it you have to check the overflow bit and do all that code yourself

What are the 4 major hardware parts of a modern central process unit (CPU)?

1) Arithmetic and Logic Unit (ALU) - Does operations on one operand (unary operation) or two operands (binary operations) or three operands (tertiary operations). 2) Memory - Registers, Random Access Memory, Read Only Memory 3) Buses - allows the transfer of information from various locations within the CPU, memory, IO devices, etc. 4) Control Unit - Based on the instruction and addressing modes sends signals to the registers, ALU, Buses, Memory, Input/output devices to execute the instruction.

What are the three ARM instruction formats?

1) Memory to Register 2) Register to Memory 3) Register to Register

There is a limit on the size of literals, What is the limit on the ARM?

12 bit unsigned integer

For right now assume when a branch is taken then IR(____________) overwrites what is in the PC.

23 - 0

What is the numerical value of the limit on literals on the ARM?

2^12 = 4096

When the ALU performs an operation, it stores status or condition information in the CCR. The processor records whether the result is: zero (Z) negative in two's complement terms (N), bit ____ is 1. generated a carry (C), carry from bit 31 full adder. arithmetic overflow (V).

31

Assembly Instructions for the ARM have the following general format

<instruction> <operand1>, <operand2>, <operand3>

The CCR flags come from the results of the __________. They are provided as inputs to the Control Unit.

ALU

Intel register names _____, BX, CX, DX, ____, BP, SI

AX, SP

The Program Counter, Memory address registers and Operands part of IR share the ________________ bus.

Address

SUBS r5, r5, #1 @Decrement the loop counter BEQ onZero @When the counter hits zero exit the loop not Zero: ADD r1, r2, r3 onZero: SUB r1, r2, r3 OnZero is the ___________ ______________ ____________ (BTA) in this case it is much like an immediate addressing mode in that the BTA is part of the instruction.

Branch target address

What is the RTL notation for ADD r0, r1, r2?

Bus P <- [R1] Bus Qmbr <- [R2] [R0] <- Add (P, Qmbr) Reg0 <- Reg1 + Reg2. Reg1 and Reg2 remain unchanged.

What is the RTL notation for SUB r0, r1, r2?

Bus P <- [R1] Bus Qmbr <- [R2] [R0] <- Sub (P, Qmbr) Reg0 <- reg1 - reg2. Reg1 and Reg2 remain unchanged

___________ processors, like the Intel IA32 update status flags after each operation. RISC processors, like the ARM, require the programmer to determine when the status flags are updated.

CISC

Instead of adding an S to the end of instructions you can just use a _______ (compare) or _______ (Test) instruction which forces the CCR update as well.

CMP, TST

Contains bits that show the results of the ALU calculations. In the case of the ARM: Z - Zero, N - Negative, C - Carry, V -Overflow.

Condition Code Register (CCR)

How does the instruction ADD r1, r2, r3 get executed by the CPU?

Control signals from the control unit to execute the instruction: Bus P <- [r2]; Bus Q <- [r3]; [r1] <- ADD(P, Q)

The operand part of the IR, MBR, Registers, and ALU share the _______________ Bus

Data

How does Java handle overflows?

Does not automatically throw an error or overflow exception

Control signals for r0, r2, #50

IR (11-0) Out to data bus P <- r2 r0 <- Add (P, Qliteral)

Control signals for LDR r1, #200

IR(11-0) Out to data bus R1 Xfer(Qliteral)

What is the RTL notation for BPL target?

If CCR (Z and not N) then [PC] <- [IR 23 - 0] IR out to address bus Branch on positive to location target. If the result of the previous operation was positive or zero then go to location target and start program execution there. If the result was negative then the next instruction after the BPL will be executed

What is the RTL notation for BEQ target?

If CCR Z then [PC] <- [IR 23 - 0] IR out to address bus Branch equal. If the result of the previous operation was zero then go to location target and start program execution there. If the result was not zero then the next instruction after the BEQ will be executed.

This contains the current instruction being executed. The instruction is decoded and control signals are generated to execute the instruction.

Instruction register (IR)

What do you have to consider about the hardware for conditional behavior?

It starts with the ALU. Have to have a way to determine and keep the results of the last ALU operation. The results go into the CCR. Based on the contents of the CCR make, or do not make the jump. If the condition is not met we do not have to do anything. By default the next instruction is executed. If the branch has to be made the PC has to be updated to the location stored in the instruction.

What ARM instruction is memory to register?

LDR (load register)

Example of the general format of ARM instructions

LDR r0, 1234

LDR r1, #200 loads 200 into r1. @This does not work on ARM assembly ________ r1, #200 @ this is the correct syntax for the ARM assembly Literal addressing saves a memory access so they run faster.

MOV

What does the hardware look like to implement these flags? Z - 32 input ________ gate C - Carry out from bit 31 full adder N - Bit _____ value. V - Sign bit is same for both numbers but the sign of the result is different. a(n - 1)b(n-1)s(n-1)' + a(n-1)'b(n-1)'s(n-1)

NOR, 31

What is wrong with the instruction LDR r8, #5000?

Over the limit of 4096

Add(p, q) will add bus ____ to bus ____.

P, Q

Add(P, Qliteral) will add bus ____ to ______________

P, Qliteral

Add(P, Qmbr) will add bus __ to ________

P, Qmbr

For the ARM an "____" needs to be added to the end of the instruction to get the CCR updated. For example ADDS SUBS

S

The ____ at the end of the instruction sets the flags in the Condition Code Register (CCR).

S

What ARM instruction is register to memory?

STR (store register)

What does the instruction LDR r0, 1234 do?

Takes the contents of memory location 1234 and loads the value into reg0 [R0] <- [1234] (RTL notation)

What does the instruction ADD r1, r2, r3 do?

Takes the contents of reg2 and reg3, adds them together and stores the results into reg1. reg2 and reg3 remain unchanged. [r1] <- [r2] + [r3] (RTL notation)

What does the instruction STR r1, 3456 do?

Takes the contents of register 1 and stores the value into memory location 3456 [3456] <- [R1] (RTL notation)

What is wrong with the instruction SUB r1, #56, r2?

The literal has to come last

The computer hardware has to be in place to detect and status these conditions (CCR flags). The overflow status bit is given the symbol "___".

V

What is wrong with the instruction LDR r1, #-20?

You can't have signed integers

What all does the CCR contain? Z - ____________ N - ____________ C - ____________ V - _____________

Zero, negative, carry, overflow

What is the RTL notation for LDR r0, address?

[MAR] <- [Address part of IR] (IR out to data bus} [MBR] <- [[MAR]] (Read memory) [R0] <- [MBR], Xfer (Qmbr) Takes the contents of memory location at address and copies it to reg0. Note: This is direct addressing which the ARM does not support.

What is the LDR instruction with direct address in RTL notation?

[MAR] <- [Address part of IR] (The address of the operand is part of the instructions) [MBR] <- [[MAR]] (Read the data from memory and store results) [Rx] <- [MBR] via the data (Move the data to register x. Because the way the control unit works we do not need to specify)

What is the RTL notation for STR r0, address?

[MAR] <- [Address part of IR] IR out to data bus [MBR] <- [R0], Xfer(P) [[MAR]] <- [MBR] (Write to memory) Takes the contents of register 0 and copies the value to the memory location address. (direct addressing which the arm doesn't support)

What is the instruction fetch routine in RTL notation?

[MAR] <- [PC] (Get ready to fetch the next instruction from memory) [PC] <- [PC] + 4 (Point to the next instruction) [MBR] <- [[MAR]] (Read the instruction from memory and store the results) [IR] <- [MBR] (Transfer the instruction the instruction register and start decoding process)

Reading from memory RTL notation

[MBR] <- [[MAR]]

What is the RTL notation for B target?

[PC] <- [Address part of IR] IR out to address bus Unconditional branch. Go to location target and start program execution

Writing to memory RTL notation

[[MAR]] <- [MBR]

MOV r1, #200 in RTL notation

[r1] <- 200

LDR r1, #200 in RTL notation

[r1] <- [200]

can be accessed/used by the programmers - for example r0 can be used by the programmer to store any data type or address.

general purpose register

Since the data is contained in the instruction there has to be _____________ which can put that part of the instruction register (IR) onto the bus so it can be transferred around the processor and be used for calculations. The IR decoder has to recognize the addressing mode then have the hardware to only put that constant on the bus to do the operations. Note the 32-bit instruction or 32-bit data from memory is much larger than the number of bits for the literal addressing. The high order bits have to be set to 0.

hardware

needed by the CPU but cannot be directly controlled by the programmer. Examples IR, MAR, MBR.

invisible registers

How does C handle overflows?

keeps on going like nothing happened

The literal has to be the _______ operand of the assembly instruction.

last

Instead of the instruction pointing to the location of the data the instruction contains the data.

literal addressing

______________ _________________ can be used in other instructions: ADD r0, r2, #50

literal addressing

This contains the address of the data that is being read from or written to memory.

memory address register (MAR)

This contains the data that is being read from or written to memory.

memory buffer register (MBR)

What is the format for register to register instructions on the ARM?

operation <reg destination>, <reg source1>, <reg source2>

Sub(p, q) will subtract ____ minus ____

p, q

This contains the address of the next instruction to be fetched from memory.

program counter (PC)

Limiting operations only to registers greatly simplifies the hardware of the CPU but more instructions have to be written by the _________________ to get the same effect. This is one of the trades offs with CPUs of this nature.

programmer

Register file is a set of 16 registers that store data.

r0 - r15

ARM register names ______, ________, . . . , r15.

r0, r1

Once something goes out to the bus then nothing else can be put on the same bus until the next "_______ ________". Not sure the text address this at all. The next time slot or clock pulse will clear all the current control signals.

time slot