CS061 Chapter 5

Data Type

A data type is a representation of information such that the ISA has opcodes that operate on that representation. There are many ways to represent the same information in a computer. If the ISA has an opcode that operates on information represented by a data type, then we say the ISA supports that data type.

ADD and AND instructions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 ADD Rl R4 R5

ADD and AND perform binary operations; they require two 16-bit source operands. The ADD instruction performs a 2's complement addition of its two source operands. The AND instruction performs a bit-wise AND of each pair of bits in its two 16-bit operands. Like the NOT, the ADD and AND use the register addressing mode for one of the source operands and for the destination operand. Bits [8:6] specify the source register and bits [11;9] specify the destination register (where the result will be written). The second source operand for both ADD and AND instructions can be specified by either register mode or as an immediate operand. Bit [5] determines which is used. If bit [5] is 0, then the second source operand uses a register, and bits [2:0] specify which register. In that case, bits [4:3] are set to 0 to complete the specification of the instruction. If bit [5] is 1, the second source operand is contained within the instruction. In fact, the second source operand is obtained by sign-extending bits [4:0] to 16 bits before performing the ADD or AND.

Addressing mode - what is it? What are the 3 places where an operand can be found?

An addressing mode is a mechanism for specifying where the operand is located. Operand can be found in memory, in a register, or as a part of the instruction.

address generation bits 15 14 13 12 - 11 10 9 - 8 7 6 5 4 3 2 1 0 opcode | DR or SR | Addr Gen bits |

Bits [8:0] contain the address generation bits. That is, bits [8:0] encode information that is used to compute the 16-bit address of the second operand. In the case of the LC-3's data movement instructions, there are four ways to interpret bits [8:0]. They are collectively called addressing modes. The opcode specifies how to interpret bits [8:0]. That is, the LC-3's opcode specifies which addressing mode should be used to obtain the operand from bits [8:0] of the instruction.

Control Instructions

Control instructions change the sequence of the instructions that are executed. The LC-3 has five opcodes that enable this sequential flow to be broken: conditional branch, unconditional jump, subroutine (sometimes called function) call, TRAP, and return from interrupt.

DECODE

DECODE phase -- the contents of the IR are decoded, resulting in the control logic providing the correct control signals (unfilled arrowheads) to control the processing of the rest of this instruction. The opcode is 0110, identifying the LDR instruction. This means that the Base+offset addressing mode is to be used to determine the address of data to be loaded into the destination register R3.

Conditional Branches 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 1 BR N Z P xOD9

During the EXECUTE phase, the processor examines the condition codes whose corresponding bits in the instruction are 1. That is, if bit [ 11 ] is 1, condition code N is examined. If bit [10] is 1, condition code Z is examined. If bit [9] is 1, condition code P is examined. If any of bits [11:9] are 0, the corresponding condition codes are not examined. If any of the condition codes that are examined are in state 1, then the PC is loaded with the address obtained in the EVALUATE ADDRESS phase. If none of the condition codes that are examined are in state 1, the PC is left unchanged. In that case, in the next instruction cycle, the next sequential instruction will be fetched. If all three bits [11:9] are 1, then all three condition codes are examined. In this case, since the last result stored into a register had to be either negative, zero, or positive (there are no other choices), one of the three condition codes must be in state 1. Since all three are examined, the PC is loaded with the address obtained in the EVALUATE ADDRESS phase. We call this an unconditional branch since the instruction flow is changed unconditionally, that is, independent of the data that is being processed. The control instructions permit the reuse of sequences of code by breaking the sequential instruction execution flow.

FETCH

FETCH phase -- In the first cycle, the contents of the PC are loaded via the global bus into the MAR, and the PC is incremented and loaded into the PC. At the end of this cycle, the PC contains x3457. In the next cycle (if memory can provide information in one cycle), the memory is read, and the instruction 0110011010000100 is loaded into the MDR. In the next cycle, the contents of the MDR are loaded into the instruction register (IR), completing the FETCH phase.

STORE RESULT

In the last cycle, the contents of the MDR are loaded into R3. The DR control field specifies Oil, the register to be loaded.

OPERAND FETCH

In the next cycle (or more than one, if memory access takes more than one cycle), the data at that address is loaded into the MDR.

EVALUATE ADDRESS

In the next cycle, the contents of R2 (the base register) and the sign-extended bits [5:0] of the IR are added and supplied via the MARMUX to the MAR. The SRI field specifies 010, the register to be read to obtain the base address. ADDR1 MUX selects SRI OUT, and ADDR2MUX selects the second from the right source.

LC-3 has how many operate instructions, what are they?

LC-3 has three operate instructions: ADD, AND, and NOT

How many different opcodes (instructions) and what types of instructions does a LC3 have

LC3 has a total of 15 opcodes. 4 bits are used to specify opcode 3 types - operates, data movement, and control

PC-Relative Mode 15 14 13 12 -- 11 10 9 -- 8 7 6 5 4 3 2 1 0 0 0 1 0 -- 0 1 0 -- 1 1 0 1 0 1 1 1 1 LD -- R2 --- xlAF

LD (opcode = 0010) and ST (opcode = 0011) specify the PC-relative addressing mode. This addressing mode is so named because bits [8:0] of the instruction specify an offset relative to the PC. The memory address is computed by sign extending bits [8:0] to 16 bits, and adding the result to the incremented PC. The incremented PC is the contents of the program counter after the FETCH phase; that is, after the PC has been incremented. If a load, the memory location corresponding to the computed memory address is read, and the result loaded into the register specified by bits [11:9] of the instruction. In step 1, the incremented PC (x4019) is added to the sign-extended value contained in IR[8:0] (xFFAF), and the result (x3FC8) is loaded into the MAR. In step 2, memory is read and the contents of x3FC8 are loaded into the MDR. Suppose the value stored in x3FC8 is 5. In step 3, the value 5 is loaded into R2, completing the instruction cycle. Note that the address can only be within +256 or —255 locations of the LD or ST instruction since the PC is incremented before the offset is added. This is the range provided by the sign-extended value contained in bits [8:0] of the instruction.

Indirect Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0 LDI R3 xlCC

LDI (opcode — 1010) and STI (opcode = 1011) specify the indirect addressing mode. An address is first formed exactly the same way as with LD and ST. However, instead of this address being the address of the operand to be loaded or stored, it contains the address of the operand to be loaded or stored. Hence the name indirect. Note that the address of the operand can be anywhere in the computer's memory, not just within the range provided by bits [8:0] of the instruction as is the case for LD and ST. The destination register for the LDI and the source register for STI, like all the other loads and stores, are specified in bits [11:9] of the instruction. Step 1 consists of adding the incremented PC (x4AlC) to the sign-extended value contained in IR[8:0] (xFFCC), and the result (x49E8) loaded into the MAR. In step 2, memory is read and the contents of x49E8 (x2110) is loaded into the MDR. In step 3, since x2110 is not the operand, but the address of the operand, it is loaded into the MAR. In step 4, memory is again read, and the MDR again loaded. This time the MDR is loaded with the contents of x2110. Suppose the value —1 is stored in memory location x2110. In step 5, the contents of the MDR (i.e., — 1) are loaded into R3, completing the instruction cycle.

Base+offset Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 LDR R1 R2 xlD

LDR (opcode = 0110) and STR (opcode = 0111) specify the Base+offset addressing mode. The Base+offset mode is so named because the address of the operand is obtained by adding a sign-extended 6-bit offset to a base register. The 6-bit offset is literally taken from the instruction, bits [5:0]. The base register is specified by bits [8:6] of the instruction. The Base+offset addressing uses the 6-bit value as a 2's complement integer between —32 and +31. Thus it must first be sign-extended to 16 bits before it is added to the base register. Step 1 the contents of R2 (x2345) are added to the sign-extended value contained in IR[5:0] (xOOlD), and the result (x2362) is loaded into the MAR. Step 2, memory is read, and the contents of x2362 are loaded into the MDR. Suppose the value stored in memory location x2362 is xOFOF. Step 3, the contents of the MDR (in this case, xOFOF) are loaded into Rl. Note that the Base+offset addressing mode also allows the address of the operand to be anywhere in the computer's memory.

Immediate Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 LEA R5 -3

LEA (opcode =1110) loads the register specified by bits [11:9] of the instruction with the value formed by adding the incremented program counter to the sign-extended bits [8:0] of the instruction. The immediate addressing mode is so named because the operand to be loaded into the destination register is obtained immediately, that is, without requiring any access of memory. Again, LEA is the only load instruction that does not access memory to obtain the information it will load into the DR. It loads into the DR the address formed from the incremented PC and the address generation bits of the instruction. The LEA instruction is useful to initialize a register with an address that is very close to the address of the instruction doing the initializing. If memory location x4018 contains the instruction LEA R5, # - 3 , and the PC contains x4018, R5 will contain x4016 after the instruction at x4018 is executed.

Data movement instructions: How many are there? Where do they move data to and from? Load? Store?

The LC-3 contains 7 instructions that move information: LD, LDR, LDI, LEA, ST, STR, and STI.

Memory

Memory is accessed by loading the memory address register (MAR) with the address of the location to be accessed. If a load is being performed, control signals then read the memory, and the result of that read is delivered by the memory to the memory data register (MDR). On the other hand, if a store is being performed, the data to be stored is first loaded into the MDR. Then the control signals specify that WE is asserted in order to store into that memory location.

MARMUX

Memory is accessed by supplying the address to the MAR. The MARMUX controls which of two sources will supply the MAR with the appropriate address during the execution of a load, a store, or a TRAP instruction. The right input to the MARMUX is obtained by adding either the incremented PC or a base register to a literal value or zero supplied by the IR. Whether the PC or a base register and what literal value depends on which opcode is being processed. The control signal ADDR1MUX specifies the PC or base register. The control signal ADDR2MUX specifies which of four values to be added. The left input to MARMUX provides the zero-extended trapvector, which is needed to invoke service calls,

Two common methods for controlling the number of iterations of a loop

Method 1 -- Use of a counter. If we know we wish to execute a loop n times, we simply set a counter to n, then after each execution of the loop, we decrement the counter and check to see if it is zero. If it is not zero, we set the PC to the start of the loop and continue with another iteration. Method 2 -- use of a sentinel. This method is particularly effective if we do not know ahead of time how many iterations we will want to perform. Each iteration is usually based on processing a value. We append to our sequence of values to be processed a value that we know ahead of time can never occur (i.e., the sentinel). For example, if we are adding a sequence of numbers, a sentinel could be a # or a *, that is, something that is not a number. Our loop test is simply a test for the occurrence of the sentinel. When we find it, we know it is time to stop.

Opcode Operands Addressing modes

Opcode: what the instruction is asking the computer to do (e.g ADD) Operands: who the computer is expected to do it to Addressing modes determine where the operands are located (e.g register mode).

What do these type of instructions do? Operate instructions Data movement instructions Control instructions

Operate instructions process information. Data movement instructions move information between memory and the registers and between registers/memory and input/output devices. Control instructions change the sequence of instructions that will be executed.

NOT instructions 15 14 13 12 - 11 10 9 - 8 7 6 - 5 4 3 2 1 0 1 0 0 1 - 0 1 1 - 1 0 1 - 1 1 1 1 1 1 NOT - R3 - R5

Performs a unary operation, that is, the operation requires one source operand. The NOT instruction bit-wise complements a 16-bit source operand and stores the result of this operation in a destination. NOT uses the register addressing mode for both its source and destination. Bits [8:6] specify the source register and bits [11:9] specify the destination register. Bits [5:0] must contain all Is. Know the key part of the data path for a NOT opcode

ALU and Register File

The ALU is the processing element. It has two inputs, source 1 from a register and source 2 from either a register or the sign-extended immediate value provided by the instruction. Note the mux that provides source 2 to the ALU. The select line of that mux, coming from the control logic, is bit [5] of the LC-3 operate instruction. The result of an ALU operation is a result that is stored in one of the registers, and the three single-bit condition codes. Note that the ALU can supply 16 bits to the bus, and that value can then be written into the register specified by the 3-bit register number DR. Also, note that the 16 bits supplied to the bus are also input to logic that determines whether that 16-bit quantity is negative, zero, or positive, and sets the three registers N, Z, and P accordingly.

Global Bus

The LC-3 global bus consists of 16 wires and associated electronics. It allows one structure to transfer up to 16 bits of information to another structure by making the necessary electronic connections on the bus. Exactly one value can be transferred on the bus at one time.

Condition Codes

The LC-3 has three single-bit registers that are set (set to 1) or cleared (set to 0) each time one of the eight general purpose registers is written. The three single-bit registers are called N, Z, and P, corresponding to their meaning: negative, zero, and positive.

EXECUTE

The LDR instruction does not require an EXECUTE phase, so this phase takes zero cycles.

PC and PCMUX

The PC supplies via the global bus to the MAR the address of the instruction to be fetched at the start of the instruction cycle. The PC, in turn, is supplied via the three-to-one PCMUX, depending on the instruction being executed. During the FETCH phase of the instruction cycle, the PC is incremented and written into the PC. That is shown as the rightmost input to the PCMUX. If the current instruction is a control instruction, then the relevant source of the PCMUX depends on which control instruction is currently being processed. If the current instruction is a conditional branch and the branch is taken, then the PC is loaded with the incremented PC + PCoffset (the 16-bit value obtained by sign-extending IR[8:0]). Note that this addition takes place in the special adder and not in the ALU. The output of the adder is the middle input to PCMUX. The third input to PCMUX is obtained from the global bus.

TRAP instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 0 0 trapvector

The TRAP (opcode = 1111) instruction changes the PC to a memory address that is part of the operating system so that the operating system will perform some task in behalf of the program that is executing. In the language of operating system jargon, we say the TRAP instruction invokes an operating system SERVICE CALL. Bits [7:0] of the TRAP instruction form the trapvector, which identifies the service call that the program wishes the operating system to perform. A program can, during its execution, request services from the operating system and continue processing after each such service is performed.

J MP Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 JMP R2

The conditional branch instruction, for all its capability, does have one unfortunate limitation. The next instruction executed must be within the range of addresses that can be computed by adding the incremented PC to the sign-extended offset obtained from bits [8:0] of the instruction obtained from bits [8:0] of the instruction. Since bits [8:0] specify a 2's complement integer, the next instruction executed after the conditional branch can be at most +256 or —255 locations from the branch instruction itself. Since registers contain 16 bits, the full address space of memory, the JMP instruction has no limitation on where the next instruction to be executed must reside.

Tri-state device

This triangle (called a tri-state device) allows the computer's control logic to enable exactly one supplier to provide information to the bus at any one time. The structure wishing to obtain the value being supplied can do so by asserting its LD.x (load enable) signal

Loop

We use the term loop to describe a sequence of instructions that get executed again and again under some controlling mechanism. Each time the body of the loop executes, one more integer is added to the running total, and the counter is decremented so we can detect whether there are any more integers left to add. Each time the loop body executes is called one iteration of the loop.

LC-3 supports five addressing modes. What are they?

immediate (or literal): operand found in the instruction itself register: three memory addressing modes: PC-relative, indirect, and Base+offset.