CSCI 3130

Feedback Circuit: SR Flip Flop

(set/reset) composed of two NOR gates resulting in the most basic memory unit

Truth Table

-Refer to sheet -09/07/2021 slides

System Bus1

1. A bus the connects major components (CPU, memory, Input/Output ( I/O)) is called a system bus and it consist of 100s of lines. • 2. A system bus is divided into 3 functional groups: •Data bus •Address bus •Control bus • 3. The information in the bus are usually broadcasted •i.e., everyone listens. ( I/O devices such as keyboard, Monitors, Memory, and so on) •Only one device can read/write data to/from the bus at a time •Everyone else can only monitor the data

The Input/Output Subsystem

1. A computer communicates with the outside world through its input/output (I/O) subsystem. 2. I/O devices connect to the CPU through various interfaces. 3. I/O can be memory-mapped-- where the I/O device behaves like main memory from the CPU's point of view. 4. Or I/O can be instruction-based, where the CPU has a specialized I/O instruction set. It can be only used by CPUs that can execute these specific instructions.

Multipoint Bus

1. Because of the sharing of bus lines, the bus protocol (set of usage rules) is very important 2. A bus that is shared by a number of devices (also called a common pathway bus).

Address Bus

1. Identify the source or destination of data •In general, the address specifies memory address or a specific I/O port 2. CPU needs to read an instruction (data) from a given location in memory 3. Bus width determines maximum memory capacity of system •8 lines indicates 8-bit address: 2^8 addressable memory = 256 bytes •16 lines indicates 16-bit address: 2^16 addressable memory = 65536 bytes = 65536/1024 = 64 Kbytes •32 lines indicates 32-bit address: 2^32 addressable memory = 4 GB

Control Bus

1. It regulates the activity on the bus 2. Control and timing information •Determines what modules can use the data and address lines •If a module wants to send data, it must : 1.Obtain permission to use the bus 2.Transfer data 3. It carries signals that reports the status of various devices. 4. Typical control lines •Memory read (data copy from address location to data bus) •Memory write (data copy from bus to address location ) •I/O read •I/O write •Bus Request •Bus Grant •Clock signals

Memory3

1. Memory : 4M x 8 RAM chip •How does the computer access a memory location corresponds to a particular address? 2. We observe that 4M can be expressed as 22 ´ 220 = 222 words. 1 word is equal to 1 byte in machine with 8-bit words. 3. The memory locations for this memory are numbered 0 through 222 - 1. 4. Thus, the memory bus of this system requires at least 22 address lines. •The address lines "count" from 0 to 222 - 1 in binary. Each line is either "on" or "off" indicating the location of the desired memory element.

CPU Basics2

1. Registers hold data that can be readily accessed by the CPU. •They can be implemented using D flip-flops. •A 32-bit register requires 32 D flip-flops.

Asynchronous Bus

1. Use handshaking protocol to enforce timing 2. Example: To read a word of data from memory the following steps should be performed: •ReqREAD: The control line is activated and the data memory address is put on address bus. •ReadyDATA: This control line is asserted when the memory system has put the required data on data bus. •ACK: This control line is used to indicate that the ReqREAD or ReadyDATA has been acknowledged. 3. Asynchronous bus scales better with technology and can support wide variety of devices.

Characteristics of Buses

1. We measure data transfer by two metrics: •Total number of bits we can transfer in parallel. This is called width of the data. •The clock rate or frequency (in Hertz) of the bus. • 2. Each time data is sent or received is considered one cycle. • 3. A bus with a width of 32 bits and a frequency of 100 MHz, has a transfer speed of 400 MB/s. •(32 *100 *10^6 ) bits per second (bps) •(32 *100 *10^6 )/8 bytes per second (Bps) •400000000 bytes per second (Bps) •400000000/ 10^6 bytes per second (Bps) •400 Mega Bytes per second (MBps)

Components of RSC

1.CPU •Registers •Arithmetic Logic Unit •Control Unit 2.Bus •Input/Output system •Memory

Multiplexer Advantages

1.Reduces number of wires. 2.Reduces circuit complexity and cost. 3.Can be useful to implement various circuits using MUX.

Multiplexer (MUX)

A device that separates a medium into multiple channels and issues signals to each of those subchannels.

D flip flop

A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs

What is the difference between latch and a flip flop?

A latch is level-sensitive, while a flip-flop is edge-triggered.

Full Adders

A unit which adds together two input variables. A full adder can a bit carried from another addition as well as the two inputs.

Boolean Operators

AND, OR, XOR, NAND and NOT used in search strings to refine the scope of the search

Sum-Of-Products

ANDed variables are ORed together.

JK flip flop

Augments the behavior of the SR Flip-Flop where J = set and K = reset. It interprets the S and R equal to 1 as the flip or toggle command

Edge-triggered (Flip flop)

Circuits that change state on the rising edge or falling edge of the clock pulse

Boolean Operator: OR

Contains at least one of the items.

RSC Registers

Eight registers: Z, IR, MAR/AR, MDR/DR, PC, OUTR, ACC, R

High-Order Memory Interleaving (HOI)

Example: suppose we have a byte addressable memory consisting of 8 module (chip) of 4 bytes each, for a total of 32 byte of memory. •We need 5 bits to uniquely identify each byte. •Leftmost 3 of those bits are used to determine the module (2^3 = 8 modules) •And the remaining 2 bits to determine the offset within that module.

Low-order Memory Interleaving (LOI)

Example: suppose we have a byte addressable memory consisting of 8 module (chip) of 4 bytes each, for a total of 32 byte of memory. •We need 5 bits to uniquely identify each byte. •Rightmost 3 of those bits are used to determine the module (2^3 = 8 modules) •And the remaining 2 bits to determine the offset within that module.

Mod 7 Counter using JK flip flop

For truth table, first 3 columns 0-6, next 3 columns add 1, then use excitation table

NOR Gate

Logic circuit that operates like an OR gate followed by an INVERTER. The output of a NOR gate is LOW (logic level 0) when any or all inputs are HIGH (logic level 1).

1.5 Memory

Memory is 32K = 2^5 x 2^10 = 2^15

Product-Of-Sums

ORed variables are ANDed together.

XOR Gate

Outputs 1 when inputs are different. (Exclusive OR)

SR block diagram

SR flip flop

Dont Care Condition

Situation when a circuit's output level for a given set of input conditions can be assigned as either a 1 or 0.

Arithmetic Unit

Some example of Arithmetic Operations: •Addition - add two binary numbers •Subtraction - subtract a binary number from another •Increment - add 1 to a bit •Decrement- subtract 1 from a bit

CPU Basics1

The computer's CPU fetches, decodes, and executes program instructions.

Combinational Circuit

The input values explicitly determine the output

What is the difference between combinational circuits and sequential circuits

The output of a combinational circuit depends only on the current input values, while the output of a sequential circuit depends on both the current input values and the previous state of the circuit.

Boolean Operator: NOT

True if not 1

Boolean Operators: AND

Will contain both of the items

NAND Gates

a combination of NOT and AND gates. They are negative gates and the results of the NAND gate are opposite the AND gate. (If either or both inputs are 1, then the output is 0. If the inputs are both 1, then the output is 0.

Karnaugh Maps (Kmaps)

a matrix consisting of rows and columns that represent the output values of a Boolean function under different inputs.

Control Unit (CU)

determines which actions to carry out according to the values in a program counter register and a status register.

Mod 7 Counter

known as divide-by-7 counter can count from 0 to 6, and on the count of seven, it automatically resets to begin the count again.

Propagation delay

the time taken for the output to change after the input has changed. •Example: flip-flop may take 1ns to get the stable output based on current input. So, propagation delay is 1ns.

Point to point vs Multipoint Bus

•A bus can be point to point connecting two specific components. •Multipoint bus on other hand connects multiple devices.

Arithmetic Logic Unit (ALU)1

•ALU is a complex digital circuit with an AU (arithmetic unit) and a LU (logic unit). •The computer central processing unit ALU performs both bitwise and mathematical operations on binary numbers and is the last component to perform calculations in the processor.

What are some example of Arithmetic Operations:

•Addition - add two binary numbers •Subtraction - subtract a binary number from another •Increment - add 1 to a bit •Decrement- subtract 1 from a bit

Bus System2

•At any one time, only one device (be it a register, the ALU, memory or some other component) may use the bus. •However, this sharing often results in a communication bottleneck. •The speed of the bus is affected by its length as well as by the number of devices sharing it. 1. Type of bus system: •Point to point bus •Multipoint bus

Buses1

•Buses are simply groups of wires that acts a shared data path to connect multiple devices within a computer system.

Bus System1

•Buses consist of data lines, control lines, and address lines. • •While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the bus. • •Address lines determine the location of the source or destination of the data.

Basic Concept: Clock

•Clock is used by a sequential circuit to decide when to update the state of the circuit (i.e. when do present input becomes past inputs?). •State changes occur in sequential circuits only when the clock ticks. •Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.

1.3 Clocks

•Clock speed should not be confused with CPU performance. •The CPU time required to run a program is given by the general performance equation: • • •We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock cycle.

Half Adder

•Combinational Circuit that find the sum of two bits. •As we see, the sum can be found using the XOR operation and the carry using the AND operation.

System Bus2

•Data bus: •Holds the data that the processer is working on. • •Address bus: •It holds the address of the memory where the data is stored. • •Control bus: •It monitors the data in data bus and address bus.

Adders

•Essential part of every CPU •Half adder (Ignores the carry-in bit) •It performs the addition of two bits •Full adder •It takes 3 bits input •Carry is one of the input

Clocks

•Every computer contains at least one clock that synchronizes the activities of its components. • •A fixed number of clock cycles are required to carry out each data movement or computational operation. • •The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. • •Clock cycle time is the reciprocal of clock frequency. •An 800 MHz clock has a cycle time of 1.25 ns.

Clock3

•Generally, when we mention clock, we are referring to the system clock that regulates the CPU and other components. • •However, certain buses also have their own clocks. • •Bus clocks are usually slower than CPU clocks. • •System components have defined performance bounds, indicating the maximum time required for the components to perform their functions. • •Manufacturers guarantee that their components will run within these bounds in the most extreme circumstances.

Data Bus

•Holds the data that the processer is working on. •Connects CPU, Memory and I/O devices •It consists of 8,16, 32, 64, 128 or more separate lines. •The number of lines is referred as width of data bus. •Each line can hold 1 bit of data. • •Width is a key determinant of performance. •What if the data bus is 8 bits wide but instructions are 16 bits long? •What if the data bus is 64 bits wide but instruction are 16 bits long?

HOI vs LOI

•In HOI, the most significant bits of the address select the memory chip. •The least significant bits are sent as addresses to each chip. •In HOI, Consecutive addresses tend to be in the same chip. The maximum rate of data transfer is limited by the memory cycle time.

HOI vs LOI one

•In LOI, the least significant bits select the module. •In LOI, consecutive memory addresses are in different memory modules. •This allows parallel memory access at much faster rates.

Memory Interleaving

•In high-order interleaving the high-order 4 bits select the chip. •In low-order interleaving the low-order 4 bits select the chip.

Clock2

•It is important to note that the architecture of a machine has a large effect on its performance. • •Two machines with the same clock speed do not necessarily execute instructions in the same number of clock cycles. • •For example, a multiply operation on an older Intel 286 machine requires 20 clock cycles, but on a new Pentium, a multiply can be done in 1 clock cycle.

Clock1

•It must be reasonable to assume that if we speed up the clock the machine will run faster. • •However, there are limits on how short we can make the clock cycles. • •The minimum clock cycle time must be at least as great as the maximum propagation delay of the circuit.

Memory2

•Memory is constructed of RAM chips, often referred to in terms of length x width (L x W). •If the memory word size of the machine is 16 bits, then a 4M x 16 RAM chip gives us 4 Megabytes of 16-bit memory locations

Overclocking

•Overclocking is the action of increasing a component's clock rate, running it at a higher speed than it was designed to run. • •Overclocking can produce additional heat. •Ensure your system has proper cooling • •Overclocking the system bus can provide considerable performance improvements but can also damage the components that use the bus or cause them to perform unreliably. • •Modern CPUs are very fast. Now, we don't have to rely on overclocking to get performance boost.

1.5 Memory1

•Physical memory usually consists of more than one RAM chip. • •Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips. • •With low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest. • •Accordingly, in high-order interleaving, the high order address bits specify the memory bank.

What are the advantages of using these shared data path or buses?

•Reduces the number of pathways needed for communication between the components, by carrying out all communications over a single data channel. •High speed transfer. •Provides synchronization between components.

Shifter

•SHR -> shifts the contents (bits) of the register in right direction •SHL -> shifts the contents (bits) of the register in left direction

Kmap Simplication Stage 1

•Stage 1: grouping stage rules of simplification are: 1.Groupings can contain only 1s; no 0s. 2.Groups can be formed only at right angles; diagonal groups are not allowed. 3.The number of 1s in a group must be a power of 2 - even if it contains a single 1. 4.The groups must be made as large as possible. 5.Groups can overlap and wrap around the sides of the Kmap.

Kmap Simplication Stage 2

•Stage 2: Generate function using group: (Rules) •After you have found all the groups, examine each group and discard the variable that differs within each group. •Apply logical OR to each term from different groups.

Bus Data Transfer Protocol

•Synchronous: •Used a clock to enforce timing • • •Asynchronous: •Use handshaking protocol to enforce timing • • •Synchronous is easier to implement, but asynchronous scales and performs better with a great variety of devices.

Rules of Precedence

•The NOT operator has highest priority. •AND has next highest priority. •Finally, OR.

The two principal parts of the CPU are the datapath and the control unit.

•The datapath consists of an arithmetic-logic unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory. •Various CPU components perform sequenced operations according to signals provided by its control unit.

Logic Unit

•The logic unit performs logical operations (e.g., AND, OR, and NOT), negation, and numeric tests like checking if a number is a negative number.

Canonical Form

•There are two canonical forms for Boolean expressions: sum-of-products and product-of-sums. •Recall the Boolean product is the AND operation and the Boolean sum is the OR operation.

Feedback

•To remember a past state, , sequential circuits rely on a concept called feedback. •Feedback in digital circuits occurs when an output is looped back to the input. •A simple example of feedback is shown below. If Q is 0 it will always be 0, if it is 1, it will always be 1.

Synchronous Bus

•Used a clock to enforce timing •Instructions are carried out after the tick of the clock.

Memory1

•We can envision memory as a matrix of bits. •Each row implemented by a register, has a length typically equivalent to the addressable unit size of the machine. •Each register (memory location) has a unique address, memory address usually start at zero and progress upward. •Normally, memory is byte addressable, which means that each individual byte have a unique address.

•What is the advantage of using decoder for logic implementation?

•We use decoder as an Integrated circuit. Hence, the space is reduced by reducing the number of wires and gates. It also reduces the cost to build a circuit

Decoder

•a combinational circuit that has n input lines and maximum of 2n output lines.

Decoder1

•a combinational circuit that has n input lines and maximum of 2n output lines. •Only one output line will be active (has 1) for a corresponding binary number represented by inputs. •They are useful in selecting a memory location according to a binary value placed on the address lines of a memory bus. •Address decoders with n inputs can select any of 2n locations. •It can also be used for logic impelementation.

Sequential Circuits

•a combinational circuit with memory. •In sequential circuits, the present output depends on the present inputs and present state (past output).

Arithmetic Logic Unit (ALU)

•carries out logical and arithmetic operations as directed by the control unit.

Level-tiggered circuits (latch)

•change state when the clock voltage reaches its highest or lowest level. (aka latch)

Boolean Algebra

•mathematical system for the manipulation of variables that can have one of two values.