Digital Logic Design
Flip-flop latch
A latch that stores a new bit only at the instant of clock input'ss rising edge
SR Latch
A latch that stores one bit, with an input s to set the latch to 1, an input r to reset the latch to 0, and with the stored bit appearing on output q. S and s are for "set"l and R and r for "reset".
Level-sensitive latch
A latch that stores only when the enable's "level" is high
DeMorgan's Law
A law of logic that is used to simplify conditions in which ! (not) operators are applied to AND + OR expressions. AND switches to OR and OR switches AND. When you invert an OR --> the AND of the complements. (a+b)' = a'b' When you invert an AND --> the OR of the complements. (ab)' = a' + b'
Select Lines
A mux's control inputs
Minterm
A product term in a Boolean expression where all possible variables appear once in true or complement form.
Function
A relation of input values to output values. Can be represented in various ways: equation, table, circuit, etc. A function may have more than one input, but has only one output.
Controller
A sequential circuit consisting of a register and combinational logic
electronically-controlled switch
A switch that has another input terminal whose voltage can turn the switch on.
NAND
A universal gate. Operates as an AND gate followed by a NOT gate; the output is false if both inputs are true; otherwise the output is true.
NOR
A universal gate. The opposite of an OR gate.
Logic Operators
AND, OR, and NOT
Product Term
Aan ANDing of (one or more) variables, like ab'c.
Minimal Cover
An expression for the function, having the fewest terms, each with the fewest literals. On a K-map, a minimal cover is a cover using the fewest, largest, circles, and the largest circles are PIs.
Prime Implicant
An implicant that cannot have a literal removed without becoming a non-implicant. In a k-map, it is each LARGEST possible valid circle.
Clock signal
An oscillating signal used to control when to store bits. Oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits.
What are the different ways of describing a function?
As English: When inputs a, b are both 1's, the output y is 1. Else, y is 0. As an equation: y = ab As a truth table. As a circuit, as a drawing, a K-map (introduced later), etc.
Edge-triggered
Certain FFs that require a change in the clock signal as a condition for switching states
D latch
Circuit that stores one bit, with an input d having the bit to be stored, an input e that when 1 enables storing the bit, and with the stored bit appearing on output q.
Convert from binary to decimal: 0001
Convert from decimal to binary: 1
Convert from binary to decimal: 1101
Convert from decimal to binary: 13
Analysis
Converting a circuit to behavior (like an equation)
Design
Converting an equation to a circuit.
Equation
Has an =, with expressions of input variables on the right, and an output variable on the left. (e.g. y = ab)
For a 16x4 encoder, what is the output if only input d5 is 1?
Input d5 is 1 and no other input is 1, so the output is the binary value for 5, or e3e2e1e0 = 0101.
How are k-maps useful?
It is a graphical method to help us find opportunities to combine terms. Otherwise, it is easy to miss "seeing" possible opportunities to combine terms.
Expression
Lacks an equal sign, and involves input variables. (e.g. ab)
Shorthand: a'
NOT(a)
Mealy FSM
Output value is a function of current state AND current input values
Moore FSM
Output value is a function of current state only
XNOR
Outputs 1 if that input values are equal/are even (in the case of > 2 inputs)
Canonical form
Standard equation form for a function
On-set
The set of midterms that define when the function is 1
What does it mean when a term "covers" a midterm?
The term evaluates to 1 whenever the midterm does. E.g. term ab for minters abc, as well as abc'.
Clock cycle
The time between two rising edges (the clock period)
Two equations with the same sum-of-minterms represent the same function (T/F).
True
How do you convert an FSM to a controller?
Use a state register to store the present state and combinational logic to compute outpus and the next state. 1. Capture the FSM 2. Create the architecture by using a state register of appropriate width and combinational logic with inputs being the state register bits and the FSM inputs and outputs being the next state bits and FSM outputs. 3. Encode the states (assign a unique binary number to each state) 4. Create the state/truth table for the combinational logic such that the logic will generate the correct FSM outputs and next state signals. 5. Implement the combinational logic using any method.
State Reduction with Partitioning Method
Use the partitioning method. 1. Group states per output values 2. Add a column for inputs for each state 3. List next states and their groups based on the transition conditions. (e.g. if b=1 --> state T) 4. List the next state group for each state+input. 5. If the next state's group differs they cannot be equivalent. 6. Split group per next states' groups. Update next states' groups
Identity (OR)
a + 0 = a
Complement (OR) Property
a + a' = 1
XOR
outputs 1 if the input values differ/are odd (in the case of > 2 inputs)
Even Parity Bit
the eighth bit, aka the parity bit, is set to 1 if the number of 1's in the data bits is odd, which would make the number of 1's in the 8 bit byte an even number. It is set to 0 if the number of 1's in the data is even. Ex: 1111 100 → the 8th bit would be 1 because it needs to be an even parity bit and there are an odd number of 1's
Involution
(a')' = a
Associative Property
(ab)c = a(bc)
Finite State Machine (FSM)
A computation model capable of describing sequential behavior. The model consists of inputs, outputs, states, state actions, transitions, and an initial state. Generates an output as processing takes place.
Timing diagram
A diagram that graphically shows a circuit's output values for given input values that change over time. Each signal (input or output) name is listed on the left. Time proceeds to the right. Each signal is drawn as a high line (1) or a low line (0).
D Flip-Flop
A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs
Sum-of-products
A form of logical representation that employs a logical sum (OR) of products (terms joined using the AND operator)
How can you convert a truth table to an equation?
A function captured as a truth table can be transformed to a sum-of-minterms equation by summing the minterms in rows having a 1
For a D latch, what is q's present value given: d: 0..0..1 e: 1..0..0
0
For a D latch, what is q's present value given: d: 0..0..1..1..0 e: 1..0..0..1..0
1
What is the common process for simplifying a sum-of-products expression?
1. Convert to sum-of-minterms 2. Seek i(j+j') opportunities
How can you create a minimal cover?
1. Generate PIs: Find all PI's by drawing all largest possible circles 2. Add essential PIs: Find any essential PIs and add them to the function's cover. 3. Cover remaining: Select PI's to cover any 1's not covered by the essential PI's.
If each AND or OR gate input requires two transistors, how many transistors does the circuit r = abc' + ab'c' (unsimplified) require? Ignore NOT gates.
16 The two AND gates have 6 inputs total (one per literal). The OR gate as 2 inputs (one per term). The total AND/OR inputs is 6 + 2 = 8. However, each input requires two transistors, so the total transistors is 8 * 2 = 16.
How many bits are required to store 4 states in a state register?
2 bits (00, 01, 10, 11)
D flip-flop: Master-servant implementation
A D flip-flop built as a first D latch whose output q is the input d of a second D latch. A clock input connects to the e input of each, inverted for the first.
Sum-of-minterms form
A canonical form of a Boolean equation where the right-side expression is a sum-of-products with each product a unique minterm
Register
A circuit that stores a groups of bits. On a rising clock edge, all bits are stored simultaneously
Sequential Circuit
A circuit whose output is a function of its input values and the current state of the circuit. A circuit whose output values may depend on the past sequence of input values, and not just the present input values
Combinational Circuit
A circuit whose output is solely determined by its input values
Priority encoder
A combinational circuit that outputs the binary value for the highest priority input that is 1, where a higher numbered inputs has higher priority Assumes that at least one input is 1, but more than one input can be 1. When multiple inputs are one, the binary value for the highest priority input will be output. Ex: If the input is d3d2d1d0 = 1010, d3 has priority over d1, so the output is e1e0 = 11.
Incompletely specified function
A function that does not define an output value for every input combination. Ex: A 3-position knob may set 2 inputs to 00, 01, or 10. Combination 11 is not possible and thus f is not specified for that combination.
K-map (Karnaugh Map)
A graphical function representation that eases the simplification process for expressions involving a few variables, by adjacently placing minterms that differ in exactly one variable. It lays out possible minterms as adjacent cells (boxes). Adjacent minterm cells differ by exactly one variable. Each function minterm cell gets a 1; other cells get 0. Can also be considered a reoriented truth table.
Oscillator
A special device that generates a clock at a specific frequency
maxterm
A sum term in a Boolean expression where all possible variables appear once in true or complement form. (e.g. a+b when only a and b are the variables)
How can you convert a sum-of-products equation into a sum-of-minterms equation?
A sum-of-products equation can be transformed to sum-of-minterms by multiplying each product term by (v + v') for any missing variable v to create minterm (removing redundant minterms) 1. Initially multiplying out to sum-of-products 2. Transform each product term to a minterm 3. Remove redundant minterms
Implicant
A term that covers only midterms in the function's on-set. Represented in a k-map by each valid circle (not necessarily the largest).
How can a SR latch be implemented?
An SR latch can be designed with two cross-coupled NOR gates (the output of each is an input to the other), with s input to top gate and r input to the bottom (whose output is q).
Carry-Ripple Adder
An adder that mimics adding by hand, adding a digit's pair of bits and carry-in bit, and generating a sum and carry-out bit.
Boolean algebra
An algebra whose only values are true or false, and whose operators are AND, OR, and NOT.
Quine-McCluskey
An algorithm for two-level logic optimization, suitable for computer automation due to using a tabular method (rather than a graphical method like K-maps). Given.a function's midterms, the steps are: 1. Generate PI's: Create a table of midterms, then pairwise check midterms for i(j + j') opportunities, combining into new terms in a new column, repeating with new terms until no more combinations can be made. Each term that wasn't combined with another (midterms or new terms) is a prime implicant (PI). 2. Find Essentials: Draw a table with PI's as rows and midterms as columns, putting a mark to indicate that a PI covers a midterm. For any column with only one mark, the PI for that row is essential so is added to the cover. All midterms covered by that PI are also checked off as covered. 3. Cover Remaining: Select minimal unadded prime implicants to cover remaining midterms.
Boolean equation
An equation that expresses a boolean output in terms of boolean inputs to which one or more Boolean functions, such as OR, AND and NOT, are applied. Can describe a digital circuit, with the output on the left and the inputs on the right.
What is the relationship between a function's minimal cover and prime implicants?
Defining prime implicants is useful because each term in a minimum cover MUST be a prime implicant, otherwise the cover is not minimal.
Idempotent
Duplicate values can be removed. a · a = a a + a = a
Latch
Stores a new bit while an enable input is 1
Compact Function Notation
Represents each minterm in a sum-of-minterms equation by a number. e.g. f(a,bc) = m3 + m7
Null elements
Result doesn't depend on the value of a. a · 0 = 0 a + 1 = 1
Distributive (AND) Property
Same as multiplication in regular algebra a(b + c) = ab + ac
Equivalent state
States that have the: - Same output - Same next state - Same input values
Essential Prime Implicant
The only prime implicant to cover a particular midterm in a function's on-set. On a K-map, an essential PI is a largest circle that is the only circle to cover a particular 1.
State register
The register in a controller, holding an FSM's present state. Each state requires a unique bit encoding which is then stored in the state register.
Latch
The simplest circuit for storing a bit
Distributive (OR) Property
Variable order does not matter. a + (bc) = (a + b)(a + c)
Shorthand: ab
a AND b
Shorthand: a + b
a OR b
Encoder
a combinational circuit that converts 1 of N inputs to a binary value using log(N) outputs
Decoder
a combinational circuit that converts N inputs to a 1 on one of 2^N outputs
Multiplexor (aka Mux)
a combinational circuit that passes one of multiple data inputs through to a single output, selecting which one based on additional control inputs
logic gate (or just gate)
a transistor circuit that implements a logic function
Literal
a variable appearance, in true or complemented form, in an expression, such as b, or b'.
Identity (AND)
a · 1 = a
Complement (AND) Property
aa' = 0
Commutative Property
ab = ba a + b = b + a
sum term
an ORing of (one or more) variables, like (a + b' + c'). A sum term is sometimes called just a term
Adder
computes A + B, where A and B are N-bit numbers, such as 8-bit numbers
Clock frequency
cycles per second of a clock, in units of hertz (Hz) meaning cycles/second
Given f(a, b, c) = a'bc + abc, the compact notation is?
f(a, b, c) = m3 + m7
If a mix has n inputs, how many select lines are needed?
log2n
Minterm Number of ab'c = ?
m5
Minterm Number of abc'
m6
Minterm Number of abc = ?
m7
Product-of-sums form
n expression in product-of-sums (POS) form consists solely of an ANDing of sum terms, like (a + b' + c)(a + b).
