Digital Logic Final Exam Review General Q's

Ch5: Applying DeMorgans theorem to the expression /(ABC) we get _____. A. /A+/B+/C B. /(A+B+C) C. A+/B+C/C D. A(B+C)

A. /A+/B+/C

CH7: The most commonly used system for representing signed binary numbers is the: A. 2's complement system. B. 1's complement system. C. 10's complement system. D. Sign-magnitude system.

A. 2's complement system

CH7: How many basic binary subtraction operations are possible? A. 4 B. 3 C. 2 D. 1

A. 4

CH8: How many inputs are required for a 1 of 10 BCD decoder? A. 4 B. 8 C. 10 D. 1

A. 4

CH1: How many binary digits are required to count to 100 (base 10)? A. 7 B. 2 C. 3 D. 100

A. 7

CH7: What is the most important operation in binary-coded decimal (BCD) arithmetic? A. Addition B. Subtraction C. Multiplication D. Division

A. Addition

CH6: Which type of gate can be used to add two bits? A. Ex-OR B. Ex-NOR C. Ex-NAND D. NOR

A. Ex-OR

CH7: What are constants in VHDL code? A. Fixed numbers represented by a name B. Fixed variables used in functions C. Fixed number types D. Constants do not exist in VHDL code.

A. Fixed numbers represented by a name

CH1: A binary number's value changes most drastically when the --- is changed. A. MSB B. Frequency C. LSB D. Duty Cycle

A. MSB

CH10: Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? A. The logic level at the D input is transferred to Q on NGT of CLK. B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. C. The Q output is ALWAYS identical to the D input when CLK = PGT. D. The Q output is ALWAYS identical to the D input.

A. The logic level at the D input is transferred to Q on NGT of CLK.

CH10: Propagation delay time, tPLH, is measured from the ________. A. Triggering edge of the clock pulse to the LOW-to-HIGH transition of the output B. Triggering edge of the clock pulse to the HIGH-to-LOW transition of the output C. Preset input to the LOW-to-HIGH transition of the output D. Clear input to the HIGH-to-LOW transition of the output

A. Triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

CH5: The systematic reduction of logic circuits is accomplished by: A. Using Boolean algebra B. Symbolic reduction C. TTL logic D. Using a truth table.

A. Using Boolean algebra

CH6: A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n): A. XNOR B. OR C. XOR D. NAND

A. XNOR

CH5: One of DeMorgan's theorems states that /(X+Y) = /X/Y, this means that logically there is no difference between: A. a NOR and an AND gate with inverted inputs B. A NAND and an OR gate with inverted inputs C. An AND and a NOR gate with inverted inputs D. A NOR and a NAND gate with inverted inputs

A. a NOR and an AND gate with inverted inputs

CH10: Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. A. 10.24 kHz B. 5 kHz C. 30.24 kHz D. 15 kHz

B. 5kHz

CH8: The expansion inputs to a comparator are used for expansion to a(n): A. 4 Bit system B. 8 Bit system C. BCD system D. Counter system

B. 8 Bit system

Ch5: Determine the values of A, B, C, and D that make the sum term /A+B+/C+D equal to 0. A. A=1, B=0, C=0, D=0 B. A=1, B=0, C=1, D=0 C. A=0, B=1, C=0, D=0 D. A=1, B=0, C=1, D=1

B. A=1, B=0, C=1, D=0

CH1: Which is the most widely used alphanumeric code or computer input and output? A. Gray. B. ASCII C. Parity D. EBCDIC

B. ASCII

CH6: The Ex-NOR is sometimes called the ____. A. Parity gate B. Equality gate C. Inverted OR D. Parity gate or the equality gate

B. Equality gate

CH7: What are the two types of basic adder circuits? A. Sum and carry B. Half-adder and full-adder C. Asynchronous and synchronous D. One- and two's-complement

B. Half-adder and full-adder

CH1: One HEX digit is referred to as? A. Byte B. Nibble C. Grouping D. Instruction

B. Nibble

CH6: Parity systems are defined as either_____ or _____ and will add an extra _____ to the digital information being transmitted. A. Positive, negative, byte B. Odd, even, bit C. Upper, lower, digit D. On, off, decimal

B. Odd, even, bit

CH6: How is odd parity generated differently from even parity? A. The first output is inverted. B. The last output is inverted.

B. The last output is inverted.

CH10: On a master-slave flip-flop, when is the master enabled? A. When the gate is LOW B. When the gate is HIGH C. Both of the above D. Neither of the above

B. When the gate is HIGH

CH7: The range of positive numbers when using an eight-bit two's-complement system is: A. 0 to 64 B. 0 to 100 C. 0 to 127 D. 0 to 256

C. 0 to 127

CH1: If a typical PC uses a 20 bit address code, how much memory can the CPU address? A. 20 MB B. 10 MB C. 1 MB D. 580 MB

C. 1 MB

CH8: How many inputs will a decimal to BCD encoder have? A. 4 B. 8 C. 10 D. 16

C. 10

CH1: Hexadecimal letters A through F are used for decimal equivalent values from: A. 1 to 6 B. 9 to 14 C. 10 to 15 D. 11 to 17

C. 10 to 15

CH5: For the SOP expression A/BC+/ABC+AB/C, how many 1s are in the truth table's output column? A. 1 B. 2 C. 3 D. 5

C. 3

CH12: How many flip-flops are required to make a MOD-32 binary counter? A. 3 B. 45 C. 5 D. 6

C. 5

CH1: How many bits are in an ASCII character? A. 16 B. 8 C. 7 D. 4

C. 7

CH8: How many exclusive-NOR gates would be required for an 8-bit comparator circuit? A. 4 B. 6 C. 8 D. 10

C. 8

CH7: What is the major difference between half-adders and full-adders? A. Nothing basically; full-adders are made up of two half-adders. B. Full adders can handle double-digit numbers. C. Full adders have a carry input capability. D. Half adders can handle only single-digit numbers.

C. Full adders have a carry input capability.

CH10: How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs? A. It can't be done. B. Invert the Q outputs. C. Invert the S-R inputs.

C. Invert the S-R inputs.

CH7: One way to make a four-bit adder perform subtraction is by: A. Inverting the output. B. Inverting the carry-in. C. Inverting the B inputs. D. Grounding the B inputs.

C. Inverting the B inputs.

CH5: An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)________ gate. A. NOT B. OR C. NOR D. NAND

C. NOR

CH8: A basic multiplexer principle can be demonstrated through the use of a: A. Single Pole relay B. DPDT switch C. Rotary switch D. Linear stepper

C. Rotary switch

CH10: With regard to a D latch, ________. A. The Q output follows the D input when EN is LOW B. The Q output is opposite the D input when EN is LOW C. The Q output follows the D input when EN is HIGH D. The Q output is HIGH regardless of EN's input state

C. The Q output follows the D input when EN is HIGH

CH6: Why is an exclusive-NOR gate also called an equality gate? A. The output is false if the inputs are equal. B. The output is true if the inputs are opposite. C. The output is true if the inputs are equal.

C. The output is true is the inputs are equal.

CH8: What is the function of an enable input on a multiplexer chip? A. To apply Vcc B. To connect ground C. To activate the entire chip D. To activate one half of the chip

C. To activate the entire chip

CH6: A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n): A. XNOR B. OR C. XOR D. NAND

C. XOR

CH6: Identify the type of gate below from the equation X=A(+) B = /AB+A/B A. XNOR B. OR C. XOR D. NAND

C. XOR

CH8: How many outputs are on a BCD decoder? A. 4 B. 16 C. 8 D. 10

D. 10

CH5: How many gates would be required to implement the following Boolean expression before simplification? XY+X(X+Z)+Y(X+Z) A. 1 B. 2 C. 4 D. 5

D. 5

CH10: How many flip-flops are required to produce a divide-by-128 device? A. 1 B. 4 C. 6 D. 7

D. 7

CH5: A truth table for the SOP expression AB/C+A/BC+/A/BC, has how many input combinations? A. 1 B. 2 C. 4 D. 8

D. 8

CH5: Which of the following expressions is in the sum-of-products (SOP) form? A. (A+B)(C+D) B. (A)B(CD) C. AB(CD) D. AB+CD

D. AB+CD

CH8: A principle regarding most IC decoders is that when the correct input is present, the related output will switch: A. Active-HIGH B. To a high impedance C. To an open D. Active-LOW

D. Active-LOW

CH1: What is the difference between binary coding and binary-coded decimal? A. BCD is pure binary B. Binary coding has a decimal format C. BCD has no decimal format D. Binary coding is pure binary

D. Binary coding is pure binary

CH8: Which digital system translates coded characters into a more useful form? A. Encoder B. Display C. Counter D. Decoder

D. Decoder

CH10: A J-K flip-flop is in a "no change" condition when ________. A. J = 1, K = 1 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 0, K = 0

D. J = 0, K = 0

CH10: How is a J-K flip-flop made to toggle? A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1

D. J = 1, K = 1

CH10: Which of the following is correct for a gated D flip-flop? A. The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D. Q output follows the input D when the enable is HIGH.

D. Q output follows the input D when the enable is HIGH.

CH1: The octal numbering system: A. Simplifies tasks B. Groups binary numbers in 4's C. Saves Time D. Simplifies tasks and save time

D. Simplify tasks and save time

CH5: Which output expression might indicate a product-of-sums circuit construction? A. X=/(CH)(D+E+F) B. X=CG(DE) C. X=/(AC+BD+EF) D. X=(C+D)(E+G)

D. X=(C+D)(E+G)

CH5: The commulative law of Boolean addition states that A+B=AB.

False

CH8: What does IC stand for?

Integrated Circuit