DSII Exam 3
If the propagate function p = '1' then the carry-out value will be '1' if: The carry-in value is '1'. The carry-in value is '0'.
'1'
In the SSRM discussed in class the M-Reg stores the value . of the original Multiplicand. ... of the original Multiplier.
... of the original Multiplicand.
In the SSRM discussed in class, PH-Reg is intitialized to 0. Multiplier value. Final Product (FP) High value. Multiplicand value.
0
How many gate-level propagation delays does it take to compute the sum bit of a stage in a RCA or CLA from the moment the cin to that stage is available? 1 3 4 2
1
How many gate-level propagation delays are in a generic Sum-Of-Products (SOP)? 1 4 3 2
2
In each PSRM stage the PP is generated using .. ... 2-input AND gates. ... 2-to-1Muxes.
2 input and gate
In the SSRM described in class a new PP is generated using . 2-input AND gates. ... 2to1-Muxes.
2 to 1 muxes
The perceptron below implements which binary function:
2-input NAND.
How many different data sets can the PSRM described in class process concurrently?
4
What is a practical limit for the number of inputs to a (static) CMOS gate? 4 16 8 unlimited.
4
Comparing a n-bit CLA to a n-bit RCA: The CLA is slower and uses less hardware resources. The CLA is faster, but uses significant more hardware resources.
CLA is faster
At the cost of additional and acceptable propagation delay, the second-level carry-look-ahead reuses computation results in the form of: gi and pi. Gj and Pj.
Gj and Pj
In a binary multiplication, which bits of the final product are calculated first? The LSbits. The MSbits.
LSBits
Compared to a RCA, a CLA uses: More hardware resources. Less hardware resources.
More
Why is the external user control input START necessary? So that the SSRM knows when a new set of input operands is valid and ready to be multiplied. So that the SSRM knows when to stop the add-shift sequence.
So that the SSRM knows when a new set of input operands is valid and ready to be multiplied
When is the value of the PP zero? When the associated multiplier bit is 0. When the associated multiplier bit is 1.
When the associated multiplier bit is 0.
In each stage of the PSRM which operations are executed during every machine cycle? add and shift right. ONLY shift right. ONLY add. subtract and shift right.
add and shift right
In the SSRM discussed in class, which sequence of operations are repeated? Sub-shift-right. Sub-shift-left. Add - shift-left. Add - shift-right.
add shift right
Which is more important in BNNs as well as in ANNs? The complexity (sophistication) of connections between neurons. OR The total number of neurons.
complexity
The sNN is designed following: the computer design methodology. OR the FSM design methodology.
computer design methodology
Assuming enough resources (2-input AND gates) are available, ALL partial products (PPs) are calculated .. ... sequentially. ... concurrently.
concurrently
In the lecture SSRM ASM Chart we initialized n = 4 and counted down to 0. If we would initialize n = 0, we would need to ... ... count up to 4. ... count up to 8.
count up to 4
The behavioral description of the SSRM CU uses if-else and/or case constructs. Which of the following is NOT used in the condition evaluations of these constructs? START DONE MC n
done
If the Multiplicand is n-bits wide and the multiplier is m-bits wide, how many times is the add-shift sequence repeated in the SSRM? m+n n 4 m
m
The generate function indicates that a carry-out of '1' will be generated by the stage: Only if the carry-in value is '1'. OR No matter what the carry-in value is.
no matter what the carry value is
What is the RCAs biggest performance problem? The 3-input XOR needed to generate the sum bit in each stage. OR The propagation of the carry values from one stage to the next.
propagation of carry values
The most time consuming operation in a binary multiplication is ... the multi-operand addition of the PPs. ... the generation of the PPs.
the multi-operand addition of the PPs.
In the SSRM mPL-Reg is used to store ... .. the remaining bits of the multiplier and the incoming MSbits of the FP. ... the remaining bits of the multiplier and the incoming LSbits of the FP.
the remaining bits of the multiplier and the incoming LSbits of the FP.
the PSRM improves .. latency. ... throughput.
throughput
Binary multiplication can be implemented in custom hardware (HW) or software (SW).
true
In an attempt to tradeoff cost/performance we can combine carry look-ahead and ripple-carry in the same adder unit. True False
true
The Perceptron weighs input evidence.
true
The sigmoid neuron weighs input evidence.
true
on avg division takes longer than multiplication
true
