Operating Systems, Chapter 9-10 Questions
How do you find a physical address given a logical address with segmentation?
1) Get the base address 2) Check that the offset is less than the length 3) Add the the offset to the base address
Rank the following page-replacement algorithms: LRU, FIFO, Optimal, and Second-chance.
1. Optimal 2. LRU 3. Second-chance 4. FIFO
Thrashing
A condition of excessive paging in which the operating system becomes sluggish. Occurs with the size of locality is greater than the total memory size.
Under what circumstances do page faults occur? Describe the actions taken by the operating system when a page fault occurs.
A page fault occurs when an access to a page that has not been brought into main memory takes place. The operating system verifies the memory access, aborting the program if it is invalid. If it is valid, a free frame is located and I/O is requested to read the needed page into the free frame. Upon completion of I/O, the process table and page table are updated and the instruction is restarted.
Consider a paging system with the page table stored in memory. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take?
A paged memory reference requires 2 memory accesses: one to get the frame number for the page number from memory and actually accessing the data. So if a memory reference takes 200 nanoseconds then a paged memory reference will take 400 nanoseconds.
How could the operating system allow access to other memory? What is the use of doing that?
Swap out a page from PT and load into the frame you want to access. This is useful for when two or more processes need to exchange data - they just read and write to the same physical addresses (which may be varying logical addresses). This makes for very efficient interprocess communication.
When virtual memory is implemented in a computing system, there are certain costs associated with the technique and certain benefits. List the costs and the benefits. Is it possible for the costs to exceed the benefits? If it is, what measures can be taken to ensure that this does not happen?
The costs are additional hardware and slower access time. The benefits are good utilization of memory and larger logical address space than physical address space.
What is the effect of allowing two entries in a page table to point to the same page frame in memory? Explain how you could use this effect to decrease the amount of time needed to copy a large amount of memory from one place to another. What would the effect of updating some byte in the one page be on the other page?
The effect is that two pages in a single process refer to the same physical page. Hence, if you change a byte at one address, a byte at the same offset in the other page will change. This can be used to perform copies quickly by mapping a page read-only at two addresses. If it is modified, then the copy can be done later(if at all)
We have an operating system for a machine that uses based and limit registers, but we have modified the machine to provide a page table. Can we set up the page tables to simulate based and limit registers?
The page table can be set up to simulate base and limit registers provided that the memory is allocated in fix-sized segments. In this way, the base of a segment can be entered into the page table and the valid/invalid bit used to indicate that portion of the segment as resident in the memory. There will be some problem with internal fragmentation however
A certain computer provides its users with a virtual-memory space of 2^32 bytes. The computer has 2^18 bytes of physical memory. The virtual memory is implemented by paging, and the page size is 4096 bytes. A user process generates the virtual address 11123456. Explain how the system establishes the corresponding physical location.
The virtual address in binary form is 0001 0001 0001 0010 0011 0100 0101 0110. Since the page size is 2^12, the page table size is 2^20. Therefore the low order 12 bits 0100 0101 0110 are used as the displacement into the page, while the remaining 20 bits 0001 0001 0001 0010 0011 are used as the displacement in the page table. The offset bits are then concatenated to the resulting physical page number (from the page table), to form the final address.
Why is it that, on a system with paging, a process cannot access memory that it does not own? How could the operating system allow access to other memory? What is the use of doing that?
There is no way for a process to refer to a page it does not own because the page will not be in the page table. To allow such access an operating system simply needs to allow entries for non-process memory to be added to the process page table. This is useful for when two or more processes need to exchange data - they just read and write to the same physical addresses (which may be varying logical addresses). This makes for very efficient interprocess communication.
What is the cause of thrashing? How does the system detect thrashing? Once it detects thrashing, what can the system do to eliminate this problem?
Thrashing is caused by under-allocation of the minimum number of pages require by a process, forcing it to continuously page fault. The system can detect thrashing by evaluating the level of CPU utilization as compared to the level of multi-programming. It can be eliminated by reducing the level of multi-programming.
When a process is rolled out of memory, it loses its ability to use the CPU (at least for a while). Describe another situation where a process loses its ability to use the CPU, but where the process does not get rolled out.
When an interrupt occurs the processes loses the CPU, but regains it as soon as the handler completes. The process never rolls out of memory.
Why is it that, on a system with paging, a process cannot access memory that it does not own?
You can only access the pages that are in your page table.
Suppose that you want to use a paging algorithm that requires a reference bit (such as second-chance replacement or working-set model), but the hardware does not provide one. Sketch how you could simulate a reference bit even if one were not provided by the hardware.
You can use the valid/invalid bit supported in hardware to simulate the reference bit. Initially set the bit to invalid. On the first reference, a trap to the operating system is generated. The operating system will set a software bit to 1 and reset the valid/invalid bit to valid.
Consider a demand-paging system with the following time-measured utilizations: CPU utilization 20%, Paging disk 97.7%, Other I/O devices 5%. Which (if any) of the following will (probably) improve CPU utilization?
d. Decrease the degree of multiprogramming e. Install more main memory f. Install a faster hard disk, or multiple controllers with multiple hard disks g. Add prepaging to the page fetch algorithms h. Increase the page size (can decrease as well)
Consider a system where a program can be separated into two parts: code and data. The CPU knows whether it wants an instruction (instruction fetch) or data (data fetch or store). Therefore, two base-limit register pairs are provided: one for instructions and one for data. The instruction base-limit register pair is automatically set to read only, so programs can be shared among different users. Discuss the advantages of this scheme.
it supports the data sharing effectively. As data is in read-only mode, it provides secure data sharing. Illegal access can be avoided. It also has an effective mechanism for code and data sharing. It supports user view of memory as separate read-only segments.
Describe the following allocation algorithm: First fit
stop at first space large enough
Describe the following allocation algorithm: Worst fit
stop at largest space available
Describe the following allocation algorithm: Best fit
stop at smallest space to fit
CPU utilization, 87 percent; disk utilization, 3 percent
system is well utilized, CPU is being kept busy most of the time. Multiprogramming should stay
Consider a system where a program can be separated into two parts: code and data. The CPU knows whether it wants an instruction (instruction fetch) or data (data fetch or store). Therefore, two base-limit register pairs are provided: one for instructions and one for data. The instruction base-limit register pair is automatically set to read only, so programs can be shared among different users. Discuss the disadvantages of this scheme.
the disadvantage with this scheme is the code and data must be separated. Usually they will be combined.
CPU utilization, 13 percent; disk utilization, 3 percent
the system is underutilized, increase the level of multiprogramming
CPU utilization, 13 percent; disk utilization, 97 percent
thrashing is occurring, decrease multi-programming
Consider a logical address space of eight pages of 1024 words each, mapped onto a physical memory of 32 frames B. How many bits are there in the physical address?
Since there are 32 = 2^5 physical pages, physical addresses are 5 + 10 bits long
Why are page sizes always powers of 2?
Recall that paging is implemented by breaking up an address into a page and offset number. It is most efficient to break the address into X page bits and Y offset bits, rather than perform arithmetic on the address to calculate the page number and offset. Because each bit position represents a power of 2, splitting an address between bits results in a page size that is a power of 2.
Which page-replacement algorithms suffer from Belady's anomaly?
Second-chance and FIFO
Describe a mechanism by which one segment could belong to the address space of two different processes.
Since segment tables are a collection of base-limit registers, segments can be shared when entries in the segment table of two different jobs point to the same physical location. The two segment tables must have identical base pointers, and shared segment number must be the same two processes.
Explain why it is easier to share a reentrant module using segmentation than it is to do so when pure paging is used.
Since segmentation is based on a logical division of memory than a physical one, segments of any size can be shared with only one entry in the segment tables of each user. With paging there must be a common entry in the page tables for each page that is shared. Also, the addresses within the code are relative to the segment, so it can be relocated more easily.
Assume that you have a page-reference string for a process with m frames (initially all empty). The page-reference string has length p; n distinct page numbers occur in it. What is a lower bound on the number of page faults? What is an upper bound?
Lower bound is n. Upper bound is p.
What is Belady's Anomaly?
More frames = more page faults (applies only to FIFO and second-chance)
Consider a logical address space of eight pages of 1024 words each, mapped onto a physical memory of 32 frames A. How many bits are there in the logical address?
Addressing within a 1024-word page requires 10 bits because 1024 = 2^10. since the logical address space contains 8 =2^3 pages, the logical address must be 10 + 3 bits.
Internal fragmentation
Area occupied by a process but cannot be used by the process. This space is unusable by the system until the process releases the space.
Given memory partitions of 100k, 500k, 200k, 300k, and 600k (in order), how would each of the First-fit, Best-fit, and Worst-fit algorithms place processes of 212k, 417k, 112k, and 426k (in order)? Which algorithm makes the most efficient use of memory?
Obvious, and best-fit is the only scheme that can store all the processes (without relocation)
External Fragmentation
Exists when total free memory is enough for the new process but it's not contiguous and can't satisfy the request. Storage is fragmented into small holes.
Segmentation is similar to paging, but uses variable-sized "pages." Define two segment-replacement algorithm based on FIFO and LRU page-replacement schemes. Remember that, since segments are not the same size, the segment that is chosen to be replaced may not be big enough to leave enough consecutive locations for the needed segment. Consider strategies for systems where segments cannot be relocated, and those for systems where they can.
FIFO: Find the first segment large enough to accommodate the incoming segment. If relocation is not possible and no one segment is large enough, select a combination of segments whose memories are contiguous, which are closest to the first of the list and which can accommodate the new segment. If relocation is possible, rearrange the memory so that the first N segments large enough for the incoming segments are contiguous in memory. Add any leftover space to the free-space list in both cases. LRU: Select the segment that has not been used for the longest period of time and that is large enough, adding any leftover space to the free-space list. If no one segment is large enough, select a combination of the "oldest" segments that are contiguous in memory (if relocation is not available) and that are large enough. If relocation is available, rearrange the oldest N segments to be contiguous in memory and replace those with the newst segment.
Consider a paging system with the page table stored in memory. If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.)
If associated registers are added and the hit ratio is 75% then effective memory access time is given as EMAT = 0.75 x 200ns + 0.25 x 400ns = 250ns
Assume we have a demand-paged memory. The page table is held in registers. It takes 8 milliseconds to service a page fault if an empty page is available or the replaced page is not modified, and 20 milliseconds if the replaced page is modified. Memory access time is 100 nanoseconds. Assume that the page to be replaced is modified 70 percent of the time. What is the maximum acceptable page-fault rate for an effective access time of no more than 200 nanoseconds?
time of no more than 200 nanoseconds? Let p be the page fault rate (the probability that a memory access results in a page fault). Then (1 − p) is the probability that a memory access costs 100 nsec. The probability that a page fault costs 20 msec is 0.7 ∗ p and the probability that a page fault costs 8 msec is 0.3 ∗ p. Since 1 nsec = 1000000 msec, (1 − p)100 + 0.7(p)(20000000) + 0.3(p)(8000000) = 200 (14000000 + 2400000 − 100)p = 100 p = 100/(16400100) = 6.1 ∗ 10−6 = .0000061 = .00061%
