133 Lab
11.10. Briefly describe why an XOR gate is not functionally complete.
A XOR gate is not functionally complete because you cannot represent all the boolean operations with it. Only NAND and NOR gates are functionally complete because all the operations can be done with variations of these gates.
3.9. List the four types of concurrent statements in VHDL.
-Concurrent Signal Assignment -Conditional Signal Assignment -Selected Signal Assignment -Process Statements
2.1. Since you now know there are many ways to implement digital circuits, describe some possible parameters involved in ascertaining the "best" way.
1. simplified and efficient design layout 2. writing readable code in Vivado 3. make sure hardware is working properly
4.3. Similar to 7-segment displays, there are also 14-segment displays out there in the real world. Briefly describe the main purpose served by 14-segment displays.
14 segment displays are more useful when trying to describe more complex sets like the alphabet.
8.4. This experiment only asked you to draw a state diagram using six states. Briefly describe how many states the FSM in this experiment actually contains.
16 states
3.5. How many rows were there be in a truth table for a 32-bit RCA? Would it be feasible to design a 32-bit RCA using a truth table?
2^64. Not feasible
10.9. Write a closed form formula that relates the maximum number of unique states in a sequential circuit to the number of 1-bit storage elements in the sequential circuit.
2^x
12.7. VHDL allows you to write complex "if" statements ("if" statements containing many conditions) as well as nested if statements. Make a statement about the complexity of an "if" statement and the size of the hardware generated by such statements.
"If" statements are implemented by logic gates. For example the statement "if ( A = B) then ...:" would be an XOR gate, and the output to this gate would be the select signal for a MUX. The MUX outputs either the statement after "then" or "else" or "elsif" depending on whether the if statement is true. So for nested "if" statements, it adds more levels of gates and MUXs and generating the select signals for the MUXs can get more complicated, as the more variables there are in the conditional if statements, and the more "elsif" statements you have, the larger and more complicated the MUXs get.
8.2. Sequential circuits are referred to as having "state". In your own words, briefly describe exactly what that means.
A "state" in a sequential circuit indicates what is being memorized by the circuit.
10.5. Self-correcting hardware is a great feature in digital design. Briefly describe what the term "illegal state recovery" means and the specific condition that it attempts to avoid.
"Illegal state recovery" is where one addresses states in state machines or input values that they did not care about or didn't address in the state machine. By connecting these inputs to a state addressed in the state machine it helps avoid getting stuck somewhere you don't want to be.
14.3. Pretend this is an EE course and write a closed form formula that relates the maximum value a result can be from multiplying two n-bit numbers. Show your calculations for this problem.
(2^n - 1)^2
9.3. Briefly describe the particular attribute of a digital circuit gave the circuit the ability to store data.
A digital circuit can have the ability to store data by making the circuit's output also an input (feedback).
6.10. Often we refer to a design as a "flat" design. In terms of VHDL modeling, briefly but fully describe what that term refers to.
A flat design is a VHDL model that does not use a structural model
3.6. How many logic gates would it require to implement the 5-bit RCA using discrete logic? For this problem, assume the logic is in reduced form, meaning not in standard SOP.
A half adder requires 2 gates and a full adder requires 6 gates. Therefore a 5-bit RCA, which needs one half-adder and four full-adders requires 26 gates. (4 x full-adders = 24 gates, 1 x half-adder = 2 gates)
9.10. Briefly explain what characteristic of a circuit makes it a "mixed logic" circuit?
A mixed logic circuit is based on which state causes an action. A '1' action state is positive logic and a '0' action state is negative logic.
7.6. The output of this circuit showed dashes when the number was not valid. Is there an output that would have been more appropriate in this activity? Briefly state your thoughts on this matter.
A possible signal that would be more appropriate is one that would display "EROR" instead of dashed on the display to better illustrate an error, and possibly some form of indication that can illustrate why it is not valid or what the general problem could be
5.7. In your own words, what is a test vector and what entity generates the vectors for your testbench?
A test vector is an input that can be used for a testbench. This input will give out an output in a timing diagram. We ourselves are the entity which generate these vectors.
9.6. Briefly describe why an AND gate is not functionally complete.
An AND gate is not functionally complete because it is not possible to create an invert gate out of an AND gate.
7.1. What is a really good reason that I don't put in the effort to design a subtractor in addition to my RCA?
An RCA can be used as both an adder and a subtractor. If I want to add A+B, I would feed A & B to the inputs of the RCA. If I want to do the operation A-B, it is equivalent to A+ (-B), I would add A and the 2's complement of B together.
6.1. Show a closed form formula that relates the data width the number range for an unsigned binary number. Make sure you use an accepted format for specifying number ranges.
BW = bit width, Range: 0 - 2^(BW) - 1
6.2. Show a closed form formula that relates the data width the number range for a signed binary number in RC format. Make sure you use an accepted format for specifying number ranges.
BW = bit width, Range: [ -2^(BW-1), (2^BW-1) - 1]
10.7. Briefly state why it is that state diagrams never includes clock signals.
Because it is expected that the transitions between states happens on a clock cycle, so by showing the transitions as arrows, we show the clock's effect on the circuit.
3.8. For a RCA, the result could be available immediately, or the result could be delayed. Describe a case where the result is available immediately and also describe a case where the delay is the "worst case". State how long the worst case is in terms of "gate delays".
Best Case: No carries. Worst Case: Carry on every addition. A case where the delay is the 'worst case' would be when the AND gate for carry is activated with every adder.
1.7. Briefly described how you verified your circuit in this experiment was working properly.
By visually testing the circuit
2.6. Briefly described how you verified your circuit in this experiment was working properly.
By visually testing the circuit
3.2. Briefly describe why is it a good idea to avoid modifying previously designed modules in your new design?
Each component has a generic purpose and will not change depending on the problem. So, when we add the previously designed module, we will not need to modify it and would only need to modify the overall code/program we write.
14.5. Another attack of the SAT questions: State diagrams are to FSMs such as "X's" are to computer programming code. For this question, what does "X" refer to?
Flow Charts
5.8. Briefly explain what it would mean if the output of your simulation did not match the outputs on hardware for the same inputs?
If the simulation and hardware outputs do not match, it means that one or both of them has been implemented incorrectly.
3.4. If you needed to extend the RCA from this lab activity to a 10-bit RCA by using a structural model with two 5-bit RCAs, what changes would you need to apply to the 5-bit RCA?
If we wanted to create 1 10-bit RCA using 2 5-bit RCA's, we would first have to adjust one of the 5-bit RCA's. This adjustment would have to come in the form of replacing its half-adder with a full-adder. Once this is done, we can connect the adjusted 5-bit RCA onto the end of the other 5-bit RCA by using the latter's carry-out as a carry-in for the former.
8.8. Sequential circuits are known to contain memory, but it is not clear from the word "sequential" where the memory comes from. For this problem, briefly describe the relation between the word "sequential" and memory.
In a sequential circuit, things happen in a sequence, meaning in order. A sequential logic circuit is able to take into account their previous input state as well as the present one. They remember these conditions and stay fixed in their current state until the next clock signal changes the state, giving the circuit memory.
3.10. Do the various module instantiations in a VHDL model operate in a concurrent manner? Briefly explain why or why not.
It depends on their declaration. If something is declared using concurrent statements then it will operate in a concurrent manner. But if it is declared in a sequential manner then it will not.
6.8. In computer programming, briefly describe why it is the best idea to use an unsigned integer type when it is known that the value will never be negative.
It is better to use an unsigned integer when a value will never be negative because it can hold a larger value than a signed integer with the same number of bits.
13.5. One of the great selling points of many computer-type devices is that they do exclusively integer- based math as opposed to using floating point math. Why would this be a good selling point for hardware? Briefly but completely support your answer.
It is faster and cheaper, because doing calculations using decimals in binary is really difficult, so it saves time and money by only doing integer based math. However, integer math is faster but less accurate.
8.3. Briefly describe why state diagrams generally do not include any notion of a clock signal.
It is implied that a clock signal governs each transition.
8.1. Briefly describe the difference between a flip-flop and a latch.
Latches are level-sensitive (asynchronous) whereas flip-flops are edge-sensitive (synchronous).
13.1. Briefly describe why the two ways to calculate parity for a given set of bits. In other words, describe why we have both a "human version" and a "hardware version"?
Machines do not inherently know if a number is even or odd like a human, so while a human can count the number of switches flipped and know what the parity of a set of bits is, you have to tell the machine by shifting the bits out one by one and counting that number. Also, HW version uses XOR gates.
1.1. In your own words, what is meant by the term "methodology".
Methodology is an analysis of the steps someone takes to solve a problem.
11.3. Mealy-type FSM are able to "react" more quickly than Moore-type FSMs. Briefly describe what characteristic of a Mealy-type FSM makes this the case.
Moore outputs need to wait until the next clock cycle to change; Mealy outputs can change when the inputs change.
5.4. We all know that the well-known hallmark of a comparator is that it uses EXOR-type gates in its implementation. Does the development board you're using actually use EXOR-type gates in your design? Briefly but completely explain.
No, it completes it through the use of lookup tables, instead of specific-type gates.
6.12. In general, does the number of levels of a particular design affect the resources required to implement that design using VHDL and implementing that circuit on an FPGA? Briefly but fully explain.
No, using more levels just allows the design to be interpreted easier by humans, and does not affecting how the circuit works or the amount of memory it stores
7.3. Could you arbitrarily use the LSB of a binary number in RC form as the sign bit and still be able to do basic mathematical operations? Briefly explain.
No, we can't use the LSB without completely redesigning the circuit because one would have to shift the other digits over to do mathematical operations and then add the bit back on and it would cause the number to be effectively very different. For example if one did a calculation that ended with "011" or 3 and then set the sign bit to return "0111" it would look like they returned 7 not
12.8. VHDL process statements contain "process sensitivity lists". If you modeled two MUXes in VHDL that were identical except for the fact that one MUX included the select signals in the process sensitivity list, and the other not, would the hardware generated by these two MUXes be identical? Briefly explain.
No, we will not get the same output. For combinatorial logic, if all the input signals are not part of the sensitivity lists, then the output will not change even when the inputs change. Similarly, for synchronous logic, we only want the clock and maybe the reset in the sensitivity list because we are only concerned with the values of the signal only when the clock has changed. Also, some synthesis tools may not check for sensitivity lists of processes. These tools may assume that all signals on the right-hand side of sequential signal assignments are in the sensitivity list. Thus these synthesis tools will interpret the two processes to be identical.
8.6. In your own words, describe what exact attribute of a concurrent signal assignment that directs the synthesizer to induce a memory element.
Not having a catch all statement causes the synthesizer to induce a memory element.
3.7. Write a formula in closed for that describes the number of gates in a RCA as a function of the bitwidth of the RCA. Recall that the LSB of the RCA is a HA. For this question, assume the FA and HA are in reduced form (not in standard SOP form).
Number of bits = n Number of gates required = 6(n-1) +2
11.5. State transitions in FSMs are primarily controlled by an active clock edge. Briefly describe one of the major factors in establishing a maximum possible clock speed for a given FSM.
One major factor is set up time which is the amount of time circuit inputs need to be stable before the clock edge. The other factor is hold time which is the amount of time circuit inputs need to be stable after the active clock edge. And delays
13.2. Briefly describe the main purpose of a parity generation and detection.
Parity generation and detection is helpful for error detection, since you can know very quickly if something is wrong in your hardware if you are expecting even parity and get odd or visa-versa by tracking the input parity and output parity.
2.2. Briefly comment on which form (SOP or POS) of the HA &FA was easier to design and implement.
SOP was easier to design and implement
14.4. Attack of the SAT questions: State diagrams are to FSMs such as "X's" are to circuits. For this question, what does "X" refer to?
Schematics
14.2. What are the four operations you can perform on a single bit?
Set, clear, toggle, hold
13.3. Shift registers are synchronous circuits. Describe what limits how fast you can shift a simple shift register and still have the device operate properly.
Shift registers only shift in a value on the clock cycle, so if the clock has a slow change, the register can only do so many shifts in a period of time and not loose values or mess up.
7.8. Quite often in digital design, there are boundary condition issues you need to deal with. What this means to me is that 98% of the errors I make in a design are with a boundary condition. This lab activity also has a boundary condition that essentially renders the result invalid even though it passes our simple validity checker. Briefly describe this boundary condition. HINT: the notion that it is a boundary condition roughly means that is has something to do with the far end of the given number range for the RC numbers.
Since we are dealing with 5-bit numbers it wouldn't be possible to subtract -16, because we wouldn't be able to represent it in 4-bits.
12.3. Relating to the previous problem, if the system clock frequency was 100MHz, how much time was required to complete the complete sort operation for the best and least case scenarios. Show your calculations for this problem. Assume your circuit is not using a clock divider. Don't even think of not writing your answer using engineering notation.
So the time it take to calculate the product is 7*10^-6 seconds.
12.4. There are many sort algorithms out there. State two reasons why you would choose one over another. For this problem, consider your task is to implement the problems in hardware.
Speed, efficiency, ease of implemenation...
8.5. Briefly but completely describe the three basic modules of a FSM. Make sure your description includes which of the two classes of digital circuits the modules represent.
State Decoder- shows what happens based off of the previous state and the external input. Register- stores the data so that it can either be fed back into the next state decoder or go into the output. Output Decoder- can either just use the previous state for an output or it can use the external input as well, this determines what kind of output it is (Moore vs Mealy).
14.11. List the four types of information provided by a state diagram. State diagrams provide information about the current state, input, output and the transition to the next state.
State diagrams provide information about the current state, input, output and the transition to the next state.
3.1. Briefly describe the two main attributes of modern digital design.
Structural modeling and hierarchical modeling
2.3. Briefly describe how the full adder is somewhat limited in doing math operations.
The FA will only take in 3 inputs and will only output answers in binary
8.7. The state registers in a FSM are considered a synchronous circuit. Briefly describe what this means in context of the FSM.
The FSM's changes of state of memory are synchronized directly with a clock signal.
1.5. How many signal assignment statements did you use in your VHDL model for the HA?
The HA has 2 signal assignment statements
1.6. Briefly describe the basic limitation of the HA (relative to the FA) in the context of a mathematical digital circuit.
The HA is disadvantaged because it cannot read in a carry to add from a previous circuit element.
11.4. In the previous question, briefly describe what exactly the term "react" refers to?
The action is initiated by a change in the output.
5.2. In your own words, briefly describe the advantage(s) of using a behavioral model as opposed to a gate-level implementation of the comparator.
The behavioral model has a bunch of logic going on behind the scenes, that we can avoid implementing when we use it, which saves a lot of time and prevents you are making errors in the fate-level implementation.
1.4. There is a programmable logic device (PLD) on the development board used for this class. What particular type of PLD is on the dev board?
The board for this class uses a FPGA PLD.
3.3. In your own words, briefly but completely explain why the circuit in this lab activity is referred to as a "ripple carry adder".
The circuit in this lab is called a ripple carry adder because the carry out from the full adders is carried to the next adder as a carry in or an input into the half adder. This means that the data from one adder is carried to the next one, then to the next, and so on in a sort of "ripple".
1.2. Briefly describe the purpose of the "constraints file", which is another name for the file with the ".xdc" extension.
The constraints file is used to assign the inputs and outputs of our design to the components on the Basys 3 board.
10.2. From your VHDL model, what would happen if any other input is asserted at the same time as the RESET input?
The input would not be asserted
5.3. Based on the previous question, you probably see that modeling comparators of any size is no big deal using VHDL. Why then did this lab activity ask that you model a larger comparator using two smaller comparators?
The lab had us use two smaller comparators instead of one larger comparator because it helps us to better understand the concept of hierarchical design. It also allows us to make a reasonably-sized truth table if needed.
11.6. Slower clock speeds of any circuit are generally considered better because they save power. Briefly describe the main factor in deciding the minimum clock speed for your FSM and still have it do the job you need it to do.
The main factor for this clock speed is the how quickly the cycle can run through with the button input. Therefore, the hold time of the button is what decides the minimum clock speed for the FSM.
3.11. Briefly describe the notion of concurrency in digital circuit design.
The notion of concurrency in digital circuit design refers to parallelism. What this means is that VHDL can model a virtually limitless number of statements at the same time.
6.3. For a given bit-width, does the number of unique numbers in an unsigned binary and signed binary number in RC format differ?
The number of unique numbers in an unsigned binary and signed binary number in RC format does not differ. The maximum magnitude of signed binary numbers in RC format is half that of unsigned binary numbers, but signed binary numbers can be positive or negative.
5.6. The process statement contains a "process sensitivity list". Briefly describe what this is. Also, state what you should generally place in the process sensitivity list.
The process statement triggers the process and contains the signals that do so.
1.3. Briefly describe what you're doing when you "synthesize" your VHDL model.
The process where VHDL is compiled and mapped to an implementation.
3.12. Consider two different VHDL models that are functionally equivalent; in particular, they are mostly the same except for the notion that one used structural modeling and the other implemented a similar set of modules but did not use structural modeling. Would expect the synthesized circuit based on these models to use the equivalent amount of resources or will one approach use more or less resources. Support your answer with intelligent commentary.
The synthesized circuit based on these models should end up using the equivalent amount of resources. For the RCA, although the high level structural model of the RCA consists of half adders and full adders, these half and full adder modules consist of the same logic gates that would be used if the RCA was not constructed using structural modeling. The structural modeling approach is superior because it is more organized and allows for modules to be reused.
9.5. Briefly describe what the term "sequential" refers to in the term "sequential circuit".
The term sequential refers to the order of events performed by the circuit, or the sequence of actions. So in a sequential circuit, the circuit works on the basis of the sequence of the Inputs.
9.4. Briefly describe the relation, if any, between a sequential circuit in digital design and a sequential statement in VHDL?
There is no relation.
11.2. Given two FSMs that perform the same basic function, a Mealy-type model typically has fewer states than Moore-type models. Briefly describe why that is generally the case.
This is because a Moore-type the outputs of the moore machine is solely a function of the state, which would need to be taken into account. This causes it to have more states, compared to a Mealy-type which would be able to account for the multiple outputs with different controls/actions in one different state.
9.9. An EXNOR gate is often referred to as an "equivalence gate". Briefly explain how it would get such a name.
This is because when the inputs are the same, it outputs a one, and when the inputs are different it outputs a zero, thus making it an "equivalence gate."
7.7. Using the development board under the conditions stated in this lab activity, would it have been possible to design an adder/subtractor unit based on 9-bit signed binary numbers (RC format)? The problem here is that you run out of switches to support 18-bit number. Consider all possibilities and fully explain your answer.
This is possible as you can set up the buttons on the development board to act at switches for the extra bits so that you can support an 18-bit number.
7.4. I have this great idea to generate signed BCD numbers. Would this be a great idea or what?
This would not be a good idea because BCD numbers use 4 bits to represent each digit and can easily be converted to RC form so this would be a repetitive and confusing way of representing signed numbers.
12.2. How many clock cycles did your circuit require to complete the sort? Your answer to this question should address best and worst case scenarios.
To calculate the product, it takes 7 clock cycles.
7.5. Briefly describe the steps necessary in order to extend this design to 8-bit signed binary numbers (once again, assume your development board and provided modules are not limiting factors).
To extend this to a 8-bit, you have to adjust the decoder used in the seven segment display in order to be able to display the correct values. Also, you have to increase the STD_LOGIC_VECTOR from (4 downto 0) to (7 downto 0) .
7.9. Describe the modifications you would need to make to the circuit in this lab activity is you needed a 2*A or A-B circuit instead of the A+B or A-B. Do not use a shift register in your solution.
To implement a 2*A or A-B circuit, we would need a RCA to add the bits of A to each other, or in order to get 2*A, if the button is not pressed and hook up the original A input to a MUX with the complement of B like we did in our original circuit.
1.8. Briefly describe the main purpose of a "gate" in the context of this course.
To implement basic logic functions
13.9. Briefly describe the main purpose of a "gate" in the context of this course.
To implement basic logic functions. A logic gate is an elementary building block of a digital circuit. A logic gate is an idealized or physical device implementing a Boolean function; that is, it performs a logical operation on one or more binary inputs and produces a single binary output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts(0 V), while the high state is approximately five volts positive (+5 V).
6.6. Two types of standard digital modules (other than half and full adders) are famous for using XOR-type gates in there implementation. What are these two modules?
Two modules commonly known to have XOR gates are Comparators and Parity generators
4.1. If you were not able to use a decoder in this experiment, how many concurrent signal assignments would you have needed to implement the segments portion of the seven segment display? Briefly explain.
Use 8 times the number of signal assignments used when a decoder was applicable, and each would be through a BCD.
4.5. One of the important design approaches in VHDL is to use a LUT (decoder) whenever possible. Briefly describe why this is a good approach.
Using a LUT is a good approach because it is essentially the truth table for combinational logic. If you can model something with a lookup table, you can easily implement it in VHDL. It is a low-level design approach that is similar to brute force design model which is tedious, yet the most descriptive.
6.9. In computer programming, briefly describe what happens when a mathematical operation exceeds the ranges for the data types associated with that operation? Does the programmer typically know the range has been exceeded?
Usually the most significant bit is lost and only the bits supported by the bit width are shown on the output. In other forms of computer programming, the user is often given a warning about the number range having been exceeded.
7.10. Provide your well-supported comments regarding the following statement: "VHDL behavioral models are much more powerful than VHDL dataflow models."
VHDL behavioral models are more powerful than dataflow models because with behavioral models we can build the circuit element by describing it, as opposed to only looking at the underlying structure, like in a data flow model.
5.5. The process statement is one of VHDL's concurrent statements. But, the process statement contains only sequential statements in the body of the process statement. Describe how this seemingly oxymoron is actually possible.
VHDL have concurrent statements however, that also means that sequential statements will be read in order as they are not being executed but rather used as a description. The result regardless will be the completed circuit.
5.10. We often use hexadecimal notation in digital-land. Can you use hex notation to represent signed binary numbers in RC format? Briefly explain.
We CAN use hex notation to represent unsigned binary numbers because the purpose of hex notation is to express binary numbers in a way that is easier to understand.
5.1. Briefly describe whether you could have used a decoder for the "logic box" portion of this lab?
We could use a decoder for the logic box portion of this lab since we could use a truth table from the sequential statements.
13.7. A shift-right operation officially performs truncation on the value in the shift register. Briefly explain what this means in the context of a shift register that shift right.
When a shift right operation occurs, and the value shifted in the register is zero, the shift register is essentially dividing by two for every shift and chopping off the least significant bit.
11.1. Describe an application where sequence detectors could potentially be useful.
When implementing something that requires a password, like a safe.
14.9. So, I ask my higher-level computer programming language to execute an unsigned integer multiplication algorithm (meaning, I use the "*" operator in an expression), and it does it for me. Is there a way to know what algorithm the computer uses to perform that operation? Briefly but completely explain.
Yes, by looking in a data sheet or forum seeing how the bits are moving.
6.5. Can an 8-bit binary number in unsigned format ever be an odd number but have even parity? Briefly explain.
Yes. Parity has nothing to do with even and odd numbers, it just counts the number of "set" bits in a group of bits. For example, the number 3 (in binary of 4 bits is "0011") has even parity because 2 bits are set, even though it is an odd number.
6.7. Can signed binary numbers in RC format have the notion of parity associated with them? Briefly explain your answer.
Yes. Parity refers to the number of bits that are set. Therefore, signed binary numbers can have the notion of parity associated with them, and depending on how many bits are '1', the parity is either even or odd.
2.4. Briefly describe how you could configure the two full adders to become a two-bit adder.
You can connect one FA with another FA by making the carry out of one of the FA's as the carry in for the other
13.6. If a shift register was used with signed binary numbers (RC), briefly describe what you would have to do when you right-shift a number. For this problem, assume the shifted number is such that the result is always valid.
You must preserve sign bit.
10.8. If someone told you they encoded their FSM using eight flip-flops, would you know how many unique states were in their state diagram? Briefly explain.
You would know that their state diagram could have a maximum of 2^8 = 256 states, and a minimum of 2^7 = 128 states