CECS 346 Midterm 2

At reset, BASEPRI is set to reject interrupts at all priority levels. (T/F)

False

Function EnableInterrupts() defined in startup.s sets bit 0 of the special register PRIMASK to be 1. (T/F)

False

On the TM4C, SysTick interrupt needs to be acknowledged by software in its ISR. (T/F)

False

A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. (T/F)

True

A vectored interrupt system employs separate connections for each device so that the computer can give automatic resolution. (T/F)

True

ARM Cortex M4 NVIC allows a higher priority interrupt to suspend the execution of a lower priority ISR. (T/F)

True

Interrupt vectors are stored in ROM at the beginning of memory. (T/F)

True

Most interrupts on the TM4C microcontrollers are vectored, a few are polled. (T/F)

True

On the TM4C microcontrollers, only the top three bits of the four 8-bit fields in register NVIC_PRIx_R are used: allow priority level 0-7, with 0 being the highest priority. (T/F)

True

The choice of frequency involves the tradeoff between software execution speed and electrical power. (T/F)

True

The following instruction sets up SysTick with interrupt enabled. NVIC_ST_CTRL_R = 0x00000007; (T/F)

True

The following code set interrupt priority to which level? NVIC_PRI8_R = (NVIC_PRI8_R & 0xFFFF1FFF) | 0x00006000; a. 3 b. 6 c. 5 d. 4 e. none of them

a. 3

Nested Vectored Interrupt Controller on TM4C123 Launchpad: a. Controls all exceptions b. Control some exceptions c. Controls only vectored interrupts d. Controls only polled interrupts

a. Controls all exceptions

Please find the right priority register for GPIO PORT B edge-triggered interrupt. a. NVIC_PRI0_R b. NVIC_PRI1_R c. NVIC_PRI2_R d. NVIC_PRI7_R e. none of them

a. NVIC_PRI0_R

If BASEPRI is set to be 4, which one of the following priority interrupts will be masked out? a. 2 b. 4 c. 0 d. 3 e. 1

b. 4

This question is for Lab6. What is the reload value for half second? a. 8000000 b. 7999999 c. 16000000 d. 15999999 e. None of them

b. 7999999

The following code tells us which bit in Port A is used to generate edge-triggered interrupt? void GPIOPortA_Handler(void){ GPIO_PORTA_ICR_R = 0x04; FallingEdges = FallingEdges + 1; } a. Bit 1 b. Bit 2 c. Bit 3 d. Bit 4

b. Bit 2

This question is for Lab6 Interrupts. Which of the following function implements LED color change? a. none of them b. GPIOPortF_Handler c. SysTick_Init d. SysTick_Handler e. main f. Switch_LED_Init

b. GPIOPortF_Handler

The following code sets Port F bit 5 to accept what type of interrupt? GPIO_PORTF_IS_R &= ~0x20; GPIO_PORTF_IBE_R &= ~0x20; GPIO_PORTF_IEV_R |= 0x20; a. none of them. b. Rising edge c. Falling edge d. Both edges

b. Rising edge

This question is for Lab6 Interrupts. Which one of the following function implements LED blinking? a. Switch_LED_Init b. SysTick_Handler c. SysTick_Init d. None of them e. GPIOPortF_Handler f. main

b. SysTick_Handler

The question is for Lab6. Which function set the LED blinking speed? a. SysTick_Handler b. SysTick_Init c. GPIOPortF_Handler d. None of them e. Switch_LED_Init

b. SysTick_Init

Which one of the following is NOT the three abilities any interrupt system must have? a. The ability for the computer to determine the source. b. The ability to support both positive and negative edge-triggered interrupts. c. The ability for the hardware to request action from computer. d. The ability for the computer to acknowledge the interrupt.

b. The ability to support both positive and negative edge-triggered interrupts.

We would like to use PLL to generate a 40MHz system clock. Assume 400MHz PLL output is used to generate this system clock. Please calculate the value for SYSDIV2 field (bit 28-22) in register SYSCTL_RCC2_R shown. Datasheet field description: Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator sources (depending on how the BYPASs2 bit is configured). SYSDIV2 is used for the divisor. a. 7 b. none of them c. 15 d. 4 e. 9

b. none of them

Please find the XTAL value for a 25MHz clock source based on the table given. a. 0x19 b. 0x15 c. 0x1A d. 0x9 e. none of them

c. 0x1A

How many different edge-triggered interrupts are implemented in TM4C123? a. 1 b. 2 c. 3 d. 4

c. 3

Which interrupt does the following code enable? NVIC_EN0_R |= 0x00000010; a. Port A b. Port C c. Port E d. Port F e. SysTick interrupt

c. Port E

Which of the following is NOT one of the 5 conditions that must be true for an interrupt to be generated? a. Hardware event trigger b. Global enable c. Device arm d. interrupt priority level must be 0 e. NVIC enable

d. Interrupt priority level must be 0

The maximum clock frequency can be set with PLL for TM4C123 is: a. 400MHz b. 50MHz c. 16MHz d. none of them e. 80MHz

e. 80MHz

The following code set interrupt priority for which interrupt source? NVIC_PRI8_R = (NVIC_PRI8_R & 0xFF1FFFFF) | 0x00400000; a. SysTick timer interrupt b. Port F interrupt c. Port B interrupt d. UART 2 Interrupt e. SSI1 Interrupt f. None of them

e. SSI1 Interrupt

This question if for Lab6. Every time the onboard switch 2 (PF0) is pressed and released, the LED color will be changed to the next color in a round robin order of red, blue, and green. Which one of the following interrupt is a best fit to capture the required switch event? a. Both edges b. Falling edge c. Low level d. None of them e. High level f. Rising edge

f. Rising edge