CET 3116 Homework Quiz 8

Suppose that the in the circuit above the propagation delay of the inverter is 1.5 ns and the propagation delay and setup times of the flip-flop are 3.5 ns and 2 ns respectively. What is the shortest clock period for the circuit that will not violate the time constraints?

- 3.5 ns - 5.5 ns - 8 ns None of the above

What would be the output of a JK Flip-Flop (assume 74LS112) at the end if J=1 and K=0 for one clock pulse and then J=1 and K=1 for the next 3 clock pulses? Assume that PS and CLR are both 1.

0

For the circuit shown what are the values of Q for times t0,t1,t2 respectively? Assume Q=0 initially.

0 1 0

The figure above shows a waveform for the inputs of a JK flip-flop falling-edge-triggering with PRESET and CLEAR. What are the values of the flip-flop output for the times shown in c, g, i, k and o respectively?

0, 0, 1, 1, 1

The figure above shows a waveform for the inputs of a JK flip-flop rise-edge-triggering. What are the values of the flip-flop output for the times shown in b,d,f,h and j respectively?

0, 1, 1, 1, 0

The figure above shows a S-R circuit and the the corresponding waveform for the inputs S and R. What are the values of the output Q for times t1, t2, t3 and t4 respectively?

0,0,1,1

For the circuit of the figure above, if the circuit is fed with the waveform given, what are the values of Q for times t1,t2 and t3 respectively? First, find the excitation equation for the Flip-Flop input D in function of Q and "input". Then build the truth table using the inputs Q and "input" and find the output Q+.

1,1,0

The table given above shows some parameters for the a 7474 Edge Triggered D Flip-Flop. What would be the maximum operating frequency this type of flip-flop? Observe that the clock cannot change until the output is stable, after either the hold time or the propagation time. Now notice that they overlap. Also it mus guarantee that the output remain stable (as the input for a following stage) for the set-up time

16.66 MHz

A negative-edge-triggered J-K flip-flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states? Note: PGT: Clock transition from '0' to '1' NGT: Clock transition from '1' to '0'

CLK = NGT, J = 1, and K = 0

The table given above shows some parameters for the a 7474 Edge Triggered D Flip-Flop. Which of the following circuit parameters would be most likely to limit the maximum operating frequencythis type of flip-flop?

High-to-Low Propagation delay time

What is one disadvantage of an R-S flip-flop?

It has an invalid state.

If both inputs of an S-R flip-flop are low, what will happen when the clock goes high?

No change will occur in the output.

The preset and clear inputs to a J-K flip-flop are HIGH (1). Which of the following is true?

The flip-flop is free to respond to its J, K, and clock inputs.

Asynchronous flip-flop preset and clear inputs generally:

act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions.

The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:

is controlled by the logic level at its ENABLE input rather than a CLK transition.

Which of the following flip-flop timing parameters indicates the time it takes a Q output to respond to an input?

t phl, t plh

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

the FF is edge-triggered and can only change states when the clock goes 0 to 1.

The setup time of a clocked flip-flop is:

the minimum amount of time that an input must remain stable before an active clock transition.

When both inputs of a J-K pulse-triggered FF are high, and the clock cycles, the output will ________.

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