Ch 14: Instruction sets: Addressing Modes and Formats
Variable-length instructions
A larger repertoire of opcodes is possible with variable length instructions.
Autoindexing
A register used for indexing that will automatically increment by one each instruction cycle. (R) <-- (R) +1
Displacement addressing
A very powerful mode of addressing combines the capabilities of direct addressing and register indirect addressing. EA= A + (R)
Direct addressing
A very simple form of addressing in which the address field contains the effective address of the operand.
Immediate addressing
The operand value is present in the instruction. Operand=A. The sign bit is extended left to the entire word size.
Displacement mode x86 addressing
the operand's offset (the effective address within a segment) is contained as part of the instruction as an 6, 16, or 32 bit displacement. This is a type of direct addressing.
Indexing addressing
the opposite of base-register addressing. The address field references a main memory address, and the referenced register contains a positive displacement from that address. Useful for iterative tasks.
Base-register addressing
the referenced register contains a main memory address and the address field contains a displacement. This exploits locality of reference.
Register Addressing
similar to direct addressing. The only difference is that the address field refers to an entire register rather than a main memory address. EA=R
Base scaled index with displacement mode x86
sums the content of the index register multiplied by a scaling factor, the contents of the base register, and the displacement.
Base with index and displacement mode x86
sums the contents of the base register, the index register, and a displacement to form the effective address.
Indirect Addressing
the address field refers to the address of a word in memory, which in turn contains a full length address of the operand. EA=(A)
Index register
the chosen register for indexing addressing
Pre-indexing
the indexing is performed before the indirection EA= (A + (R))
Base with displacement mode x86
the instruction includes a displacement to be added to a base register. This is useful when referencing a data structure like an array, stack, or field.
Scaled index with displacement mode x86
the instruction includes a displacement to be added to a register, in this case called an index register. The index register can be multiplied by a scaling factor.
ARM preindex addressing
the memory address is formed the same way as with offset addressing, but the base register is also updated.
ARM postindex addressing
the memory address is the base register value. The offset is added to the base register to update it after.
Immediate mode x86 addressing
the operand is included in the instruction
register operand mode x86 addressing
the operand is located in a register. The operand is in a 32, 16, or 8 bit general register.
x86 prefix bytes
1. Instruction prefixes (a lack or repeat prefix may be presented) 2. Segment override (specifies which segment register to include other than the implicit register) 3. Operand size 4. Address size
Instruction length design principals
1. Larger instructions= more opcodes (and operands, addressing modes, and address range, but requires more space. This allows more flexibility to the programmer) 2. Should be a factor of memory transfer length 3. Should be a multiple of character length
Factors that determine the use of addressing bits
1. Number of addressing modes (a bit may be included to differentiate between addressing modes) 2. Number of operands (usually 2 are present) 3. Register versus memory (a couple of bits signal which register) 4. Number of register sets (necessary if there are different sets of registers) 5. Address range (more range=more bits) 6. Address Granularity (more granularity= more bits)
x86 Instruction contents
1. Opcode 2. ModR/M (Specifies whether an operand is in a register or in memory) 3. SIB (adds onto the ModR/M) 4. Displacement 5. Immediate (provides an immediate value)
PDP-10 instruction set design principals
1. Orthogonality 2. Completeness 3. Direct Addressing
VAX instruction format
All instructions (should) have their "natural" number of operands. All operands should have the same generality in specification. VAX can have up to 6 operands. In theory, it allows more efficient compilations of high-level languages. However, it also requires a more complex processor.
ARM instruction formats
All instructions in the ARM architecture are 32 bits long and follow a regular format. - First four bits are the condition code - Next 3 bits specify general instruction, next 5 are specific instruction. - Remaining 20 bits are operand addressing.
Stack addressing
Also referred to as a push down list or LIFO queue. Associated with the stack is a pointer whose value is the address at the top of the stack.
PDP-10 Instruction set
Emphasis on making an easy to program, time shared system. It has a 36-bit word an instruction length.
Postindexing
If indexing is performed after the indirection EA= (A) + (R) Note that R comes second
Effective address
In a system without virtual memory, it is the memory address or register. If virtual memory is present, it may also be a virtual address.
Relative addressing x86
It can be used in transfer-of-control instructions. A displacement is added to the value of the program counter.
PDP-11 instruction set
It was originally designed to provide a powerful and flexible instruction set within the constraints of a 16-bit mini computer. Eight 16-bit general purpose registers are used.
Orthogonality
Linking the addressing mode to the operand rather than the opcode. Thus, the opcode and addressing mode are independent of each other. In general terms for computer science, orthogonality refers to two variables being independent of each other.
ARM immediate Constants
To achieve a greater range of immediate values, the data processing immediate format specifies both an immediate value and a rotate value.
Register Indirect Addressing
analogous to indirect addressing. A register is referenced that holds a memory address that has the operand in it. EA= (R)
Multi-level or cascaded addressing
a rarely used variant of indirect addressing, where multiple levels are referenced EA= (...(A)...)
ARM THUMB instruction set
a re-encoded subset of the ARM instruction set. Thumb is designed to increase the performance of ARM implementations that use a 16 bit of narrower memory data bus and to allow better code density. Note that: - Thumb instructions are unconditional - There are less Thumb instructions - There are less operand specifications
Relative Addressing
also called PC-relative addressing, the implicitly referenced register is the program counter. The next instruction address is added to the address field to produce the EA.
ARM THUMB-2 Instruction set
an enhancement to Thumb. The instruction size is 32 bits and covers almost all of the functionality of the ARM instruction set. It also has code density comparable to Thumb.
Base mode x86 addressing
an indirect addressing mode that specifies that one of the 8, 16, or 32 bit registers contains the effective address. This is like register indirect addressing.
ARM offset addressing
an offset value is added to or subtracted from the value in the base register to form the memory address.
Instruction Format
defines the layout of the bits of an instruction, in terms of its constituent fields. It must include an opcode, operands, and an addressing mode.
ARM data processing instruction addressing
either register or immediate addressing
ARM Load/Store multiple addressing
load or store multiple instructions. Load or store all (or some) of the general purpose registers.
PDP-8 Instruction set
one of the simplest instruction designs for a general purpose computer. It uses 12 bit instructions and words. Opcode 7 defines microinstrcutions.
Mode Field
one or more bits that determine which addressing mode is to be used.
ARM branch instructions addressing
only immediate addressing is used.
x86 Instruction Formats
only the opcode is always present. The addressing mode is provided as part of the opcode.