Chapter 3 Computer Org. & Archit.

Each data path consists of a pair of wires (referred to as a __________ ) that transmits data one bit at a time. A. lane B. path C. line D. bus

A. lane

A sequence of codes or instructions is called __________. A. software B. memory C. an interconnect D. a register

A. software

A bus that connects major computer components (processor, memory, I/O) is called a __________. A. system bus B. address bus C. data bus D. control bus

A. system bus

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. A. transaction layer B. root layer C. configuration layer D. transport layer

A. transaction layer

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. A. John Maulchy B. John von Neumann C. Herman Hollerith D. John Eckert

B. John von Neumann

A(n) _________ is generated by a failure such as power failure or memory parity error. A. I/O interrupt B. hardware failure interrupt C. timer interrupt D. program interrupt

B. hardware failure interrupt

A __________ is the high-level set of rules for exchanging packets of data between devices. A. bus B. protocol C. packet D. QPI

B. protocol

The data lines provide a path for moving data among system modules and are collectively called the _________. A. control bus B. address bus C. data bus D. system bus

C. data bus

The processing required for a single instruction is called a(n) __________ cycle. A. execute B. fetch C. instruction D. packet

C. instruction

A(n) _________ is generated by some condition that occurs as a result of an instruction execution. A. timer interrupt B. I/O interrupt C. program interrupt D. hardware failure interrupt

C. program interrupt

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. A. link B. protocol C. routing D. physical

C. routing

The __________ are used to designate the source or destination of the data on the data bus. A. system lines B. data lines C. control lines D. address lines

D. address lines

The TL supports which of the following address spaces? A. memory B. I/O C. message D. all of the above

D. all of the above

The interconnection structure must support which transfer? A. memory to processor B. processor to memory C. I/O to or from memory D. all of the above

D. all of the above

The von Neumann architecture is based on which concept? A. data and instructions are stored in a single read-write memory B. the contents of this memory are addressable by location C. execution occurs in a sequential fashion D. all of the above

D. all of the above

A key characteristic of a bus is that it is not a shared transmission medium.

False

An I/O module cannot exchange data directly with the processor.

False

Interrupts do not improve processing efficiency.

False

It is not possible to connect I/O controllers directly onto the system bus.

False

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

False

A(n) ________ interrupt is generated by an I/O controller to signal normal completion of an operation, request service from the processor, or to signal a variety of error conditions.

I/O

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet.

True

At a top level, a computer consists of CPU, memory, and I/O components.

True

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

True

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.

True

Program execution consists of repeating the process of instruction fetch and instruction execution.

True

The basic function of a computer is to execute programs.

True

Timing refers to the way in which events are coordinated on the bus.

True

With __________ timing the occurrence of one event on a bus follows and depends on the occurrence of a previous event.

asynchronous

A __________ is a communication pathway connecting two or more devices.

bus

Bus lines can be separated into two generic types: ________ and multiplexed.

dedicated

A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.

disabled

The QPI link layer performs two key functions: flow control and _________ control.

error

The most common classes of interrupts are: program, timer, I/O and ________.

hardware failure

The collection of paths connecting the various modules is called the _________ structure.

interconnection

A __________ register specifies the address in memory for the next read or write.

memory address (MAR)

A _________ register contains the data to be written into memory or receives the data read from memory.

memory buffer (MBR)

The __________ is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus.

peripheral component interconnect (PCI)

A(n) _________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

timer