Cosc 2150 Exam II

Evaluate 2 3 + 6 3 * +

23

A system has 32 registers and 64k of memory. How many bits are required to access one of the registers?

5

If a pipeline has 7 stages, what is the theoretical speedup possible as compared to a sequential processor

7

Direct Addressing

Address of the data is given in the instruction

For registers: contains the machine code instruction

IR

A 32-bit data bus consists of 32 separate single bit channels. T/F

True

In cache memory, the miss penalty is the time required to process a miss, including the time that ittakes to replace a block of memory plus the time it takes to deliver the data to the processor. T/F

True

(Between multiplexed, dedicated, or both) which bus contains both data and address lines

both

Memory-mapped I/O

shares memory address space between I/O devices and program memory

(There are four different approaches to CPU short term scheduling.)the smallest jobs get scheduled first

shortest job first

Channel I/O

uses dedicated I/O processors

The clock frequency for a modern microcontroller is measured in MegaHertz (MHz). If a microcontroller has a clock source of 1 MHz, how many clock cycles occur per second?

1,000,000

A system has 32 registers and 64k of memory. How many bits are required to specify a memory address within the instruction?

16

Big endian machines store the most significant byte first (at the lower address): T/F

True

In associative cache mapping, main memory blocks are allowed to go anywhere in cache. In this way, cache would have to fill up before any blocks are evicted. T/F

True

In set associative cache mapping, a memory block can map only to the subset of cache slots. T/F

True

Sluggish input/output system throughput can have a ripple effect, dragging down overall system performance. T/F

True

The simplest cache mapping scheme is direct-mapped cache. In this technique, a cache consisting of N blocks of cache and X blocks of main memory maps to cache block Y = X mod N. This provides for a fixed cache location for a given block. T/F

True

The two principal parts of the CPU are the datapath and the control unit. The datapath consists of an arithmetic logic unit and registers. The CPU performs sequenced operations according to signals provided by its control unit. T/F

True

There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into read-only memory (ROM). The resulting control signal pattern is the same regardless of which control scheme is implemented. T/F

True

Interrupt-driven I/O

allows the CPU to do other things until I/O is requested

(Between multiplexed, dedicated, or both) more complex control

multiplexed

The clock frequency for a modern microcontroller is measured in MegaHertz (MHz). If a microcontroller has a clock source of 1 MHz, how often does a clock cycle repeat? Express your answer in microseconds.

1

Instruction sets are differentiated by the following: a. Number of bits per instruction. b. Number of explicit operands per instructions. c. Operand location. d. Types of operations. e. Type and size of operands.

A through E

Compared with parallel data interfaces, serial communications interfaces: a) Are less expensive b) Require fewer conductors c) Are less susceptible to attenuation and degradation

A, B, C

Which bus width determines the maximum memory capacity of system?

Address

Amdahl's Law gives us a handy way to estimate the performance improvement we can expect when we upgrade a system component. The premise behind Amdahl's Law is the overall performance of a system is a result of the interaction of all of its components. System performance is most effectively improved when the performance of the least used components is improved. T/F

False

An interrupt is a mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing. An interrupt is planned, but an unscheduled event. Typically, the interrupt is of lower priority than routine program execution. T/F

False

Assemblers are the simplest of all programming tools. They translate mnemonic instructions to machine code. Most assemblers carry out this translation in three passes over the source code. Assembly language is considered a "second generation" programming language (2GL). T/F

False

Bytes can be conveyed from one point to another by sending their encoding signals simultaneously using parallel data transmission or by sending them one bit at a time in serial data transmission. In parallel data transmission, the interface requires one conductor for each bit. Parallel cables are typically less expensive than a serial cable for the same cable length. T/F

False

Cache replacement policies must take into account dirty blocks, those blocks that have been updated while they were in the cache. Write back (also called copyback) updates memory only when the block is selected for replacement. This provides for more memory traffic than other techniques. T/F

False

Dynamic RAM (DRAM) stores logic values using capacitive effects. The effects slowly leak charge over time and must be refreshed every few nanoseconds (ns) to prevent data loss. T/F

False

Each newer language generation presents problem solving tools that are farther away from how people think and closer to how the machine implements the solution. T/F

False

In the memory hierarchy concept, main memory is accessed by content; whereas, cache memory is typically accessed by an address. T/F

False

Java programs (classes) execute within a virtual machine, the Java Virtual Machine (JVM). Because the JVM performs so many tasks at run time, its performance surpasses the performance of a traditional compiled language. T/F

False

Memory addresses consists of two parts: the memory bank (chip) select address and the specific memory address within a given memory chip. With high-order interleaving, the low order bits of the address specify which memory bank contains the address of interest. T/F

False

Random Access Memory (RAM) is volatile. That is it loses its memory when power is removed. It has limited use within computer applications. T/F

False

Registers hold data that can be readily accessed by the CPU. A register is typically implemented using D flip-flops. Data stored in main memory may be accessed more quickly than data stored in a CPU register. T/F

False

Stack arithmetic requires the use infix notation T/F

False

The cache memory purpose is to speed up accesses by storing recently used data closer to theCPU, instead of main memory. The cache memory is smaller than main memory and its accesstime is a fraction of that of main memory (much faster). The cost to store a bit in cache memory isalso much less expensive than main memory. T/F

False

The internet is a little-endian based system: T/F

False

There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into read-only memory (ROM). In microprogrammed control, the instruction microcode produces control signal changes. The resulting microprogram is stored in firmware. This extra level of instruction interpretation is what makes microprogrammed control faster than hardwired control. T/F

False

Direct Memory Access (DMA)

Offloads I/O processing to a special-purpose chip that takes care of the details

For registers: contain the address of the next instruction to be executed

PC

Programmed I/O

Reserves a register for each I/O device. Each register is continually polled to detect data arrival.

Pipeline hazards arise that cause pipeline conflicts and stalls. An instruction pipeline may stall or be flushed for what reasons?

Resource conflicts, data dependencies, and conditional branching

For registers: contains the address of the next available memory location on the stack

SP

Clock speed should not be confused with overall CPU performance. There are many other factors that contribute to the throughput of a computer's assigned task. Which of the following do not contribute to the CPU's performance?

The FLOP (floating operations per second) rating of the CPU

A computer is a large synchronous machine. The events are synchronized in a computer via the leading edge of the clock time base. T/F

True

An entire block of data is copied to cache after a hit in memory because the principle of locality tells usthat once a byte is accessed, it is likely that a nearby data element will be needed soon. T/F

True

As compared to polling techniques, an interrupt is a time efficient method of responding to external stimuli. When an external event occurs, interrupt specific processing (i.e. an interrupt service routine - ISR) is executed. T/F

True

Cache replacement policies must take into account dirty blocks, those blocks that have been updated while they were in the cache. Write through updates cache and main memory simultaneously on every write. T/F

True

Channel I/O is distinguished from DMA by the intelligence of the Input/Output Processors (IOPs). The IOP negotiates protocols, issues device commands, translates storage coding to memory coding, and can transfer entire files or groups of files independent of the host CPU. T/F

True

Direct Memory Access (DMA) runs at a higher priority and steals memory cycles from the CPU. During a DMA transfer the CPU is bypassed. T/F

True

Dynamic RAM (DRAM) is "cheap" memory owing to its simple design. DRAM enjoys high bitdensity -- that is, more memory capacity per unit area as compared to Static RAM (SRAM). T/F

True

In Big endian machines store the most significant byte first (at the lower address): T/F

True

In Redundant Array of Independent Disks (RAID), data is stored across many disks, with extra disks added to the array to provide error correction (redundancy). A higher RAID level does not necessarily mean a "better" RAID level. T/F

True

In a general purpose register (GPR) architecture, registers are used instead of memory. This results in longer (wider) instructions. Most systems today use the GPR approach. Operand access from registers is much faster than memory access: T/F

True

In a stack architecture, instructions and operands are implicitly taken from the stack: T/F

True

In an accumulator architecture, one operand of a binary operation is implicitly in the accumulator: T/F

True

Low cost is the major advantage of hard disks; however, their limitations include: they are very slow compared to main memory, they are fragile, and the moving parts wear out. T/F

True

Many operating systems provide protected environments that isolate processes, or groups of processes from each other. Three common approaches to establishing protected environments are virtual machines, subsystems, and partitions. T/F

True

Memory hierarchy involves registers, cache, main memory, and virtual memory. Registers are storage locations near the processor itself. T/F

True

Memory is constructed of random access memory (RAM) chips. Memory may be viewed as a linear array of addressable storage cells that are similar to registers.

True

Process management lies at the heart of operating system services. The operating system creates processes, schedules their access to resources, deletes processes, and deallocates resources that were allocated during process execution. T/F

True

Read-Only-Memory (ROM) is non-volatile. That is it retains contents even during power failure. It is used for permanent storage applications such as microprogramming, library subroutines, systems programs (BIOS), and function tables. T/F

True

Solid State Drive (SSD) access time and transfer rates are significantly faster than magnetic disk, but much slower than onboard main memory (RAM). The primary advantage of SSD over hard drives is there are no moving parts. T/F

True

Stack machines use one - and zero-operand instructions. PUSH and POP stack operations involve only the stack's top element T/F

True

Static RAM (SRAM) consists of circuits similar to the D flip-flop. It is a very fast memory as compared to DRAM and doesn't need to be refreshed. It is primarily used to build cache memory

True

The arithmetic logic unit carries out logical and arithmetic operations as directed by the control unit. T/F

True

There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into read-only memory (ROM). In hardwired control, the instruction machine code bit pattern in the IR is decoded by combinational logic. The decoder output works with the control signals of the current system state to produce a new set of control signals. The control signals are routed to registers, the data path, and the ALU to execute the specific instruction. T/F

True

There are two different methods of processing multiple, simultaneous interrupt events: disabling interrupts and establishing interrupt priorities. In the disabling interrupt technique, interrupts are serviced in the order that they are received by the processor. T/F

True

There are two different methods of processing multiple, simultaneous interrupt events: disabling interrupts and establishing interrupt priorities. When using defined priorities, lower priority interrupts can be interrupted by higher priority interrupts. When the higher priority interrupt has been serviced, the processor returns to the previous lower priority interrupt. T/F

True

Variable size partitioning for virtual memory swapping allocates exactly the required memory to aprocess. This leads to holes within the memory space. One technique to solve this challenge isfrom time to time go through memory and move all hole into one free block (disk de-fragmentation). T/F

True

Virtual memory enhances performance by providing greater memory capacity, without the expense of adding main memory. A portion of a disk drive serves as an extension of main memory. T/F

True

Virtual memory is memory that appears to exist as main storage (RAM) although most of it is supported by data held in secondary storage (hard drive). This technique extends the address space from RAM to the hard drive. T/F

True

n memory-mapped I/O, devices and main memory share the same address space. Each I/O device has its own reserved block of memory. Memory-mapped I/O therefore looks just like a memory access from the point of view of the CPU. T/F

True

Indexed Addressing

Uses a register as an offset, which is added to the address in the operand to determine the effective address of the data

Immediate addressing

data is part of the instruction

(Between multiplexed, dedicated, or both) has better overall performance

dedicated

(There are four different approaches to CPU short term scheduling.) jobs are serviced in arrival sequence and run to completion if they have all of the resources they need

first-come, first served

Indirect Addressing

gives the address of the address of the data in the instruction

(Between multiplexed, dedicated, or both) has fewer lines for the same application

multiplexed

(Between multiplexed, dedicated, or both) time shares address and data lines

multiplexed

(There are four different approaches to CPU short term scheduling.)preempts a job with a lower priority when a higher-priority job needs the CPU

priority scheduling

Register Indirect Addressing

register stores the address of the address of the data

(There are four different approaches to CPU short term scheduling.)each job is allotted a certain amount of CPU time. A context switch occurs when the time expires.

round robin scheduling

Two operating system components are crucial: the kernel and the system programs. The kernel performs which of the following functions: scheduling, synchronization, memory management interrupt handling, provides security and protection

scheduling, synchronization, memory management, interrupt handling, provides security and protection

Which type of scheduler selects which process should be executed next by the CPU?

short term

Thrashing occurs in memory paging when too many processes are used with too little memory. The Operating System spends all its time swapping pages rather than performing real work. This may be remedied by doing the following:

use a good page replacement algorithm, reduce number of processors running, and equip the computer with a larger main memory.

A shorter program (fewer program steps) always runs faster: T/F

False

For registers: connected to address bus, specifies address for read or write operation

MAR

There are a number of electromechanical properties of hard disk drives that determine how fast its data can be accessed. The overall access time is the sum of seek time and rotational delay. Rotational delay is the time that it takes for a disk arm to move into position over the desired cylinder; whereas, seek time is the time that it takes for the desired sector to move into position beneath the read/write head. T/F

False

Which bus width determines the range of integers that may be stored in the computer?

Data

Register Addressing

Data is located in a register

A bus is a set of wires that simultaneously conveys a single bit along each line. Buses consist of:

Data lines, control lines, and address lines

A least recently used (LRU) algorithm keeps track of the last time that a block was assessed and evicts the block that was used most recently by the CPU. T/F

False

For registers: holds the memory address constant during memory operations

MAR

For registers: connected to data bus, holds data to write or last data read

MBR

For registers: storage register for data coming in and out of memory

MBR