CS2200 Exam 1

Z register

- 1 bit reg - has a zero detect combination logic in front of it to see whether the val on the bus is equal to 0

LC2200 instruction set

- 32 bit, register-oriented, little endian - fixed length instruction format - 16 registers - a separate pc reg - 2^32 * 32 bit addressability

step 8 of CC:

- After function logic, callee stores result in $vo and on stack (if using $vo) addi $v0, $0, return-val

push $ra

addi $sp, $sp, -1 #make space on stack sw $ra, 0($sp)

translation stack

- Problem (sort a list) - Algorithm (qsort) - Program (c, Java) - Instruction Set Architecture, ISA (LC3, ARM) - Microarchitecture, data path (Core March, r2000) - Circuits (CMOS, ECL) - Devices, transistors (MOSFET)

Interrupts

- a hardware mechanism for alerting the processor that something external to the program is happening and needs attention - ex: client click

Client

- a separate software component for each player in a game or user

Single bus design

- a single set of wires shared by all the datapath elements - lc 2200 - ex: group meeting; only one person can talk at a time while everyone else listens

R-type instructions

- add and nand

I-type instructions

- addi, lw, sw, beq

step 12 of CC:

- after caller jalr: caller restores $ra lw $ra, 0($sp) addi $sp, $sp, 1

fixed width encoding

- all instructions have length of one word - pros: simplifies implementation, interpretation is faster - cons: potential wasted space, need additional logic like decoders and multiplexers to figure out which instruction it is, all instructions are limited to the fixed length

interrupt handler

- already disabled addi $sp, $sp, -1 sw $k0, 0($sp) EI //handler code DI lw $k0, 0($sp) addi $sp, $sp, 1 reti

$a0 - $a2 reg

- arguments for function

$at reg

- assembler's temp - holds target address - when doing recursion this will hold the address of the function when recursing

level logic

- associated with latches - changes states when the clock signal is high

beq

- beq r1, r2, L1 - compares r1 and r2; if equal jump to L1 address - range is limited to bit-size - for lc2200 bit size is 16 --> range is 16 lines

step 5 of CC:

- called calls callee jalr $at, $ra - assuming function address is already loaded into $at la $at, fib

step 7 of CC:

- callee pushes any $s regs it will use (local variables) addi $sp, $sp, -1 sw $s0, 0($sp)

step 9 of CC:

- callee restores any saved regs lw $s0, 0($sp) addi $sp, $sp, 1

step 10 of CC:

- callee restores old $fp lw $fp, 0($sp) addi $sp, $sp, 1

step 11 of CC:

- callee returns jalr $ra, $0

step 6 of CC:

- callee saves $fp, sets $fp to $sp addi $sp, $sp, -1 sw $fp, 0($sp) addi $fp, $sp, 0

step 3 of CC:

- caller allocates space for return value if it is larger than the size of $v0 addi $sp, $sp, -1

step 13 of CC:

- caller discards any extra args used addi $sp, $sp, 2

step 4 of CC:

- caller pushes $ra addi $sp, $sp, -1 sw $ra, 0($sp)

Step 2 of the CC:

- caller pushes the paramaters for the function addi $a0, $0, 10 addi $a1, $0, 20 addi $a2, $0, 30 - don't need to increment $sp

step 14 of CC:

- caller restores $t regs lw $t0, 0($sp) addi $sp, $sp, 1

Step 1 of the calling convention:

- caller saves any t registers needed addi $sp, $sp, -1 sw $t0, 0($sp)

Server

- central software component that maintains state

Immediate values

- constant values. ex: 0, 1, 8

$zero reg

- constant, unwritable, 0, null

Registers

- describe resources available within a processor - physically close to the ALU so they are faster than memory - if operands are in registers, they are faster to access than if they were in memory

HLL expressions and assignment statements

- ex: a = b + c - for ISA: ADD a, b, c

DECODE macrostate

- examine contents in IR[31:28] to figure out what the instruction is

How are servers and clients connected?

- executed on different machines and connected by a *local area network*

PC-relative addressing mode

- find address of next instruction by adding PC + offset - ex: BEQ r1, r2, offset --> will go to the address at PC (address of this beq instruction) + offset (what LC3 used)

Control unit

- finite state machine - takes the datapath through successive stages in order to accomplish instructions - FETCH, DECODE, EXECUTE

edge-triggered logic

- flip-flop - changes states on the rising (positive edge-trigger) or falling (negative edge-trigger) edge of the clock

$k0

- for the os - don't really use

$fp

- frame pointer - callee save

Draw hardware side of level of abstraction

- from bottom --> up - lowest level is *electrons and holes* - the electrons are then sent through *transistors* - transistors form *logic gates* - logic gates make up the *logic elements* - all of the logic elements creates the cpu's *datapath* - After going through the datapath, the *instruction set* is created

stack grows from _____ to ______

- grows from high to low - stack pointer starts here and points to lower addresses when moving

o-type instructions

- halt

Zero - operand instructions

- halt, nop

Operating system importance in level of abstraction

- handles the interrupts from clients - it fields the interrupt, recognizes which program the interrupt is for (client or server), and then sends a message to that program - the corresponding program sends a message to any other programs connected to it (if client, sends message to server) - OS updates states after processing message

State reg

- hold the encoding of the microstates needed to execute an instruction like FETCH

MAR

- holds the address sent by the ALU to the mem

j-type instructions

- jalr

packing

- laying out the operands in memory, ensuring no wasted space - also reduces number of memory accesses

Little endian

- least significant byte first - ex: 0x12345678 would be stored as 78 - 56 - 34 - 12 - word order stays the same but byte order changes

Base+index addressing mode

- let the effective addressing be computed by the sum of two registers - lw r3, r1(r2) --> load what is in memory at r1 + r2 into r3

Step 0 of Calling convention:

- load address of stack into $sp la $sp, stack - load value of stack into $sp lw $sp, 0($sp)

lw vs sw

- load: into registers from mem - store: from registers to mem

base + offset addressing mode

- memory address is computed in the instruction - equals the sum of the contents of a reg and an immediate value offset from that reg - ex: lw r2, offset(rb); put what is in offset + rb into r2

Big endian

- most significant byte first - ex: 0x12345678 would be stored as 12 - 34 - 56 - 78

combinational logic

- no concept of a state (no memory) - basic logic gates (AND, OR, ect) - ex: key lock

drivers or tristate buffers

- one driver for each wire coming from a datapath element - prevents shorts from happening - in order to electronically connect the datapath element to the bus, the corresponding driver needs to be on - DrReg, DrMem

Program Counter (PC)

- points to the currently executing instruction - is incremented after each instruction

Adressing mode

- refers to how the operands are specified in an instruction - register addressing is when operands are in registers

$ra

- return address - caller save

$v0 reg

- return val

Registers $s0 - $s2

- saved registers - callee saved - used for when a function has more than 3 args

Accessing array components

- say we have an array = a[100] (size is 100) - we load the array into r1 - to get a[7] into r2--> lw r2, 28(r1) - go 28 bits after the address of r1 to get a[7]

aligned access

- says how memory should be packed so that there is no extra memory accesses - ints need to be on their own word since an int is one word long - char's and shorts can share a word as long as a short isnt spilling over into another word - may lose space, but is more efficient

WrEn signal

- signal for each datapath - in order to receive what is on the bus, this needs to be turned on - multiple WrEn signals can be turned on to get the signal in one clock cycle

Addressability

- smallest precision operand that can be individually adressed in mem - byte addressability = one byte for each address - if addressability is large --> takes more space in mem

$sp

- stack pointer - callee save

Draw software side of level of abstraction

- start with application - connected to HLL source program - compiler translates it to an instruction set that can be understood by a processor - compiler also sends information back to application (should point to both)

Registers $t0 - $t2

- temp registers - caller saved

Memory footprint

- the amount of space occupied by a program in memory

Caller

- the entity that makes the call - ex: main

What is the meeting point of software and hardware?

- the instruction set - serves as the abstraction needed by the compiler to generate the code that is run on the processor

Callee

- the procedure that is being called - ex: function foo()

Registers and clock cycle

- to write to a reg, the input has to be stable for some amount of time before the rising edge - it has to continue to be stable for some time after the rising edge - can only read or write to one reg at a time during one clock cycle bc of this

Two bus design

- two wires connecting the data structures - two registers can be read and supplied to the ALU in the same clock cycle

step 2 if more than three args:

- use s registers for extra arguments: addi $s0, $0, $40 - need to push any s registers on the stack: addi $sp, $sp, -1 sw $s0, 0($sp) - if doing more than one, push in reverse order: sw $s1, 1($sp) sw $s0, 0($sp)

What does the ISA define?

- uses hardware resources to do different things in the processor - specifies the capabilities of the machine - contract b/w the software and processor

Sequential logic

- uses the current inputs to determine the state of the circuit - flip-flop important for logic - ex: combinational lock

word vs half-word vs byte

- word = 32 bits - half-word = 16 bits - byte = 8 bits

Binary/three-operand instructions

- work on two operands to produce a result - ex: a = b + c; ADD a,b,c

HLL feature set (4) and they're relation to ISA

1. *Expressions and assignment statements* 2. *high-level data abstractions* 3. *Conditional statements and loops* 4. *Procedural calls*

FETCH macrostate

1. DrPC, LdMar, LdA 2. DrMEM, LdIR 3. func = 11, DrALU, LdPC

JALR macrostate

1. DrPC, RegSel = 01, WrReg 2. RegSel = 00, DrREG, LdPC

ADD macrostate

1. RegSel = 01, DrReg, LdA 2. RegSel = 10, DrReg, LdB 3. func = 00, DrALU, RegSel = 00, WrREG

LW macrostate

1. regsel = 01, DrReg, LdA 2. DrOFF, LdB 3. func = 00, DrALU, LdMAR 4. DrMem, RegSel = 00, WrReg

instructions when an interrupt happens

DI $k0 = pc

pop $ra

lw $ra, 0($sp) addi $sp, $sp, 1 #get rid of space on stack