CSA Final with answers
square[i][j] what is a miss rate
12.5%
28. How many generations semiconductor memory has been through, since 1970? (please write number)
13
square[i][j] number of writes that hit
224
square[j][i] number of writes that hit and miss
256
square[j][i] number of writes that miss
64
What is the description(s) of Transistors? A. A semiconductor device used to amplify electronic signals and electrical power. B. A semiconductor device used to switch electronic signals and electrical power. C. A semiconductor device used to amplify or switch electronic signals and electrical power. D. A semiconductor device used to reduce or switch electronic signals and electrical power. E. A semiconductor device used to reduce or combine electronic signals and electrical power.
A. A semiconductor device used to amplify electronic signals and electrical power. B. A semiconductor device used to switch electronic signals and electrical power. C. A semiconductor device used to amplify or switch electronic signals and electrical power.
12. Algorithm for Cache MISS: • Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
79. At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache "Order of fill": o 0,1,2,3,4,5,6,7 o 3,4,5,6,7,0,1,2
• 0,1,2,3,4,5,6,7
66. Which digits are used in octal number system? o 0-7 o 0 and 1 o 0-9 o All digits
• 0-7
36. Which of the following is the right result for this operation: 11001+110001= o 10101010 o 10101110 o 01001010 o 01100110 o 10001010
• 01001010
37. Convert decimal 230 to the binary: o 011000110 o 011100110 o 101100110 o 011100110
• 011100110
41. How many issue queue used in Centralized Superscalar 2 and Exceptions? o 4 o 3 o 2 o 1
• 1
124. Systems alternate between two states of service with respect to an SLA: o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
• 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
46. Which of the following is the result of the binary multiplication: 100010*100101= o 11011101010 o 10111101010 o 10010001010 o 10010101010 o 10011101010
• 10011101010
38. Convert binary 1100111 to decimal: o 103 o 100 o 95 o 130 o 110
• 103
30. Clock Frequency of SDRAM is equal to: o 200 o 600 o 300 o 166 o 156
• 166
56. Choose the years of the first generation computer architecture o 1958-1964 o 1964-1974 o 1974-present o 1945-1964 o 1945-1958
• 1945-1958
57. Choose the years of the second generation computer architecture o 1945-1958 o 1964-1974 o 1974-present o 1945-1964 o 1958-1964
• 1958-1964
42. How many issue queue used in Distributed Superscalar 2 and Exceptions: o 4 o 3 o 1 o 2
• 2
43. How many instructions used in Distributed Superscalar 2 and Exceptions? o 4 o 3 o 2 o 1
• 2
73. Into how many parts a program (or algorithm) which can be parallelized can be split up? o 3 o 4 o 5 o 2
• 2
105. How many size of Cache L2 is true approximately? : o 256 KB o 4 KB o 32 MB
• 256 KB
107. How many main levels of Cache Memory? o 3 o 2 o 6 o 8
• 3
129. How many access methods are there? o 3 o 2 o 4 o 5 o 6
• 3
190. How many policy conditions for deadlock to be possible are there? o 3 o 4 o 2 o 5 o 1
• 3
199. How many approaches of mutex implementation are there? o 3 o 4 o 2 o 5 o 1
• 3
209. How many categories of process management are there? o 3 o 2 o 4 o 5 o 1
• 3
106. How many size of Cache L3 is true approximately? : o 3 MB o 256 MB o 256 KB
• 3 MB
80. At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first "Order of fill": o 3,4,5,6,7,0,1,2 o 0,1,2,3,4,5,6,7
• 3,4,5,6,7,0,1,2
42. Convert hexadecimal value: DAD to decimal: o 3500 o 3501 o 4501 o 4500 o 3503
• 3501
43. Convert decimal value: 877 to hexadecimal: o 36D o 38A o 36B o 38C o 36A
• 36D
141. How many fields contains the entry in the ROB: o 4 o 5 o 6 o 3
• 4
179. How many deadlock recovery algorithms are there? o 4 o 3 o 2 o 5 o 1
• 4
34. How many number systems are exist? o 4 o 3 o 2 o 1 o 5
• 4
55. How many generations of computer architecture are there? o 4 o 3 o 2 o 1 o 5
• 4
61. How many number systems are there? o 1 o 2 o 3 o 4
• 4
123. The most companies spend only ____________ of their income on R&D, which includes all engineering. o 4% to 12% o 15% to 30% o 1% to 17% o 30% to 48%
• 4% to 12%
131. How many performance factors are there o 5 o 4 o 3 o 2 o 6
• 5
135. How many physical characteristics of disk systems are there? o 4 o 5 o 2 o 3 o 6
• 5
31. An instruction pipeline increases the performance of a processor by overlapping the processing of several different instructions. How many stages it is consist of: o 6 o 3 o 5 o 7 o 4
• 5
50. How many stages used in Superscalar (Pipeline)? o 5 o 4 o 6 o 7
• 5
47. Convert the binary value: 111011 to decimal o 59 o 58 o 56 o 60 o 69
• 59
123. How many elements of cache design are there? o 2 o 5 o 4 o 6 o 7
• 7
104. How many size of Cache L1 is true approximately? : o 8 KB o 256 KB o 2 MB
• 8 KB
12. The world's first general-purpose microprocessor. It was used in the first personal computer, the Altair. o 8070 o 8080 o 8086 o 8090
• 8080
127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code. o 90% 10% o 50% 50% o 70% 30% o 89% 11%
• 90% 10%
169. Which symbol you should use to leave the variable uninitialized o ? o ! o @ o $
• ?
164. Choose the legal name(s) in assembly o @variable_name o variable? o variable&name o variable name o 1variable
• @variable_name • variable?
175. Choose the definition of stack segment in assembly o A block of memory to store a stack o All variable definitions o Contains a program's instructions
• A block of memory to store a stack
86. Choose the right formula for AMAT o AMAT = Hit time + Miss rate + Miss penalty o AMAT = Hit time * Miss rate + Miss penalty o AMAT = Hit time * Miss rate * Miss penalty o AMAT = Hit time + Miss rate * Miss penalty
• AMAT = Hit time + Miss rate * Miss penalty
120. For random-access memory, the time it takes to perform a read or write operation is called o Clock Rate o CPI o Access Time o Latency
• Access Time • Latency
227. For random-access memory, this is the time it takes to perform a read or write operation o Access time o Memory cycle time o Transfer rate o Performance o All of the above
• Access time
153. What is included into performance characteristic of computer memory systems? o Access time o Cycle Time o Transfer Rate o Word o Number of bytes o Number of words
• Access time • Cycle Time • Transfer Rate
136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias o Achievable ILP with software resource constraints o Limited ILP due to software dependences o Achievable ILP with hardware resource constraints o Variability of ILP due to software and hardware interaction
• Achievable ILP with software resource constraints
148. Choose the component of SSD for the following definition: Logic that performs the selection function across the flash memory components o Addressing o Flash Memory Components o Data buffer/cache o Controller o Error Correction
• Addressing
66. What is an ALAT? : o Advanced Load Address Table o Allocated Link Address Table o Allowing List Address Table o Addition Long Accessibility Table
• Advanced Load Address Table
174. Choose the definition of data segment in assembly o All variable definitions o A block of memory to store a stack o Contains a program's instructions
• All variable definitions
67. At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches: o Allow one instruction to branch multiple directions o Speculative operations that don't cause exceptions
• Allow one instruction to branch multiple directions
88. What is a RAID 1? o Also called mirroring or shadowing, there are two copies of every piece of data o It has no redundancy and is sometimes nicknamed JBOD, for "just a bunch of disks," although the data may be striped across the disks in the array o This organization was inspired by applying memory-style error correcting codes to disks
• Also called mirroring or shadowing, there are two copies of every piece of data
13. Which of the following laws deals with the potential speedup of a program using multiple processors compared to a single processor. o Moor's Law o Little's Law o Murphy's law o Amdahl's law
• Amdahl's law
15. Data Hazard: o An instruction depends on a data value produced by an earlier instruction o An instruction in the pipeline needs a resource being used by another instruction in the pipeline o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
• An instruction depends on a data value produced by an earlier instruction
14. Structural Hazard: o An instruction in the pipeline needs a resource being used by another instruction in the pipeline o An instruction depends on a data value produced by an earlier instruction o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
• An instruction in the pipeline needs a resource being used by another instruction in the pipeline
45. What is a ARF: o Architectural Register File o Architecture Relocation File o Architecture Reload File o Architectural Read File
• Architectural Register File
80. In which cache memory mapping technique any block from main memory can be placed anywhere in the cache? o Associative Mapping o Set Associative Mapping o Direct Mapping
• Associative Mapping
77. How a memory unit accessed by contents is called? o Associative Memory o Content Addressable Memory o Auxiliary Memory o Cache Memory o Virtual Memory
• Associative Memory • Content Addressable Memory
84. Which type of memory accessed via the input/output channels? o Main Memory o Cache Memory o Virtual Memory o Auxiliary Memory o Secondary Memory
• Auxiliary Memory • Secondary Memory
103. Little's Law and a series of definitions lead to several useful equations for "Length queue" -: o Average length of queue o Average number of tasks in service
• Average length of queue
40. Little's Law and a series of definitions lead to several useful equations for "Length queue" -: o Average length of queue o Average number of tasks in service
• Average length of queue
24. AMAT stands for: o Average memory access time o Automatic Message Accounting Transmitter o Asymptotic Mean Acquisition Time o Absolute memory access time
• Average memory access time
102. Little's Law and a series of definitions lead to several useful equations for "Length server" - : o Average number of tasks in service o Average length of queue
• Average number of tasks in service
39. Little's Law and a series of definitions lead to several useful equations for "Length server" - : o Average number of tasks in service o Average length of queue
• Average number of tasks in service
100. Little's Law and a series of definitions lead to several useful equations for "Time queue" - : o Average time per task in the queue o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
• Average time per task in the queue
37. Little's Law and a series of definitions lead to several useful equations for "Time queue" - : o Average time per task in the queue o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
• Average time per task in the queue
36. Little's Law and a series of definitions lead to several useful equations for "Time server" - : o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time per task in the queue o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
• Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
99. Little's Law and a series of definitions lead to several useful equations for "Time server" - : o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time per task in the queue o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
• Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
101. Little's Law and a series of definitions lead to several useful equations for "Time system" - : o Average time/task in the system, or the response time, which is the sum of Time queue and Time server o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time per task in the queue
• Average time/task in the system, or the response time, which is the sum of Time queue and Time server
38. Little's Law and a series of definitions lead to several useful equations for "Time system" - : o Average time/task in the system, or the response time, which is the sum of Time queue and Time server o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts o Average time per task in the queue
• Average time/task in the system, or the response time, which is the sum of Time queue and Time server
96. Select cache optimizations to reduce hit time (both basic and advanced) o Avoiding Address Translation during Cache Indexing o Small and Simple First-Level Caches o Way Prediction o Compiler Optimizations o Compiler-Controlled Prefetching
• Avoiding Address Translation during Cache Indexing • Small and Simple First-Level Caches • Way Prediction
9. Using this technique processor looks ahead in the instruction code fetched from memory and predicts which groups of instructions are likely to be processed next. o Branch prediction o Data flow analysis o Pipelining o Speculative execution
• Branch prediction
2. Controls the operation of the computer and performs its data processing functions: o Main memory o I/O o CPU o System interconnection
• CPU
68. What is time elapsed to program execution? o CPU Time o User time + OS Time o I/O waiting & Other programs o CPU Time + I/O waiting & Other programs
• CPU Time + I/O waiting & Other programs
75. Non-Blocking Cache Timeline for "Hit Under Miss" the sequence is -? o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time o CPU time-Cache Miss-Miss Penalty-CPU time o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
• CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
76. Non-Blocking Cache Timeline for "Miss Under Miss" the sequence is -? o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time o CPU time-Cache Miss-Miss Penalty-CPU time o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
• CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
74. Non-Blocking Cache Timeline for "Blocking Cache" the sequence is - ? o CPU time-Cache Miss-Miss Penalty-CPU time o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
• CPU time-Cache Miss-Miss Penalty-CPU time
85. Which type of memory stores frequently used data? o Main Memory o Virtual Memory o Auxiliary Memory o Secondary Memory o Cache Memory
• Cache Memory
125. Choose the element(s) of cache design o Tag o Latency o AMAT o Cache Size o Line Size o Number of Caches
• Cache Size • Line Size • Number of Caches
226. A state in which data requested for processing by a component or application is found in the cache memory o Cache hit o Cache miss o Cache set o Cache overwrites o Cache access time
• Cache hit
113. Choose the key characteristics of computer memory systems o Capacity o Performance o Organization o Instruction Fetch o Instruction Decode
• Capacity • Performance • Organization
186. Choose the correct answer for the following definition "A closed chain of processes exists, such that each process is blocked waiting for a resource held by another process in the set" o Circular wait o Mutual exclusion o No preemption o Hold and wait
• Circular wait
138. Which of these is NOT characteristics of recent highperformance microprocessors? o Color o Power o Functional unit capability o Clock rate
• Color
134. Choose the system attribute(s) by which the performance factors are influenced o Cache size o Unit of Transfer o Compiler Technology o Processor Implementation o Cache and memory hierarchy
• Compiler Technology • Processor Implementation • Cache and memory hierarchy
173. Choose the definition of code segment in assembly o Contains a program's instructions o A block of memory to store a stack o All variable definitions
• Contains a program's instructions
102. Choose hazard for the following definition: fetch cannot continue because it does not know the outcome of an earlier branch - special case of a data hazard o Control o Structural o Data
• Control
145. Choose the component of SSD for the following definition: provides SSD device level interfacing and firmware execution o Controller o Addressing o Data buffer/cache o Error correction o Flash memory components
• Controller
140. Choose the components of SSD o Controller o Addressing o Data buffer/cache o Data size o Memory hierarchy
• Controller • Addressing • Data buffer/cache
212. The time between pulses called? o Cycle time o Clock speed o Clock rate o Clock cycle
• Cycle time
67. What does CPI stand for? o Cycles Per Instruction o Clocks Per Instruction o Cycles Per Interface o Clocks Per Interface
• Cycles Per Instruction
101. Choose hazard for the following definition: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction o Data o Structural o Control
• Data
149. Choose the component of SSD for the following definition: High speed RAM memory components used for speed matching and to increased data throughput o Data buffer/cache o Flash Memory Components o Addressing o Controller o Error Correction
• Data buffer/cache
10. Which technique helps to processor investigates which instructions are dependent on each other's results, or data, to create an optimized schedule of instructions o Branch prediction o Data flow analysis o Pipelining o Speculative execution
• Data flow analysis
183. Choose the correct approach for the following definition "involves making dynamic choices that guarantee prevention" o Deadlock avoidance o Deadlock prevention o Deadlock detection and recovery
• Deadlock avoidance
182. Choose the correct approach for the following definition "involves recognizing when deadlock has occurred, and trying to recover" o Deadlock detection and recovery o Deadlock avoidance o Deadlock prevention
• Deadlock detection and recovery
184. Choose the correct approach for the following definition "adopting a static policy that disallows one of the four conditions above" o Deadlock prevention o Deadlock detection and recovery o Deadlock avoidance
• Deadlock prevention
18. Bus lines can be separated into two generic types: o Dedicated o Centralized o Distributed o Multiplexed o Synchronous o Asynchronous
• Dedicated / • Multiplexed
92. At storage systems Gray and Siewiorek classify faults what does mean "Hardware faults"? : o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell o Faults in software (usually) and hardware design (occasionally) o Mistakes by operations and maintenance personnel
• Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
82. In which cache memory mapping technique any memory block is mapped to exactly one block in the cache? o Direct Mapping o Set Associative Mapping o Associative Mapping
• Direct Mapping
23. Reduce Miss Rate: High Associativity. Empirical Rule of Thumb: o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2 o If cache size is doubled, miss rate usually drops by about √2 o None of them
• Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
206. Choose the correct answer for the following definition "multiple processes on multiple systems" o Distributed processing o Multiprogramming o Multiprocessing
• Distributed processing
32. What does DDR stands for? o Double data rate o Dual data rate o Double data reaction o None of them
• Double data rate
135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state o Dynamic power o Static power o Processing rate o Processor state
• Dynamic power
48. DRAM stands for: o Direct random access memory o Dynamic random accessible memory o Dynamical random access memory o Dynamic random access memory o Discrete random access memory
• Dynamic random access memory
145. Which Multiple-issue processors has not the hardware hazard detection: o EPIC o Superscalar(dynamic) o Superscalar(static) o Superscalar(speculative)
• EPIC
177. Which keyword you should use in order to define a constant in assembly language o EQU o DD o CONST o EQ o DW
• EQU
4. ENIAC stands for: o Electronical Numerical Integrator And Computer o Electronic Numerical Integration Analogue Computer o Electronic Numerical Integrator And Computer o Electronic Numerical Interaction And Calcuation
• Electronic Numerical Integrator And Computer
215. ENIAC stands for: o Electronic Numerical Integrator and Computer o Electronic Nuclear Integrator and Computer o Encapsulation Numerical Integrator and Commerce o Encapsulation Numerical Integrator and Computer o Electronic Numerical Integer and Computer
• Electronic Numerical Integrator and Computer
25. _____________ is a special purpose system that is used to perform one or few dedicated functions. o Distributed systems o Embedded systems o Ultra-Large-Scale Systems o Centralized systems o Ubiquitous systems
• Embedded systems
146. Choose the component of SSD for the following definition: Logic for error detection and correction o Error Correction o Addressing o Data buffer/cache o Controller o Flash memory components
• Error Correction
52. Speculating on Exceptions "Prediction mechanism" is - • Exceptions are rare, so simply predicting no exceptions is very accurate o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types o Only write architectural state at commit point, so can throw away partially executed instructions after exception o None of them
• Exceptions are rare, so simply predicting no exceptions is very accurate
53. Speculating on Exceptions "Check prediction mechanism" is - o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types o Exceptions are rare, so simply predicting no exceptions is very accurate o The way in which an object is accessed by a subject o None of them
• Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
109. What is a "Kernel" in Cache Memory? o Execution or waiting for synchronization variables o Execution in the OS that is neither idle nor in synchronization access o Execution in user code
• Execution in the OS that is neither idle nor in synchronization access
111. What is a "Kernel" in Cache Memory? o Execution or waiting for synchronization variables o Execution in the OS that is neither idle nor in synchronization access o Execution in user code
• Execution in the OS that is neither idle nor in synchronization access
113. What is a "Kernel" in Cache Memory? o Execution or waiting for synchronization variables o Execution in the OS that is neither idle nor in synchronization access o Execution in user code
• Execution in the OS that is neither idle nor in synchronization access
108. What is a "Synchronization" in Cache Memory? o Execution in the OS that is neither idle nor in synchronization access o Execution in user code o Execution or waiting for synchronization variables
• Execution or waiting for synchronization variables
110. What is a "Synchronization" in Cache Memory? o Execution in the OS that is neither idle nor in synchronization access o Execution in user code o Execution or waiting for synchronization variables
• Execution or waiting for synchronization variables
112. What is a "Synchronization" in Cache Memory? o Execution in the OS that is neither idle nor in synchronization access o Execution in user code o Execution or waiting for synchronization variables
• Execution or waiting for synchronization variables
33. _____________ is the amount of time it takes the program to perform in seconds o Elapsed time o Overall time o Estimate time o Execution time o Process time
• Execution time
103. A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called pipelining o True o False
• False
107. In execution stage identification of the operation is performed o True o False
• False
116. The "natural" unit of organization of memory is called block o True o False
• False
117. After implementing embedded systems, you can easily use them for another purposes o True o False
• False
118. Digital circuits are inflexible and slower, because they are technology dependent o True o False
• False
126. There are three types of cache addresses o True o False
• False
127. There are two types of mapping functions o True o False
• False
128. We can find needed block in associatively mapped cache by its block address o True o False
• False
142. SSDs are susceptible to mechanical wear o True o False
• False
143. SSDs are more susceptible to physical shock and vibration o True o False
• False
165. In two-operand instruction, the first operand is source and the second operand is destination o True o False
• False
166. An instruction may have one or more operands o True o False
• False
167. In assembly language you can express data only in binary and decimal o True o False
• False
178. In assembly statement name and comment are mandatory o True o False
• False
180. There are 3 approaches of deadlock avoidance o True o False
• False
185. There are 4 approaches of dealing with deadlock o True o False
• False
197. When using semaphores, processes communicate using messages o True o False
• False
202. In concurrency, locating programming errors can't be difficult, because the contexts in which errors occur cannot always be reproduced easily o True o False
• False
204. Concurrency offers genuine simultaneous execution o True o False
• False
205. Parallelism is interleaving of processes in time to give the appearance of simultaneous execution o True o False
• False
214. Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors. o False o True
• False
230. Moore's law: "The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic rate" o False o True
• False
231. Moore's law: "Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed" o False o True
• False
237. The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache o False o True
• False
58. In 1976 Apple II computer model was released o True o False
• False
63. Four bits make octal digit o True o False
• False
64. Three bits make hexadecimal digit o True o False
• False
65. Octal and hexadecimal numbers are hard on use and conversion o True o False
• False
69. The execution time of a program clearly depends on the number of instructions o True o False
• False
70. The more clock rate of processor, the faster is processor o True o False
• False
74. The time interval is called a clock rate o True o False
• False
76. Static RAM has a reduced power consumption, and a large storage capacity o True o False
• False
79. ROM is the place in a computer where the operating system, application programs, and data in current use are kept. o True o False
• False
81. In LRU replacement algorithm, the block that is in the cache longest is replaced o True o False
• False
92. In virtual memory, memory can be used efficiently because a section of program always loaded o True o False
• False
93. The advantage of virtual memory is that it takes less time to switch between applications because of additional memory o True o False
• False
97. Physical address used by program, and which OS must translate into virtual address o True o False
• False
99. Pipelining can only be implemented on hardware o True o False
• False
93. At storage systems Gray and Siewiorek classify faults what does mean "Design faults"? : o Faults in software (usually) and hardware design (occasionally) o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell o Mistakes by operations and maintenance personnel
• Faults in software (usually) and hardware design (occasionally)
85. In Non-Blocking Caches what does mean "Early restart"? o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
• Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
51. What is about Superscalar means "F-D-X-M-W"? o Fetch, Decode, Execute, Memory, Writeback o Fetch, Decode, Instruct, Map, Write o Fetch, Decode, Excite, Memory, Write o Fetch, Decode, Except, Map, Writeback
• Fetch, Decode, Execute, Memory, Writeback
47. What is a FSB? o Finished Store Buffer o Finished Stack Buffer o Finished Stall Buffer o Finished Star Buffer
• Finished Store Buffer
95. At storage systems Gray and Siewiorek classify faults what does mean "Environmental faults"? : o Fire, flood, earthquake, power failure, and sabotage o Faults in software (usually) and hardware design (occasionally) o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
• Fire, flood, earthquake, power failure, and sabotage
130. Choose the type(s) of auxiliary memory o Flash Memory o Optical Disk o Hard Drive o SSD o RAM
• Flash Memory • Optical Disk
147. Choose the component of SSD for the following definition: Individual NAND flash chips o Flash Memory Components o Addressing o Data buffer/cache o Controller o Error Correction
• Flash Memory Components
56. What is a FL? o Free List o Free Last o Free Leg o Free Launch
• Free List
129. Which of the following descriptions corresponds to static power? o Grows proportionally to the transistor count (whether or not the transistors are switching) o Proportional to the product of the number of switching transistors and the switching rate Probability o Proportional to the product of the number of switching transistors and the switching rate o All of the above
• Grows proportionally to the transistor count (whether or not the transistors are switching)
49. How is called the permanent physical defect when the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1? o Soft error o Hard error o Hard failure o Soft failure o Epic failure
• Hard failure
95. Choose advanced cache optimizations o Giving Reads Priority over Writes o Larger Cache Size o Hardware Prefetching of Instructions and Data o Merging Write Buffer o Critical Word First and Early Restart
• Hardware Prefetching of Instructions and Data • Merging Write Buffer • Critical Word First and Early Restart
65. Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling: o Hardware to check pointer hazards o Speculative operations that don't cause exceptions
• Hardware to check pointer hazards
60. Choose two types of models for a computing machine o Harvard architecture o Von Neumann architecture o Oxford architecture o Stanford architecture
• Harvard architecture / • Von Neumann architecture
137. Choose the physical characteristic(s) of disk systems o Disk system implementstion o Disk Size o Head Mechanism o Head Motion o Disk Portability
• Head Mechanism • Head Motion • Disk Portability
136. Choose the physical characteristic(s) of disk systems o Head Mechanism o Platters o Disk Size o Sides o Disk system implementstion
• Head Mechanism • Platters • Sides
53. Choose the feature(s) of second generation computer architecture o High level languages o Transistors o 2 Kb memory, 10 KIPS o 2 Mb memory, 5 MIPS o Different types of supported instructions
• High level languages / • Transistors
7. Average Memory Access Time is equal: o Hit Time * ( Miss Rate + Miss Penalty ) o Hit Time - ( Miss Rate + Miss Penalty ) o Hit Time / ( Miss Rate - Miss Penalty ) o Hit Time + ( Miss Rate * Miss Penalty )
• Hit Time + ( Miss Rate * Miss Penalty )
188. Choose the correct answer for the following definition "A process may hold some resources while waiting for others" o Hold and wait o Mutual exclusion o Circular wait o No pre-emption
• Hold and wait
22. Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb: o If cache size is doubled, miss rate usually drops by about √2 o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2 o None of them
• If cache size is doubled, miss rate usually drops by about √2
131. Which of the written below is NOT increase power consumption? o Increasing multithreading o Increasing performance o Increasing multiple cores o Increasing multithreading
• Increasing multithreading
86. A virus classification by target includes the following categories, What is a File infector? o Infects files that the operating system or shell consider to be executable o A typical approach is as follows o The key is stored with the virus o Far more sophisticated techniques are possible
• Infects files that the operating system or shell consider to be executable
132. Choose the performance factor(s) o Cache Size o Line Size o Instruction Count o Number of Processor Cycles o Mapping function o Latency
• Instruction Count • Number of Processor Cycles
133. Choose the performance factor(s) o Cache Size o Line Size o Instruction Count o Number of Processor Cycles o Number of memory references
• Instruction Count • Number of Processor Cycles • Number of memory references
104. Stage in which the instruction is fetched from memory and placed in the instruction register called o Memory read/write o Instruction Decode o Execution o Write Back o Instruction Fetch
• Instruction Fetch
44. Which of the following formula is true about Issue Queue for "Instruction Ready": o Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards o Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
• Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
219. Employed to hold temporarily the right-hand instruction from a word in memory o Instruction buffer register (IBR) o Memory buffer register (MBR) o Memory address register (MAR) o Instruction register (IR) o Program counter (PC)
• Instruction buffer register (IBR)
213. A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f: o Instruction execution rate o Instruction execution cycle o Instruction execution time o Instruction execution period o None of the above
• Instruction execution rate
218. Contains the 8-bit opcode instruction being executed o Instruction register (IR) o Memory buffer register (MBR) o Memory address register (MAR) o Instruction buffer register (IBR) o Program counter (PC)
• Instruction register (IR)
60. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic? o Integer Datapath o CLK o Free List o Address Queue
• Integer Datapath
154. What does IDE stand for?
• Integrated Development Environment
57. What is an IQ? o Issue Queue o Internal Queue o Interrupt Queue o Instruction Queue
• Issue Queue
87. What is a RAID 0? o It has no redundancy and is sometimes nicknamed JBOD, for "just a bunch of disks," although the data may be striped across the disks in the array o Also called mirroring or shadowing, there are two copies of every piece of data o This organization was inspired by applying memory-style error correcting codes to disks
• It has no redundancy and is sometimes nicknamed JBOD, for "just a bunch of disks," although the data may be striped across the disks in the array
146. Examples of EPIC: o Itanium o Pentium 4, MIPS R12K, IBM, Power5 o MIPS and ARM o TI C6x
• Itanium
75. What does LRU stand for? o Least Right Used o Last Recently User o Last Recently Used o Least Recently Used
• Least Recently Used
112. Choose the key characteristics of computer memory systems o Stalling o Unit of Transfer o Hazards o Location o Access Method
• Location • Unit of Transfer • Access Method
62. At VLIW by "performance and loop iteration" which time is longer? o Loop Unrolled o Software Pipelined
• Loop Unrolled
111. Floating point performance is expressed as o CPI o FLOPS o MIPS o MFLOPS
• MFLOPS
110. A common measure of performance for a processor is the rate at which instructions are executed, called o CPI o Clock Rate o MFLOPS o MIPS
• MIPS
147. Examples of superscalar(static): o MIPS and ARM o Pentium 4, MIPS R12K, IBM, Power5 o Itanium o TI C6x
• MIPS and ARM
91. What is a RAID 4? o Many applications are dominated by small accesses o Since the higher-level disk interfaces understand the health of a disk, it's easy to figure out which disk failed o Also called mirroring or shadowing, there are two copies of every piece of data
• Many applications are dominated by small accesses
124. Choose the element(s) of cache design o Tag o Latency o AMAT o Mapping Function o Replacement Algorithm o Number of Caches
• Mapping Function • Replacement Algorithm • Number of Caches
217. Specifies the address in memory of the word to be written from or read into the MBR o Memory address register (MAR) o Memory buffer register (MBR) o Instruction register (IR) o Instruction buffer register (IBR) o Program counter (PC)
• Memory address register (MAR)
216. Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit o Memory buffer register (MBR) o Memory address register (MAR) o Instruction register (IR) o Instruction buffer register (IBR) o Program counter (PC)
• Memory buffer register (MBR)
225. The basic element of a semiconductor memory is: o Memory cell o Cache memory o RAM o DRAM o None of the above
• Memory cell
105. Which stage is responsible for storing and loading values to and from memory? o Instruction Fetch o Memory read/write o Instruction Decode o Execution o Write Back
• Memory read/write
193. In which of the following approaches there is no shared data? o Message passing o Mutual exclusion o Monitors o Semaphores
• Message passing
194. Choose the correct answer for the following definition "Synchronization between processes is defined by the blocking policy attached to the sending and receiving of messages" o Message passing o Mutual exclusion o Monitors o Semaphores
• Message passing
160. Choose the correct answer for the following characteristics: 1. Depend mainly on its peripherals 2. Used for a few dedicated functions 3. Usually used as a part of a larger system o Microcontroller o General purpose microprocessor
• Microcontroller
78. What does MAF? o Miss Address File o Map Address File o Memory Address File
• Miss Address File
77. What does mean MSHR? o Miss Status Handling Register o Map Status Handling Reload o Mips Status Hardware Register o Memory Status Handling Register
• Miss Status Handling Register
94. At storage systems Gray and Siewiorek classify faults what does mean "Operation faults"? : o Mistakes by operations and maintenance personnel o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell o Faults in software (usually) and hardware design (occasionally)
• Mistakes by operations and maintenance personnel
94. Choose basic cache optimizations o Compiler-Controlled Prefetching o Nonblocking Caches o Small and Simple First-Level Caches o Multilevel Caches o Avoiding Address Translation during Cache Indexing
• Multilevel Caches • Avoiding Address Translation during Cache Indexing
90. Select cache optimizations to reduce miss penalty o Multilevel Caches o Giving Reads Priority over Writes o Way Prediction o Higher associativity
• Multilevel Caches • Giving Reads Priority over Writes
6. How the central termination point for data channels, the CPU, and memory is called. It schedules access to the memory from the CPU and data channels, allowing these devices to act independently. o Transistor o Multiplexor o Integrated circuit o Resistors o Capacitors
• Multiplexor
207. Choose the correct answer for the following definition "multiple processes on a system with multiple processors" o Multiprocessing o Multiprogramming o Distributed processing
• Multiprocessing
208. Choose the correct answer for the following definition "multiple processes on a system with a single processor" o Multiprogramming o Multiprocessing o Distributed processing
• Multiprogramming
189. Choose the correct answer for the following definition "Only one process may use a resource at one time" o Mutual exclusion o Circular wait o No preemption o Hold and wait
• Mutual exclusion
200. Choose the correct answer for the following definition "When one process is inside a critical section of code, other processes must be prevented from entering that section" o Mutual exclusion o Semaphores o Monitors o Message passing o Critical section
• Mutual exclusion
6. Cache MISS: o No Write Allocate, Write Allocate o Write Through, Write Back
• No Write Allocate, Write Allocate
187. Choose the correct answer for the following definition: "No process can be forced to release a resource" o No preemption o Mutual exclusion o Hold and wait o Circular wait
• No preemption
91. Select cache optimizations to increase the Cache Bandwidth o Nonblocking Caches o Multibanked Caches o Pipelined Cache Access o Multilevel Caches o Small and Simple First-Level Caches
• Nonblocking Caches • Multibanked Caches • Pipelined Cache Access
148. Examples of superscalar(dynamic) : o None at the present o Pentium 4, MIPS R12K, IBM, Power5 o MIPS and ARM o TI C6x
• None at the present
71. CPU Time = I * CPI / R. Which parameter requires special profiling software? o Cycles Per instruction o Clock Rate o Numbers of instructions o Execution time
• Numbers of instructions
54. Choose the feature(s) of fourth generation computer architecture o Wide spread use of data communications o Use of cache memory o Smallest in size o Use of drum memory or magnetic core memory o Object-Oriented programming
• Object-Oriented programming • Wide spread use of data communications • Smallest in size
83. Storage Systems, "Higher associativity to reduce miss rate" - o Obviously, increasing associativity reduces conflict misses o The obvious way to reduce capacity misses is to increase cache capacity o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
• Obviously, increasing associativity reduces conflict misses
89. Choose the definition for conflict misses o Occurs if the block placement strategy is not fully associative o Occurs if the cache cannot contain all the blocks needed during execution of a program o The very first access to a block cannot be in the cache
• Occurs if the block placement strategy is not fully associative
88. Choose the definition for capacity misses o Occurs if the cache cannot contain all the blocks needed during execution of a program o The very first access to a block cannot be in the cache o Occurs if the block placement strategy is not fully associative
• Occurs if the cache cannot contain all the blocks needed during execution of a program
54. Speculating on Exceptions "Recovery mechanism" is - o Only write architectural state at commit point, so can throw away partially executed instructions after exception o Exceptions are rare, so simply predicting no exceptions is very accurate o An entity capable of accessing objects o None of them
• Only write architectural state at commit point, so can throw away partially executed instructions after exception
19. PCI stands for: o Power Control Interface o Peripheral component interconnect o Property Casualty Insurers o Programmable Communications Interface
• Peripheral component interconnect
191. What is the deadlock? o Permanent blocking of a set of processes that either compete for global resources or communicate with each other o Interleaving of processes in time to give the appearance of simultaneous execution o When one process is inside a critical section of code, other processes must be prevented from entering that section o Processes "communicate" via global counters that are initialized to a positive integer and that can be accessed only through two atomic operations
• Permanent blocking of a set of processes that either compete for global resources or communicate with each other
48. What is a PRF? o Physical Register File o Pending Register File o Pipeline Register File o Pure Register File
• Physical Register File
114. Choose the key characteristics of computer memory systems o Physical Type o Physical Characteristics o Access Method o Unit of Transfer o Performance
• Physical Type • Physical Characteristics • Access Method • Unit of Transfer • Performance
235. Processor can simultaneously work on multiple instructions. How this technique called? o Pipelining o Branch prediction o Data flow analysis o Speculative execution o None of the above
• Pipelining
8. Which technique allows to processor simultaneously work on multiple instructions? o Branch prediction o Data flow analysis o Pipelining o Speculative execution
• Pipelining
137. What is a hash table? o Popular data structure for organizing a large collection of data items so that one can quickly answer questions o Popular data structure for updating large collections, so that one can hardly answer questions o Popular tables for organizing a large collection of data structure o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
• Popular data structure for organizing a large collection of data items so that one can quickly answer questions
11. Algorithm for Cache HIT: o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
• Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
220. Contains the address of the next instruction pair to be fetched from memory o Program counter (PC) o Memory buffer register (MBR) o Memory address register (MAR) o Instruction register (IR) o Instruction buffer register (IBR)
• Program counter (PC)
130. Which of the following descriptions corresponds to dynamic power? o Proportional to the product of the number of switching transistors and the switching rate o Grows proportionally to the transistor count (whether or not the transistors are switching) o Certainly a design concern o None of the above
• Proportional to the product of the number of switching transistors and the switching rate
33. What is kernel process? o Provide at least two modes, indicating whether the running process is a user process or an operating system process o Provide at least five modes, indicating whether the running process is a user process or an operating system process o Provide a portion of the processor state that a user process can use but not write o None of them
• Provide at least two modes, indicating whether the running process is a user process or an operating system process
78. Choose the access method(s) o Parallel Access o Indirect Access o Random Access o Direct Access o Sequential Access
• Random Access • Direct Access • Sequential Access
108. Choose data dependences o Read-After-Read o Read-After-Write o Write-After-Write o Write-After-Read
• Read-After-Write • Write-After-Write • Write-After-Read
224. RAID stands for o Redundant Array Independent Disk o Random Access Integral Disk o Redundant Access Integral Disk o Random Array Independent Disk o Redundant Access Independent Disk
• Redundant Array Independent Disk
138. What does RAID stand for? o Random Array of Independent Disks o Redundant Array of Independent Disks o Redundant Array of Interoperable Disks o Random Access to Independent Disks
• Redundant Array of Independent Disks
59. Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic? o Register name o Instruction cache o Data tags o Data cache
• Register name
3. What provides storage internal to the CPU? o Registers o Arithmetic and logic unit o CPU interconnection o Control unit
• Registers
55. What is a RT? o Rename Table o Recall Table o Relocate Table o Remove Table
• Rename Table
46. What is a ROB? o Reorder Buffer o Read Only Buffer o Reload Buffer o Recall Buffer
• Reorder Buffer
84. In Non-Blocking Caches what does mean "Critical Word First"? o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
• Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
49. What is a SB? o Scoreboard o Scorebased o Scaleboard o Scalebit
• Scoreboard
151. How external nonvolatile memory is called? o Secondary memory o Main memory o Cache memory o Virtual memory
• Secondary memory
152. What is included into physical type characteristic of computer memory systems? o Semiconductor o Magnetic o Word o Access Time o Number of bytes
• Semiconductor • Magnetic
228. Memory is organized into units of data, called records; access must be made in a specific linear sequence o Sequential access o Word o Addressable units o Unit of transfer o Direct access
• Sequential access
20. The methods of accessing units of data: o Sequential access o Pseudo access o Direct access o Indirect access o Single access o Random access o Associative access
• Sequential access / • Direct access / • Associative access / • Random access
83. In which cache memory mapping technique any memory block mapped to subset of cache locations? o Set Associative Mapping o Direct Mapping o Associative Mapping
• Set Associative Mapping
90. What is a RAID 3? o Since the higher-level disk interfaces understand the health of a disk, it's easy to figure out which disk failed o Many applications are dominated by small accesses o Also called mirroring or shadowing, there are two copies of every piece of data
• Since the higher-level disk interfaces understand the health of a disk, it's easy to figure out which disk failed
223. The use of the _______ defines the third generation of computers. o Small and medium-scale integration o Transistor o Vacuum tube o Large-scale integration o Very-large-scale integration
• Small and medium-scale integration
50. How is called a random, nondestructive event that alters the contents of one or more memory cells without damaging the memory? o Soft error o Hard error o Hard failure o Soft failure o Epic failure
• Soft error
63. At VLIW by "performance and loop iteration" which time is shorter? o Software Pipelined o Loop Unrolled
• Software Pipelined
144. SSD stands for o Solid State Drive o Solid State Driver o Speed State Drive o Speed State Driver
• Solid State Drive
11. This technique enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed. o Branch prediction o Data flow analysis o Pipelining o Speculative execution
• Speculative execution
64. At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion? o Speculative operations that don't cause exceptions o Hardware to check pointer hazards
• Speculative operations that don't cause exceptions
41. What measures the ability of a computer to complete a single task? o Clock rate o Speed metric o Clock speed o Clock cycle o Execution speed
• Speed metric
23. Amdahl's law: o Speed up= 1/(1 + f ) * f/N o Speed up= 1/(1 - f ) * f/N o Speed up= 1/(1 - f ) - f/N o Speed up= 1/(1 - f ) + f/N o Speed up= 1/(1 + f ) + f/N
• Speed up= 1/(1 - f ) + f/N
128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to: o Speedup o Efficiency o Probability o Ration
• Speedup
134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement o Static power o Dynamic power o Processing rate o Processor state
• Static power
100. Choose hazard for the following definition: different instructions in different stages (or the same stage) conflicting for the same resource o Structural o Data o Control
• Structural
44. How we call the thing that is connects major computer components (processor, memory, I/O)? o System connector o System controllers o System bus o System interconnector
• System bus
149. Examples of VLIW/LIW: o TI C6x o MIPS and ARM o Itanium o Pentium 4, MIPS R12K, IBM, Power5
• TI C6x
29. What is the cycle time? o The minimum time between requests to memory. o Time between when a read is requested and when the desired word arrives o The maximum time between requests to memory. o None of them
• The minimum time between requests to memory.
196. In atomic operations semSignal(x) and semWait(x), what is the 'x'? o The number of processes that can execute critical section o The number of processes o The number of monitors o No correct answer
• The number of processes that can execute critical section
132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when: o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate o The number of transistors switching will be proportional to the sustained rate o The performance is proportional to the peak issue rate
• The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
82. Storage Systems, "Bigger caches to reduce miss rate" - o The obvious way to reduce capacity misses is to increase cache capacity o Obviously, increasing associativity reduces conflict misses o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
• The obvious way to reduce capacity misses is to increase cache capacity
81. Storage Systems, "Larger block size to reduce miss rate" - o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size o The obvious way to reduce capacity misses is to increase cache capacity o Obviously, increasing associativity reduces conflict misses
• The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
34. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "System response time" - ?: o The time between when the user enters the command and the complete response is displayed o The time for the user to enter the command o The time from the reception of the response until the user begins to enter the next command
• The time between when the user enters the command and the complete response is displayed
97. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "System response time" - ?: o The time between when the user enters the command and the complete response is displayed o The time for the user to enter the command o The time from the reception of the response until the user begins to enter the next command
• The time between when the user enters the command and the complete response is displayed
96. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "Entry time" - ? : o The time for the user to enter the command o The time between when the user enters the command and the complete response is displayed o The time from the reception of the response until the user begins to enter the next command
• The time for the user to enter the command
35. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "Think time" - ?: • The time from the reception of the response until the user begins to enter the next command o The time for the user to enter the command o The time between when the user enters the command and the complete response is displayed
• The time from the reception of the response until the user begins to enter the next command
98. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an "Think time" - ?: o The time from the reception of the response until the user begins to enter the next command o The time for the user to enter the command o The time between when the user enters the command and the complete response is displayed
• The time from the reception of the response until the user begins to enter the next command
87. Choose the definition for compulsory misses o Occurs if the cache cannot contain all the blocks needed during execution of a program o Occurs if the block placement strategy is not fully associative o The very first access to a block cannot be in the cache
• The very first access to a block cannot be in the cache
89. What is a RAID 2? o This organization was inspired by applying memory-style error correcting codes to disks o It has no redundancy and is sometimes nicknamed JBOD, for "just a bunch of disks," although the data may be striped across the disks in the array o Also called mirroring or shadowing, there are two copies of every piece of data
• This organization was inspired by applying memory-style error correcting codes to disks
28. What is the access time? o Time between when a read is requested and when the desired word arrives o The minimum time between requests to memory. o Describes the technology inside the memory chips and those innovative, internal organizations o None of them
• Time between when a read is requested and when the desired word arrives
52. Choose the feature(s) of third generation computer architecture o Object-Oriented programming o Floating point arithmetic o Graphics o Timesharing o Use of cache memory
• Timesharing / • Use of cache memory
140. For what the reorder buffer is used : o To pass results among instructions that may be speculated. o To pass parameters through instructions that may be speculated o To get additional registers in the same way as the reservation stations o To control registers
• To pass results among instructions that may be speculated.
121. The rate at which data can be transferred into or out of a memory unit is called o Transfer time o Transfer Rate o MIPS o FLOPS o MFLOPS
• Transfer Rate
221. The use of the _______ defines the second generation of computers. o Transistor o Vacuum tube o Small and medium-scale integration o Large-scale integration o Very-large-scale integration
• Transistor
115. Word is the "natural" unit of organization of memory o True o False
• True
119. When using microprocessor based systems, it is enough to update the software o True o False
• True
122. The particular block is currently being stored is called tag o True o False
• True
139. The RAID scheme consists of 7 levels o True o False
• True
141. SSD is over 10 times faster than the spinning disks in HDD o True o False
• True
150. The basic element of a semiconductor memory is the memory cell o True o False
• True
162. The assembler translates names into memory addresses o True o False
• True
163. Name field of assembly statement is not case sensitive o True o False
• True
168. You should use a radix symbol in order to differentiate between binary, octal or hexadecimal o True o False
• True
170. In assembly language, you can skip the name of variable o True o False
• True
176. There is no memory allocated for constants in assembly language o True o False
• True
181. There are 2 policies of deadlock prevention o True o False
• True
192. Deadlock occurs when each process in the set is blocked awaiting an event that can be triggered only by another blocked process in the set o True o False
• True
195. Monitors are similar to classes in java and has methods and fields o True o False
• True
198. We can implement mutex through the OS or using programming languages o True o False
• True
201. In concurrency optimal allocation of resources is difficult o True o False
• True
203. In concurrency, sharing global resources safely is difficult o True o False
• True
232. Moore's law: "The computer becomes smaller, making it more convenient to place in a variety of environments" o True o False
• True
233. Moore's law: "There is a reduction in power and cooling requirements" o True o False
• True
234. Moore's law: "The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections" o True o False
• True
236. The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache o True o False
• True
35. Basic memory elements hold only two states: Zero / One o True o False
• True
59. IBM System/360 Model 91 was introduced in 1966 o True o False
• True
222. The use of the _______ defines the first generation of computers. o Vacuum tube o Transistor o Small and medium-scale integration o Large-scale integration o Very-large-scale integration
• Vacuum tube
51. Choose the feature(s) of first generation computer architecture o Magnetic core memory o Semiconductor memory o Machine code o Vacuum tubes o Assembly language
• Vacuum tubes / • Assembly language
61. What is "VLIW"? o Very Long Instruction Word o Very Less Interpreter Word o Very Light Internal Word o Very Low Invalid Word
• Very Long Instruction Word
. Expand the abbreviation VLSI o Very-large-scale integration o Very-little-scale integration o Very-large-scale interactions o Very-large-scale integrator
• Very-large-scale integration
22. What kind of memory type stores data using virtual addresses: o Logical o Virtual o Peripheral o Main o Buffer
• Virtual
159. Which of the following architectures differs by memory accessing? o Von Neumann o Harvard o Complex Instruction Set Computers o Reduced Instruction Set Computers
• Von Neumann • Harvard
133. If we want to sustain four instructions per clock o We must fetch more, issue more, and initiate execution on more than four instructions o We must fetch less, issue more, and initiate execution on more than two instructions o We must fetch more, issue less, and initiate execution on more than three instructions o We must fetch more, issue more, and initiate execution on less than five instructions
• We must fetch more, issue more, and initiate execution on more than four instructions
58. At VLIW "Superscalar Control Logic Scaling" which parameters are used? o Width and Lifetime o Width and Height o Time and Cycle o Length and Addition
• Width and Lifetime
229. The "natural" unit of organization of memory o Word o Sequential access o Addressable units o Unit of transfer o Direct access
• Word
106. How the stage in which the results of the operation are written to the destination register is called? o Instruction Fetch o Write Back o Instruction Decode o Execution o Memory read/write
• Write Back
21. Cache Hit - o Write Through - write both cache and memory, generally higher traffic but simpler to design o write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated o No Write Allocate - only write to main memory
• Write Through - write both cache and memory, generally higher traffic but simpler to design
5. Cache HIT: o No Write Allocate, Write Allocate o Write Through, Write Back
• Write Through, Write Back
17. What is a Bandwidth: o a is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle o is time for a single access - Main memory latency is usually >> than processor cycle time o is amount of data that can be in flight at the same time (Little's Law)
• a is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
210. Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by: o a system clock o a system processor o a clock processor o a processor o a clock
• a system clock
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer... o bandwidth o latency o throughput o performance
• bandwidth
62. How a binary digit is called? o byte o digit o kilobyte o bit
• bit
25. Exploit spatial locality: o by fetching blocks of data around recently accessed locations o by remembering the contents of recently accessed locations o None of them
• by fetching blocks of data around recently accessed locations
24. Exploit temporal locality: o by remembering the contents of recently accessed locations o by fetching blocks of data around recently accessed locations o None of them
• by remembering the contents of recently accessed locations
69. What is a Capacity? o cache is too small to hold all data needed by program, occur even under perfect replacement policy o first-reference to a block, occur even with infinite cache o misses that occur because of collisions due to less than full associativity
• cache is too small to hold all data needed by program, occur even under perfect replacement policy
9. Capacity - o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines) o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines) o first-reference to a block, occur even with infinite cache
• cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
20. Least Recently Used (LRU): o cache state must be updated on every access o Used in highly associative caches o FIFO with exception for most recently used block(s)
• cache state must be updated on every access
118. Products that are sold by multiple vendors in large volumes and are essentialy identical o commodities o boxes o folders o files
• commodities
17. What is used to manage the access to and the use of the data and address lines? o address bus o control lines o memory write o bus grant o address lines
• control lines
139. How this process called: "Operations execute as soon as their operands are available" o data flow execution o instruction execution o data control execution o instruction field execution
• data flow execution
39. A single, self-contained transistor is called ________. o integrated circuit o microchip o discrete component o single transistor o small-scale integration
• discrete component
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____ o dynamic power o physical energy o constant supply o simple battery
• dynamic power
119. Integrated circuit processes are charecterized by the o feature size o permanent size n o compex size o fixed size
• feature size
68. What is a Compulsory? o first-reference to a block, occur even with infinite cache o cache is too small to hold all data needed by program, occur even under perfect replacement policy o misses that occur because of collisions due to less than full associativity
• first-reference to a block, occur even with infinite cache
8. Compulsory - o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines) o first-reference to a block, occur even with infinite cache o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
• first-reference to a block, occur even with infinite cache
10. Conflict - o first-reference to a block, occur even with infinite cache o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines) o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
• first-reference to a block, occur even with infinite cache (NOT CORRECT!!!)
40. GPU stands for: o graphical processing unit o graphical performing units o graphics processing units o graphics processing utility
• graphics processing units
15. The processor responds by suspending operation of the current program, branching off to a program to service that particular I/O device, known as _________________, and resuming the original execution after the device is serviced. Which of the following will be the missing word: o interrupt handler o interrupt cycle o disabled interrupt o interrupt request
• interrupt handler
18. What is a Bandwidth-Delay Product: o is amount of data that can be in flight at the same time (Little's Law) o is time for a single access - Main memory latency is usually >> than processor cycle time o is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
• is amount of data that can be in flight at the same time (Little's Law)
19. What is Computer Architecture? o is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies o is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users o the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
• is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
1. What is a Latency: o is time for a single access - Main memory latency is usually >> than processor cycle time o is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle o is amount of data that can be in flight at the same time (Little's Law)
• is time for a single access - Main memory latency is usually >> than processor cycle time
72. Select the correct interpretation(s) of Amdahl's Law o is used to compare computers' performance o is used calculate the execution time of a program o is used to find the maximum expected improvement o it means that it is the algorithm that decides the speedup not the number of processors
• is used to find the maximum expected improvement • it means that it is the algorithm that decides the speedup not the number of processors
143. Choose the steps of instruction execution: o issue, execute, write result, commit o execution, commit, rollback o issue, execute, override, exit o begin, write, interrupt, commit
• issue, execute, write result, commit
155. Choose the characteristics of CISC processors o large number of instructions o support many addressing modes o more elaborate way of accessing data o less number of instructions o instructions are of fixed length o few addressing modes
• large number of instructions • support many addressing modes • more elaborate way of accessing data
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is... o latency o bandwidth o throughput o performance
• latency
156. Choose the characteristics of RISC processors o less number of instructions o large number of instructions o instructions are of fixed length o support many addressing modes o more elaborate way of accessing data o few addressing modes
• less number of instructions • instructions are of fixed length • few addressing modes
29. MIC stands for: o mini integrated core o many integrated core o main integrated core o many interaction core o main interaction core
• many integrated core
126. What MTTF means: o mean time to failure o mean time to feauture o mean this to failure o my transfers to failure
• mean time to failure
72. In Multilevel Caches "Global miss rate" equals = o misses in cache / CPU memory accesses o misses in cache / accesses to cache o misses in cache / number of instructions
• misses in cache / CPU memory accesses
71. In Multilevel Caches "Local miss rate" equals = o misses in cache / accesses to cache o misses in cache / CPU memory accesses o misses in cache / number of instructions
• misses in cache / accesses to cache
73. In Multilevel Caches "Misses per instruction" equals = o misses in cache / number of instructions o misses in cache / accesses to cache o misses in cache / CPU memory accesses
• misses in cache / number of instructions
70. What is a Conflict? o misses that occur because of collisions due to less than full associativity o first-reference to a block, occur even with infinite cache o cache is too small to hold all data needed by program, occur even under perfect replacement policy
• misses that occur because of collisions due to less than full associativity
2. What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns? o n loop iterations o subroutine call o vector access
• n loop iterations
161. Choose the correct syntax of assembly statements o name operation operand(s) comments o operation name operand(s) comments o operation operand(s) name comments o comments name operation operand(s)
• name operation operand(s) comments
157. Choose the characteristics of Von Neumann architecture o one memory for data and program o CPU provides address to get data or instructions o data and instructions must have the same width o separate busses, can be accessed simultaneously o separated buses allow one instruction to execute while the next instruction is fetched o data and instructions mustn't have the same width
• one memory for data and program • CPU provides address to get data or instructions • data and instructions must have the same width
114. Network performance depends of what? o performance of swithes and transmission system o performance of switches o performance of transmission system o has no dependensies
• performance of swithes and transmission system
98. Process of instruction execution is divided into two or more steps, called o pipelining o pipe stages o pipe segments o instruction execution o pipeline hazard
• pipe stages • pipe segments
16. What is the data line? o provide a path for moving data among system modules o is used to designate the source or destination of the data on the data bus o is used to control the access to and the use of the data and address lines o indicates that a module needs to gain control of the bus
• provide a path for moving data among system modules
211. Typically all operations performed by a processor begin with the: o pulse of the clock o pulse of the processor o it begins by itself o both of clock and processor pulse o none of the above
• pulse of the clock
122. Volume is a ________ key factor in determining cost. o second o first o fifth o third
• second
158. Choose the characteristics of Harvard architecture o separate program and data memories o separated buses allow one instruction to execute while the next instruction is fetched o data and instructions mustn't have the same width o one memory for data and program o CPU provides address to get data or instruction o data and instructions must have the same width
• separate program and data memories • separated buses allow one instruction to execute while the next instruction is fetched • data and instructions mustn't have the same width
109. Halting the flow of instructions until the required result is ready to be used is called o waiting o delaying o halting o stalling
• stalling
144. Which one is not the major flavor of Multiple-issue processors: o statistically superscalar processors o dynamically scheduled superscalar processors o statically scheduled superscalar processors o VLIW (very long instruction word) processors
• statistically superscalar processors
3. What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns? o subroutine call o n loop iterations o vector access
• subroutine call
142. Choose correct fields of entry in the ROB: • the instruction type, the destination field, the value field, and the ready field o the source type, the destination field, the value field, and the ready field o the program type, the ready field, the parameter field, the destination field o the instruction type, the destination field, and the ready field
• the instruction type, the destination field, the value field, and the ready field
121. Manufacturing costs that decrease over time are ____ o the learning curve o the cycled line o the regular option o the final loop
• the learning curve
13. The formula of "Iron Law" of Processor Performance: o time/program = instruction/program * (cycles/instruction)* time/cycle o time/program = instruction/program * (cycles/instruction) + time/cycle o time/program = instruction/program + (cycles/instruction) * time/cycle
• time/program = instruction/program * (cycles/instruction) * time/cycle
125. Desktop benchmarks divide into __ broad classes: o two o three o four o five
• two
171. Choose the correct syntax of variable declaration in assembly o variable_name type initial_value o type variable_name initial_vaule o variable_name type initial_value o type initial_value variable_name
• variable_name type initial_value
4. What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns? o subroutine call o n loop iterations o vector access
• vector access
117. Learning curve itself is best measured by change in... o yeld o bytes o bits o seconds
• yeld
