CSC205ch6-9
Consider the postfix (reverse Polish notation) 3 5 + 7 2 - * . The equivalent infix expression is:
(3 + 5) * (7 - 2)
Which of the following is false concerning compiled code:
-Interpreters optimize as nicely as compilers do. -compiled code is generally slower than interpreted code -compiled code is often more portable Correct == all of the above are false
CISC computers generally have these features except:
-Reduce the instructions per program -Rely on microcode to process instruction complexity -Interprets each instruction as it is fetched from memory Correct Answer == -Microcode allows handling of variable length instructions as efficiently as fixed length instructions.
RISC computers general have the following features except
-Simpler instruction set -shorter clock cycles Correct= -more transistors -cheaper manufacturing costs
Assume a 262,144byte memory: What are the lowest and highest addresses if memory is byte-addressable?
0 --- 262143
The first two bytes of a 2M x 16 main memory have the following hex values: Byte 0 is 12 Byte 1 is 34 Which of the following is the representation of a little endian?
0x3412
A system implements a paged virtual address space for each process using a one-level pagetable. The maximum size of virtual address space is 16MB. The page size is 1024 bytes and the maximum physical memory size of the machine is 2MB. What is the maximum number of entries in a page table?
10^14
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing atotal of 64K bytes of data and blocks of 32 bytes. Show the format of a 24-bit memoryaddress for: Direct Map
11 bits are needed for the block field. 5 bits are needed for the offset field, leaving 8 for the tag.
If you have a memory capacity of 8192 bytes, how many bits will each address contain?
13
A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of eight bytes each and byte addressing is used. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.
14-bit addresses with 9 bits in the tag field, 2 bits in the set field (since we have four sets), and 3 in the offset field
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory.Suppose the page size is 2^4 bytes., ) How many page frames are there in main memory?
16
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing atotal of 64K bytes of data and blocks of 32 bytes. For an associate cache, how many bits are needed for the tag field?
19
How many bits are required to address a 1M × 8 main memory if main memory is byte-addressable?
20
A system implements a paged virtual address space for each process using a one-level pagetable. The maximum size of virtual address space is 16MB. The page size is 1024 bytes and the maximum physical memory size of the machine is 2MB. How many bits are required for each physical address?
21
A digital computer has a memory unit with 32 bits per word. The instruction set consists of 180 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are left for the address part of the instruction?
24
A system implements a paged virtual address space for each process using a one-level pagetable. The maximum size of virtual address space is 16MB. The page size is 1024 bytes and the maximum physical memory size of the machine is 2MB. How many bits are required for each virtual address?
24
Suppose a computer using fully associative cache has 2^24 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields?
24 bit addresses with 18 bits in the tag field and 6 in the offset field
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing atotal of 64K bytes of data and blocks of 32 bytes. For a direct mapped cache, how many blocks are in cache?
2^11
Suppose a computer using fully associative cache has 2^24 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. How many blocks of main memory are there?
2^18
Suppose a byte-addressable computer using set associative cache has 2^16 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. If this cache is 4-way set associative, how many sets should this cache have?
2^3
Java, C, C++, Fortran, Cobol are examples of what generation programming language?
3rd
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing atotal of 64K bytes of data and blocks of 32 bytes. Show the format of a 24-bit memoryaddress for: Associative
5 bits are needed for the offset field, leaving 19 for the tag.
Suppose that a 16M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable, how many RAM chips are necessary?
64
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory.Suppose the page size is 2^4 bytes., How many entries are in the page table for a process that uses all of virtual memory?
64
Suppose we have 2^10 bytes of virtual memory and 2^8 bytes of physical main memory.Suppose the page size is 2^4 bytes., How many pages are there in virtual memory?
64
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 125 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are needed for the opcode?
7
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of64 bytes each, and 4 page frames. How many bits are in a physical address?
8
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of64 bytes each, and 4 page frames. How many bits are in a virtual address?
9
A generic DMA controller consists of which of the following components:
Address generator Address bus interface Data bus interface Correct = All of the above
An operating system is responsible for all of the below except which one of the following Process management, I/O management, application program compilation, memory management
Application program compilation
________________________ refers to how a computer system is designed and what technologies it is compatible with.
Architecture
By design, Cache is not accessed by address specification. Alternatively, Cache is commanly also known as:
CAM
Of the four types of I/O architectures, which of the following are typically used in the largest Enterprise class systems
Channel I/O
____________________ requires the user to know the syntax of the operating system
Command-line interface
The computer component that makes sure that instructions are deciphered and processed properly is the:
Control Unit
Of programmed I/O, interrupt-driven I/O, DMA, or channel I/O, which is most suitable for processing the I/O of a CD.
DMA
Stack, accumulator, and general-purpose registers are
Examples of ISA
A fixed-length instruction must have fixed-length opcodes.
False
A program counter points to the memory address of the instruction that the CPU is currently executing
False
A user program executing under the confines of a virtual machine can access only selected resources that are defined to it.
False
Accumulator architectures store one operand on the stack and the other in the accumulator.
False
An assembler "assembles" assembly language into register transfer code.
False
Because the Java Virtual Machine is so efficient in loading and executing bytecode, its performance is similar to that of a compiled language
False
Direct mapped cache is more expensive than other caches because the memory scheme require the manufacture of chips that incorporate the logic of address mapping.
False
In describing a paging environment, if a page valid bit is 0, one would replace the virtual page number with the actual page frame number.
False
Many appliances,toys, and most automobiles use RAM chips to store information information when the device requiring memory for operation is not in use.
False
Processor, memory, and a monitor is all that is necessary to construct a computer (defines a computer).
False
Some systems place the directory on the outer tracks of the disk for faster access time.
False
The best architecture for evaluating infix notation is the stack-based architecture.
False
Today's state of the art computer hardware technology eliminates the need for accumulators as part of the architecture.
False
-Bi-directional (can be sent both ways)- Width of the data bus is defines by the number of wires or lines it contains- If the data bus is the same width as a computer word, data can be transferred to and from memory in a single operation
Features of a data bus
Backup and recovery services to the cloud is a limited form of:
Infrastructure as a Service (IaaS).
The output from the Java compiler is a binary class file that is executed by a:
Java Virtual Machine
Which is not an example of the three main types of Cloud computing platforms.
MaaS
In 1965 one of the founders of Intel predicted, "The density of transistors in an integrated circuit will double every year." This is now known as:
Moore's Law.
When a process relinquishes the CPU voluntarily, it is called
Nonpreemptive scheduling
Operating systems ensure process security through the use of all below except:
Performing context verification on each process
facilitates the flow of data to and from external devices connected to the computer.
Ports
Consider the hexadecimal number 2AC2081B stored in memory. If the machine is big endian and the number is an IEEE single-precision floating point value, is the number positive or negative?
Positive
I/O design that reserves a register for each I/O device. Each register is continually polled to detect data arrival
Programmed I/O
RAID level that stripes bits across a set of data drives and provides separate disk for parity
Raid level 3
Which of the RAID systems described in this chapter cannot tolerate a single disk failure?
Raid-0
Suppose a computer using fully associative cache has 2^24 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. To which cache block will the memory address 0x01D872 map
Since it's associative cache, it can map anywhere
The _________________________________ connects the CPU to memory.
System bus
Your friend has just bought a new personal computer. She tells you that her new system runs at 1GHz, which makes it over three times faster than her old 300 MHz system. What would you tell her? (Hint: Consider how Amdahl's Law applies.) You would tell her that:
The processor is only one component contributing to the overall performance of a system.
DVDs rotate at about ______________ times the speed of CDs.
Three
A disadvantage of RAID-1 is that it is costly and requires large memory space.
True
In the von Neumann model, the control unit part of the processor is responsible for monitoring instruction fetching.
True
It is not necessary to store programs in continuous chucks of memory for processes to run.
True
Larger caches usually provides an increase in processor performance.
True
Like RAID-6, RAID DP can tolerate the simultaneous loss of two disk drives without loss of data.
True
Little endian computers store a two-byte integer with the least significant byte at the low end of the address field.
True
MARIE has a common bus scheme, which means a number of entities share the bus.
True
Multiprogramming typically refers to multiple processes from multiple users
True
On CDs, directory entries are not in a fixed location, they can "float."
True
Operating system user interfaces are divided into two general categories: command-line interfaces and graphical user interfaces.
True
Windows VMM ia a subsystem that starts when Windows is booted.
True
You get more efficient usage (less wasted space) on the disk, if you have a larger number of sectors per cluster
True
Although not specifically designed for this purpose, some operating could use this device for paging, some operating systems are designed to allow a user to incorporate this device for the purpose of virtual memory paging.
USB flash drive
________________ is a technique that distributes data and erase/write cycles evenly over the entire disk to extend the life of the disk.
Wear leveling
Java ____________ are bytecode that runs in browsers.
applets
Electrical signal loss over time or distance during data transfer is called:
attenuation.
The term endian reflects the architecture of a computer's
byte order
Advantages of dynamic linking are:
causes 0 or minimal load-time delays
The level of the computer hierarchy that is composed of gates and wires is the:
digital logic level.
DLL stands for:
dynamic link library
Which recording methodology does DAT use to record data?
helical
When as a result of paging the last page copied into memory is not need for processing, if the unused memory in the last frame is wasted, we have a condition known as
internal fragmentation
MTTR means:
mean time to repair
Computer chips having multiple processing units on a single chip are ________________________________ architectures.
multicore
The final output of most assemblers is a stream of ___________ binary instructions.
relocatable
__________________ is a precursor to modern operating systems that allowed programs to be processed without human interaction.
resident monitor
A simpler and more elegant approach is memory-mapped I/O because I/O devices and main memory share the:
same address space.
Because server farms have become more prevalent in the business environment, every major enterprise business manufacturer is offering ________________________________ in an attempt to ease the burden of managing a multitude of server issues.
server consolidation
Any task done by _____________ can also be done using computer hardware, and any operation performed directly by hardware can be done using _______________..
software
Which of the following checks the symbol table that checks for the presence of programmer defined variable that populate the tree:
syntax analyzer
Access time is
the sum of the rotational delay and the seek time.
Holographic data storage stores enormous data density by using:
three-dimensional medium.
Assembly programming provides interesting challenges in trying to complete a programing objective. As such which of the following is false: Assembly programming is
yields execution times for programs that are slower than for high level languages
A stack-organized computer uses ________________ addressing.
zero-address
