CSci 451 Chapter 6-10 questions

Consider a system with memory mapping done on a page basis and using a singlelevel page table. Assume that the necessary page table is always in memory.

(15) If a memory reference takes 100 nanoseconds, how long does a memory mapped reference take if there is no TLB within the MMU to cache recently used page addresses? 200 nanoseconds: 100 to get the page table entry, and 100 to access the memory location. (20) Now we add an MMU which imposes an overhead of 15 nanoseconds on a hit or a miss. If we assume that 90 percent of all memory references hit in the MMU TLB, what is the Effective Memory Access time? There are two cases. In the first case, the TLB contains the required entry. Then we pay the 15 ns overhead on top of the 100 ns memory access time. In the second case, the TLB does not contain the item. Then we pay an additional 100 ns to get the required entry into the TLB, making 215 ns altogether. Hence, the EMAT is: (115 * 0.9) + (215 * 0.1) = 125 ns (15) Explain how the TLB hit rate affects the EMAT. The higher the TLB hit rate is, the smaller the EMAT is, because the additional 100 ns penalty to get the page table entry into the TLB on a miss contributes less to the EMAT. It is important to note, however, that while any increase in the TLB hit rate decreases the EMAT, the magnitude of change in the EMAT is not constant. The EMAT asymtotically approaches the physical memory speed as the TLB hit rate approaches 100\%. Thus, at some point it makes more sense to stop spending money to increase the TLB hit rate, and to spend it instead on faster physical memory.

8.18) Given a paged logical address space composed of 32 pages of 2 Kbytes each, mapped into a 1 MByte physical memory space, a) The format of the processors logical space is: 5 bits for logical page number (25 = 32) | 11 bits for the offset (211 =2K) b) The length and width of the page table is: The length = 32 (32 pages to map). The width = 9 bits (220 =1M. 20 - 11=9) c) If the physical memory size is halved, the number of physical page frames is halved and the physical page address space is halved, so the page table width is reduced by 1.

...

Consider the following set of processes: Process Arrival Time Processing Time A 0 3 B 1 5 C 3 2 D 9 5 E 12 5 Perform the same analysis as depicted in Table 9.5 and Figure 9.5 for this set.

0 5 10 15 20 | | | | | | | | | | | | | | | | | | | | | FCFS P1 ------ P2 ---------- P3 ---- P4 ---------- P5 ---------- RR q=1 P1 -- -- -- P2 -- -- -- -- -- P3 -- -- P4 -- -- -- -- -- P5 -- -- -- ---- RR q=4 P1 ------ P2 -------- -- P3 ---- P4 -------- -- P5 -------- -- SPN P1 ------ P2 ---------- P3 ---- P4 ---------- P5 ---------- SRT P1 ------ P2 ---------- P3 ---- P4 ---------- P5 ---------- HRRN P1 ------ P2 ---------- P3 ---- P4 ---------- P5 ---------- FB q=1 P1 -- -- -- P2 -- -- ---- -- P3 -- -- P4 -- -- -- -- -- P5 -- -- -- ---- FB q=2^i P1 -- ---- P2 -- ---- ---- P3 -- -- P4 ------ ---- P5 -- -------- For feedback queueing with a quantum of 1, I assume that when a process is taken off the processor and placed in a lower priority queue, it is not eligible to go right back onto the processor. It must wait another quantum. For feedback queueing with a quantum of 2i, I assume that a newly arriving process can't preempt the current process until it is done with its quantum. This is different from the book's assumption and therefore different from Figure 9.5 in the book. Here are the metrics: 1 2 3 4 5 Ta 0 1 3 9 12 Ts 3 5 2 5 5 ================================================ FCFS Tf 3 8 10 15 20 Tq 3 7 7 6 8 6.20 Tq/Ts 1.00 1.40 3.50 1.20 1.60 1.74 ================================================ RR q=1 Tf 6 11 8 18 20 Tq 6 10 5 9 8 7.60 Tq/Ts 2.00 2.00 2.50 1.80 1.60 1.98 ================================================ RR q=4 Tf 3 10 9 19 20 Tq 3 9 6 10 8 7.20 Tq/Ts 1.00 1.80 3.00 2.00 1.60 1.88 ================================================ SPN Tf 3 10 5 15 20 Tq 3 9 2 6 8 5.60 Tq/Ts 1.00 1.80 1.00 1.20 1.60 1.32 ================================================ SRT Tf 3 10 5 15 20 Tq 3 9 2 6 8 5.60 Tq/Ts 1.00 1.80 1.00 1.20 1.60 1.32 ================================================ HRRN Tf 3 10 5 15 20 Tq 3 7 7 6 8 6.20 Tq/Ts 1.00 1.40 3.50 1.20 1.60 1.74 ================================================ FB q=1 Tf 7 11 6 18 20 Tq 7 10 3 9 8 7.40 Tq/Ts 2.33 2.00 1.50 1.80 1.60 1.85 ================================================ FB q=1 Tf 4 10 8 16 20 Tq 4 9 5 7 8 7.00 Tq/Ts 1.33 1.80 2.50 1.40 1.60 1.81 ================================================ Assume the following burst-time pattern for a process: 6,4,6,4,13,13,13, and assume that the initial guess is 10.

Another placement algorithm for dynamic partitioning is referred to as worst-fit. In this case, the largest free block of memory is used for bringing in a process. a. Discuss the pros and cons of this method compared to first-, next-, and best-fit. b. What is the average length of the search for worst-fit?

A criticism of the best fit algorithm is that the space remaining after allocating a block of the required size is so small that in general it is of no real use. The worst fit algorithm maximizes the chance that the free space left after a placement will be large enough to satisfy another request, thus minimizing the frequency of compaction. The disadvantage of this approach is that the largest blocks are allocated first Therefore a request for a large area is more likely to fail.

Which type of process is generally favored by a multilevel feedback queueing scheduler—a processor-bound process or an I/O-bound process? Briefly explain why.

As processes use more and more CPU, they are moved down to the lower-priority queues. I/O-bound processes, which do not use much CPU, are moved up. So, this strategy favors I/O-bound jobs.

chapter 8, 8.1 Suppose the page table for the process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1,024 bytes. Virtual page number Valid bit Reference bit Modify bit Page frame number 0 1 1 0 4 1 1 1 1 7 2 0 0 0 — 3 1 0 0 2 4 0 0 0 — 5 1 0 1 0 a. Describe exactly how, in general, a virtual address generated by the CPU is translated into a physical main memory address. b. What physical address, if any, would each of the following virtual addresses correspond to? (Do not try to handle any page faults, if any.) (i) 1,052 (ii) 2,221 (iii) 5,499

Assume that a task is divided into four equal-sized segments and that the system builds an eight-entry page descriptor table for each segment. Thus, the system has a combination of segmentation and paging. Assume also that the page size is 2 Kbytes. a. What is the maximum size of each segment?

To implement the various placement algorithms for dynamic partitioning, a list of free blocks of memory must be kept. For each of best-fit, first-fit, next-fit, what is the average length of the search?

By problem 7.3, we know that the average number of holes is s/2, where s is the number of resident segments. Regardless of fit strategy, in equilibrium, the average search length is s/4.

Consider a system consisting of four processes and a single resource. The current state of the claim and allocation matrices are: C = § 3 2 9 7 ¥ A = § 1 1 3 2 ¥ What is the minimum number of units of the resource needed to be available for this state to be safe?

C = [3, 2, 9, 7]T A = [1, 1, 3, 2]T V = [?] C = [3, 2, 9, 7]T A = [1, 1, 3, 2]T R = [7] V = [0] X Cannot make progress on any process! need at least 1 extra instance of resource C = [3, 2, 9, 7]T A = [1, 1, 3, 2]T R = [8] V = [1] Finish P2: C = [3, 2, 9, 7]T A = [1, 0, 3, 2]T V = [2] Finish P1: C = [3, 2, 9, 7]T A = [0, 0, 3, 2]T V = [3] X Cannot make progress on any process! need at least 2 extra instances of resource C = [3, 2, 9, 7]T A = [0, 0, 3, 2]T R = [10] V = [5] Finish P4: C = [3, 2, 9, 7]T A = [0, 0, 3, 0]T V = [7] Finish P3: C = [3, 2, 9, 7]T A = [0, 0, 0, 0]T V = [10]

Comment on the following solution to the dining philosophers problem. A hungry philosopher first picks up his left fork; if his right fork is also available, he picks up his right fork and starts eating; otherwise he puts down his left fork again and repeats the cycle

Deadlock will not occur as no hold-and-wait. However, the philosophers can starve while repeatedly picking up and putting down their left forks in perfect unison.

chapter 10, 10.1 Consider a set of three periodic tasks with the execution profiles of Table 10.6 . Develop scheduling diagrams similar to those of Figure 10.5 for this set of tasks. Table 10.6 Execution Profile for Problem 10.1 Process Arrival Time Execution Time Ending Deadline A(1) 0 10 20 A(2) 20 10 40 • • • • • • • • • • • • B(1) 0 10 50 B(2) 50 10 100 • • • • • • • • • • • • C(1) 0 15 50 C(2) 50 15 100 • • • • • • • • • • • •

Develop scheduling diagrams for this set of tasks.

Consider a dynamic partitioning scheme. Show that, on average, the memory contains half as many holes as segments.

Let s and h denote the average number of segments and holes, respectively. The probability that a given segment is followed by a hole in memory (and not by another segment) is 0.5, because deletions and creations are equally probable in equilibrium. So, with s segments in memory, the average number of holes must be s/2. It is intuitively reasonable that the number of holes must be less than the number of segments because neighboring segments can be combined into a single hole on deletion

A process references five pages, A, B, C, D, and E, in the following order: A; B; C; D; A; B; E; A; B; C; D; E Assume that the replacement algorithm is first-in-first-out and find the number of page transfers during this sequence of references starting with an empty main memory with three page frames. Repeat for four page frames

Main Memory frames: Page transfer count A 1 B A 2 C B A 3 D C B 4 A D C 5 B A D 6 E B A 7 E B A 7 E B A 7 C E B 8 D C E 9 D C E 9 9 page transfers.

6.13

NO answer

Prove that, among nonpreemptive scheduling algorithms, SPN provides the minimum average waiting time for a batch of jobs that arrive at the same time. Assume that the scheduler must always execute a task if one is available.

Suppose there are n jobs arrive at the same time. Their service time are $T_1 < T_2 < T_3 \cdots < T_n$. According to SPN algorithm the average waiting time should be $\frac{T_1 \times (n - 1) + T_2 \times (n - 2) + \cdots + T_n}{n}$. If we switch the order of job $i$ and $j$ (assume $i < j$), then the value increased by $\frac{(j-i-1) \times (T_j - T_i)}{n} > 0$, so the SPN algorithm always provides the minimum average waiting time.

A system uses a fixed-partition scheme, with equal-sized partitions of 216 bytes, and a total main memory size of 224 bytes. A process table is maintained that includes a pointer to the resident partition for each resident process. How many bits are required for this pointer? Why?

The number of partitions would be 2^24/2^16, or 2^8 . So, the pointer to the partition would require 8 bits.

Consider the following string of page references 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2. Complete a figure similar to Figure 8.15 , showing the frame allocation for: a. FIFO (first-in-first-out) b. LRU (least recently used) c. Clock d. Optimal (assume the page reference string continues with 1, 2, 0, 1, 7, 0, 1) e. List the total number of page faults and the miss rate for each policy. Count page faults only after all frames have been initialized.

Time is number of ticks since process load time. Page fault has occurred at time 164. Which page is replaced and why: a. FIFO Page Frame Number (PFN) 3 since it was loaded longest ago at time 20 b. LRU PFN 1 since it was referenced longest ago at time 160 c. Clock Clear R in PFN 3 (oldest loaded), clear R in PFN 2 (next oldest loaded), victim PFN is 0 since R=0 Time is number of ticks since process load time. Page fault has occurred at time 164. Which page is replaced and why: d. Optimal, assuming page reference string 4,0,0,0,2,4,2,1,0,3,2 Replace the page in PFN 3 since VPN 3 (in PFN 3) is used furthest in the future e. Given above (just before page fault), assume page reference string4,0,0,0,2,4,2,1,0,3,2. How many page faults if working set policy with LRU were used with a window size 4 and a fixed allocation? There are 6 faults, indicated by *

8.12 Consider a page reference string for a process with a working set of M frames, initially all empty. The page reference string is of length P with N distinct page numbers in it. For any page replacement algorithm, a. What is a lower bound on the number of page faults? b. What is an upper bound on the number of page faults?

What is a lower bound on the number of page faults? Lower Bound: N. The reference string indicates that the program actually references N distinct pages, and the best that any page replacement algorithm can do is make the first page fault for a page the last. What is an upper bound on the number of page faults? Upper Bound: P. The worst possible situation is one where the working set is so small, and the page replacement algorithm so inept, that every reference to a new page in the reference string is a page fault.

Consider a simple segmentation system that has the following segment table: Starting Address Length (bytes) 660 248 1,752 422 222 198 996 604 For each of the following logical addresses, determine the physical address or indicate if a segment fault occurs: a. 0, 198 b. 2, 156 c. 1, 530 d. 3, 444 e. 0, 222

\item 660 + 198 = 858 \item 222 + 156 = 378 \item Segment 1 has a length of 422 bytes, so this address triggers a segment fault. \item 996 + 444 = 1440 \item 660 + 222 = 882

Consider a variant of the RR scheduling algorithm where the entries in the ready queue are pointers to the PCBs. a. What would be the effect of putting two pointers to the same process in the ready queue? b. What would be the major advantage of this scheme? c. How could you modify the basic RR algorithm to achieve the same effect without the duplicate pointers?

a) In effect, that process will have increased its priority since by getting time more often it is receiveing preferentail treatment. b) The advantage is that more important jobs could be given more time, in other words, higher priority in treatment. The consequence, of course, is that shorter jobs will suffer. c) Allot a longer amount of time to processes deserving higher priority, on other words, have two ro more quantums possible in the RR scheme.

Chapter 9, 9.1 9.1 Consider the following workload: Process Burst Time Priority Arrival Time P1 50 ms 4 0 ms P2 20 ms 1 20 ms P3 100 ms 3 40 ms P4 40 ms 2 60 ms a. Show the schedule using shortest remaining time, nonpreemptive priority (a smaller priority number implies higher priority) and round robin with quantum 30 ms. Use time scale diagram as shown below for the FCFS example to show the schedule for each requested scheduling policy. 9.6 / KEY TERMS, REVIEW QUESTIONS, AND PROBLEMS 427 Example for FCFS (1 unit = 10 ms): P1 P1 P1 P1 P1 P2 P2 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P4 P4 P4 P4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 b. What is the average waiting time of the above scheduling policies?

a. Example for FCFS (1 unit = 10 ms): P1 P1 P1 P1 P1 P2 P2 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P4 P4 P4 P4 b. Average waiting time: (20+0+70+10)/4 = 25ms. Explanation: P2 does not wait, but P1 waits 20ms, P3 waits 70ms and P4 waits 10ms.

A process contains eight virtual pages on disk and is assigned a fixed allocation of four page frames in main memory. The following page trace occurs: 1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 4, 5, 1, 5, 2, 4, 5, 6, 7, 6, 7, 2, 4, 2, 7, 3, 3, 2, 3 a. Show the successive pages residing in the four frames using the LRU replacement policy. Compute the hit ratio in main memory. Assume that the frames are initially empty. b. Repeat part (a) for the FIFO replacement policy. c. Compare the two hit ratios and comment on the effectiveness of using FIFO to approximate LRU with respect to this particular trace.

a. Hit ratio = 16/33 1 0 2 2 1 7 6 7 0 1 2 0 3 0 4 5 1 5 2 4 5 6 7 6 7 2 4 2 7 3 3 2 3 PF1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 PF2 - 0 0 0 0 0 6 6 6 6 2 2 2 2 2 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 PF3 - - 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 2 2 2 2 7 7 7 7 7 7 7 7 7 7 7 PF4 - - - - - 7 7 7 7 7 7 7 3 3 3 3 1 1 1 1 1 6 6 6 6 6 6 6 6 3 3 3 3 F F F F F F F F F F F F F F F F F c. Compare the two policy's effectiveness with respect to this trace. The two policies are equally effective for this particular page trace.

Consider a simple paging system with the following parameters: 2^32 bytes of physical memory; page size of 2^10 bytes; 2^16 pages of logical address space. a. How many bits are in a logical address? b. How many bytes in a frame? c. How many bits in the physical address specify the frame? d. How many entries in the page table? e. How many bits in each page table entry? Assume each page table entry contains a valid/invalid bit.

a. How many bits are in a logical address? The number of bytes in the logical address space is (2^16 pages) × (2^10 bytes/page) = 2^26 bytes. Therefore, 26 bits are required for the logical address. b. How many bytes are there in a frame? A frame is the same size as a page, 2^10 bytes. c. How many bits in the physical address specify the frame? The number of frames in main memory is (2^32 bytes of main memory)/(2^10 bytes/frame) = 2^22 frames. So 22 bits is needed to specify the frame. d. How many entries are there in the page table? There is one entry for each page in the logical address space. Therefore there are 2^16 entries. e. How many bits are there in each page table entry? Assume each page table entry contains a valid/invalid bit. In addition to the valid/invalid bit, 22 bits are needed to specify the frame location in main memory, for a total of 23 bits

8.3 a. How much memory space is needed for the user page table of Figure 8.4 ? b. Assume you want to implement a hashed inverted page table for the same addressing scheme as depicted in Figure 8.4 , using a hash function that maps the 20-bit page number into a 6-bit hash value. The table entry contains the page number, the frame number, and a chain pointer. If the page table allocates space for up to 3 overflow entries per hashed entry, how much memory space does the hashed inverted page table take?

a. How much memory space is needed for the user page table of Fig. 8.4? 4 Mbytes b. Hashed inverted table for above, 20-bit PN 6-bit hash number. Entry = page number, frame number, chain pointer; 3 overflow entries per table entry. What is the inverted page table size? Number of rows: 26+3=256 entries. Each entry consist of: 20 (page number) + 20 (frame number) + 8 bits (chain index) = 48 bits = 6 bytes. Total: 256 × 6= 1536 bytes Alternate possibility: 3 overflow includes initial entry 128 × 6 = 768

Consider a buddy system in which a particular block under the current allocation has an address of 011011110000. a. If the block is of size 4, what is the binary address of its buddy? b. If the block is of size 16, what is the binary address of its buddy?

a. If the block is of size 4, the binary address of its buddy is 011011110100 b. f the block is of size 16, the binary address of its buddy is 011011100000.

Consider a system with a total of 150 units of memory, allocated to three processes as shown: Process Max Hold 1 70 45 2 60 40 3 60 15 Apply the banker's algorithm to determine whether it would be safe to grant each of the following requests. If yes, indicate a sequence of terminations that could be guaranteed possible. If no, show the reduction of the resulting allocation table. a. A fourth process arrives, with a maximum memory need of 60 and an initial need of 25 units. b. A fourth process arrives, with a maximum memory need of 60 and an initial need of 35 units.

a. Solution: Yes, it is safe. After allocating 25 units to the process 4, there are still 25 unused units. Process 2 can use 20 of these units to complete, therefore freeing additional 40 units. Now, with 65 units available, any process can run to completion as long as 65 available units are not immediately spread among multiple processes. b. A fourth process arrives, with a maximum memory need of 60 and an initial need of 35 units.

8.17 Assume that a task is divided into four equal-sized segments and that the system builds an eight-entry page descriptor table for each segment. Thus, the system has a combination of segmentation and paging. Assume also that the page size is 2 Kbytes. a. What is the maximum size of each segment? b. What is the maximum logical address space for the task? c. Assume that an element in physical location 00021ABC is accessed by this task. What is the format of the logical address that the task generates for it? What is the maximum physical address space for the system?

a. What is the maximum size of each segment? 8 × 2K = 16K b. What is the maximum logical address space for the task? 16K × 4 = 64K c. What is the maximum physical address space for the system? 232 = 4 GBytes c. Assume that an element in physical location 00021ABC is accessed by this task. What is the format of the logical address that the task generates for it? image so nope

Suppose the following two processes, foo and bar are executed concurrently and share the semaphore variables S and R (each initialized to 1) and the integer variable x (initialized to 0). void foo( ) { do { semWait(S); semWait(R); x++; semSignal(S); SemSignal(R); } while (1); } void bar( ) { do { semWait(R); semWait(S); x--; semSignal(S; SemSignal(R); } while (1); } a. Can the concurrent execution of these two processes result in one or both being blocked forever? If yes, give an execution sequence in which one or both are blocked forever. b. Can the concurrent execution of these two processes result in the indefinite postponement of one of them? If yes, give an execution sequence in which one is indefinitely postponed.

a. foo: semWait(S) bar: semWait(R) foo: semWait(R) - blocked bar: semWait(S) - blocked b,. No

Five batch jobs, A through E, arrive at a computer center at essentially the same time. They have an estimated running time of 15, 9, 3, 6, and 12 minutes, respectively. Their (externally defined) priorities are 6, 3, 7, 9, and 4, respectively, with a lower value corresponding to a higher priority. For each of the following scheduling algorithms, determine the turnaround time for each process and the average turnaround for all jobs. Ignore process switching overhead. Explain how you arrived at your answers. In the last three cases, assume that only one job at a time runs until it finishes and that all jobs are completely processor bound. a. round robin with a time quantum of 1 minute b. priority scheduling c. FCFS (run in order 15, 9, 3, 6, and 12) d. shortest job first

a. round robin with a time quantum of 1 minute 1 2 3 4 5 Elapsed Time ============================ A B C D E 5 A B C D E 10 A B C D E 15 A B D E 19 A B D E 23 A B D E 27 A B E 30 A B E 33 A B E 36 A E 38 A E 40 A E 42 A 43 A 44 A 45 Process Turnaround Time ======================== A 45 B 35 C 13 D 26 E 42 Average Turnaround Time = 32.2 minutes b. priority scheduling Process Priority Turnaround Time ================================== B 7 9 E 6 21 A 4 36 C 3 39 D 1 45 Average Turnaround Time = 30 minutes c. FCFS (run in order 15, 9, 3, 6, and 12) Process Turnaround Time ======================== A 15 B 24 C 27 D 33 E 45 Average Turnaround Time = 28.8 minutes d. shortest job first Process Running Time Turnaround Time ====================================== C 3 3 D 6 9 B 9 18 E 12 30 A 15 45 Average Turnaround Time = 21 minutes

Let buddy k ( x ) address of the buddy of the block of size 2 k whose address is x . Write a general expression for buddy k ( x ).

buddyk(x) = x + 2^k if 2^k+1 divides x otherwise, x = 2^k

The two variables a and b have initial values of 1 and 2, respectively. The following code is for a Linux system: Thread 1 Thread 2 a = 3; — mb(); — b = 4; c = b; — rmb(); — d = a; What possible errors are avoided by the use of the memory barriers?

can figure it out

8.2

code

Chapter 7.1

comparison from chapter 2 (lets argue against it :D)

7.6, 7.7

drawing nope, table/binary tree nope

6.18-20, 21

figures and table, long ass code,

7.15

image

10.2-8

no clue

7.13

no clue

8.19

no clue

8.7-8.9

no clue

9.12-14

no clue

9.15

no clue

9.4-10

no clue

Consider the following ways of handling deadlock: (1) banker's algorithm, (2) detect deadlock and kill thread, releasing all resources, (3) reserve all resources in advance, (4) restart thread and release all resources if thread needs to wait, (5) resource ordering, and (6) detect deadlock and roll back thread's actions.

no clue

8.13-4, 5, 6

no clue, draw, no clue

7.10,7.11

no clue, figure

Assuming a page size of 4 Kbytes and that a page table entry takes 4 bytes, how many levels of page tables would be required to map a 64-bit address space, if the top level page table fits into a single page?

page size = 4KB = 2^12 PTE = 4B = 2^2 total entries possible in page table if page table is of size equal to page size = 2^12 / 2^2 = 2^10 entries. ADDSPACE = 64bits = 2^64 locations Standard Page Table Implementation:The number of entries in the page table is determined by the number of virtual pages available and not the number of page frames. dividing ADDSPACE into pages = 2^64 / 2^12 = 2^52 pages level A(bottommost) = 2^54 / 2^10 = 2^42 page tables level B = 2^42 / 2^10 = 2^32 page tables level C = 2^32 / 2^10 = 2^22 page tables level D = 2^22 / 2^10 = 2^12 page tables level E = 2^12 / 2^10 = 2 page tables level F = 1 page table storing info of 2 page tables at level E so total 6 levels. However, if using inverted page tables, then you would have one entry per page frame. This is the case with some 64-bit systems, where the size of the virtual memory is enormous. [http://www.urch.com/forums/gre-computer-science/78456-number-entries-page-table.html] Therefore, size of physical memory is required.

6.1-4, 6.5, 6.6, 6.7, 6.8, 6.9-6.10

picture so guessing no, to long, code, image, continue on, no answer

Evaluate the banker's algorithm for its usefulness in an OS.

you should know this