Digital Systems Design Test 1

signal propagation delays through interconnect

- delays due to physical nature of real wires -always non-zero cause we live in reality -FPGAs have significant routing delays because of programmable routing

Random Access Memory (RAM)

- more efficient than registers for storing large amounts of data -can read and write to RAM -addressable memory -can be with clock or with out (synchronous vs. asynchronous) -dimensions: (depth) x (width)

types of ASIC technologies

- full costume flow -standard cells -gate arrays

Static Timing Analysis

-a method of validating the timing performance of a design by checking all possible path for timing violations -generally performed and MIN and MAX conditions

RAM -width

-amount of data stored in one location -set by user

RAM- depth

-number of locations -set by user

Look Up Table (LUT)

-used to realize any boolean function -quick programable device for a truth table

ASIC or FPGA

ASIC- have non-recurring engineering cost Low production volume= FPGA high production volume=ASIC ASIC generally have higher performance

S'R' Latch

NAND gates used to create a lanch

sequential logic - storage

a feedback loop allows us to store data for an infinite amount of time

Configurable logic blocks (CLBS)

basically 'blocks' in device that contain four 6-input LUTs and eight storage elements

ENTITY in VHDL

declares the input and output signals naming guy

Architecture in VHDL

describes the function, describes what the entity's do.

4-bit ripple carry VHDL with generate

entity adder4 is port (cin : in std_logic; x,y : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); cout : out std_logic); end adder4; architecture structure of adder4 is c(0) <= cin; cout <= c(4); g1: for i in 0 to 3 generate stages: fulladd port map (c(i), x(i), y(i), s(i), c(i+1)); end generate; end structure;

D Latch in VHDL

entity latch is port (d,clk : in std_logic; q : out std_logic); end latch; architecture behavior of latch is begin process (d,clk) begin if clk = '1' then q <= d; end if; end process; end behavior;

priority encoder VHDL

entity priority is port (w : in std_logic_vector(3 downto 0); y : out std_logic_vector(1 downto 0); z : out std_logic); end priority; architecture behavior of priority is begin y <= "11" when w(3) = '1' else "10" when w(2) = '1' else "01" when w(1) = '1' else "00"; z <= '0' when w = "0000" else '1'; end behavior; //////can also use process statements and IF-else statements to write this

frequency equation

f=1/ ~fancy t~ ~fancy t~ is period

true of false : VHDL is a programming language

false : hardware description language

FIFO

first in, first out uhhh i don't get why we learned there

inverse of period is ..... (tricky one ! )

frequency (come on, we should know this by now)

pin to pin combinational delay

input pin to output pin with no intervening registers

duty cycle equation

ratio of pulse width to period (in %): duty cycle = P / ~fancy t~ where P= pulse width and ~fancy t~ is period

calculate throughput time

through put = (number of results) / (clock periods it took to get those results)

Mealy Machine

A finite state machine that determines its outputs from the current state and current inputs.

Latch vs Flip Flop

Latch = edge sensitive flip flop = level sensitive

Pros and cons of system on a programmable chip

Pros: reconfigurable nature, short development cycle Cons: higher unit costs in production, relatively high power consumption

Pipelining

Technique that allows the CPU to work on more than one instruction at a time - this will increase latency (youre adding DFF) but decreases miminum clock period

hard core vs soft core processor

hard core = less configurable but have higher performance than soft core hard core has an additional embedded processor, soft core uses existing logic elements on device soft core= allows for more specification of parameters than hardcore

lower Vdd means _______ delays

longer

clock to output delay

longest combinational path from Q DFF output to any output pin

input to register delay

longest combinational path from input pin to D Dff input

sequential logic - latch

makes or breaks the feedback loop where a bit is being stored so that way we can use it ! yay!

Maximum frequency equation

max freq = 1 / (longest delay path)

longest path delay

maximum delay is the longest single-path delay from input to output

standard cells - ASIC technology

pretty much full costume, but gates are already set designer uses a library of standard cells transistor density and performance decreases compared to full costume flow faster design time than full costume flow still involves creation of custom chip, same manufacturing costs/time as full costume flow

SRAM

static random access memory, larger than DRAM, fast boys

Full custom flow - ASIC technology

takes a long time to do but get the best result designer has to be an expert in VLSI high trsnsitor density cause the guy has to hand draw transistors high fabrication costs

White Box Testing

testers use their knowledge of system internals when testing the system • Dependent on implementation

hold time (T hd)

the amount of the time the synchronous input(D) must be stable ~after~ the active edge of the clock

latency

the amount of time between when an input is applied and the corresponding output is produced -latency on all paths needs to be the same to keep operands synchronized (ie make sure all paths have the same number of DFFs)

setup time (T su)

the amount of time the synchronous input (D) must be stable ~before~ the active edge of the clock.

WE on RAM

write enable - must assert WE for write to occur, when de-asserted read occurs

types of programmable technologies

- programmable logic devices(PLDS) -Complex PLDS -Field programmable gate arrays(FPGAs)

FMS have three fundamental blocks

- state memory (flip flops) -next state logic -output logic

Combinational logic propagation delays

- transistors within a date take a finite amount of time to switch -smaller transistors = faster switching times

bottom-up HDL design approach

-good for designing simple components -testing desired functionality can be integrated into larger designs

FPGAs [Field Programmable Gate Arrays]

-not application specific -manufactured by the IC vendor -basically it is made up of primitive logic blocks that are interconnected by a set of programmable switches in matrix form -reprogrammable in the field -embedded memory -can be used for prototype and verify designs before investing in technologies with high start up costs -performance and transistor density is lower than standard cell

Top-down HDL design approach

-rapid time to market requirements -reduced non-recurring engineering costs -design reuse facilitated -flexibility in design changes post-production

hardware description language

-what VHDL is, not a programming language! -statements in HDL are transformed into gates statements can be rearranged and still produce the same result

test-bench approach

1) apply a set of inputs 2) delay a set amount of time 3) check the output against a known results 4) rinse and repeat ;)

Steps to using FSM to design a logic system

1. Form a complete state spanning tree. 2. Form a complete state-output table from the spanning state tree. 3. Using the state-output table, minimize (remove redundant or impossible) states and draw the FSM state diagram (ASM chart). 4. Select your state encoding. 5. From the minimized FSM state diagram, create a FSM state transition table. 6. Select your FF. 7. Create FF excitation table. 8. Derive the excitation (next-state) equations. 9. Derive the output equations. 10. Draw the logic schematic and/or capture it in an HDL

Complex PLD (CPLD)

A digital device consisting of several programmable sections with internal interconnections between the sections. want more chips--> put more PLDs on each chip

moore machine

A finite state machine whose output is determined only by the current state

Flip-Flop

A flip-flop is a single-bit storage unit with two stages (master/slave). • The first stage (master) accepts input (flip). • The second stage (slave) gives output as received by the first stage (flop).

D Flip-Flop

A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs

Shift Register

Digital circuit that accepts binary data from some input source and then shifts these data through a chain of flip-flops one bit at a time.

DRAM

Dynamic Random Access Memory. Dynamic RAM. The slowest type of RAM, which requires frequent electrical refreshes to keep contents valid. small boys

Company A is a huge international semiconductor manufacturer. They want to build the fastest chip on the market and can afford to hire the best digital designer. What kind of implementation scheme will they most likely use?

Full Custom Flow

Functional vs. Timing simulation

Functional simulation = user specific input values and the outputs are generated. propagation is negligible. does my circuit do what i want it to do? timing simulation = all placements and routing delays are in place. when i program this on a device, will it behave the way i want it to?

Company B is a start-up with a great idea, but not a lot of money to implement it. They are trying to prove their concept in a simple prototype device to show possible venture capitalists. Their device must operate as fast as possible to impress them. What kind of implementation scheme will they most likely use?

Gate array because still has higher performance than CPLD/FPGA but costly slightly less than full custom/standard cell

what are the library's to use

LIBRARY ieee; use STD_LOGIC_1164.all; and/or use STD_LOGIC_VECTOR;

SR Latch

NOR gates uses feedback to "store" a bit

Simple PLDs

PAL, PLA, PROM idk man mostly just gates , very simple stuff

RAM -single port, dual port, True dual port, ROM

Single Port = one access port capable of read and write Dual Port = one read port, one write port True Dual port= two access ports, each capable of read and write ROM= read only memory, data programmed permanently

Company C has been hit hard by the economy and had to lay off their top VLSI expert. However, they still need fast chips and a lot of them. Their plan is to beat Company A to market with their design to get a foothold. What kind of implementation scheme will they most likely choose?

Standard cell, unit cost for many chips is low, don't need to be a VLSI expert to design them, design time is shorter than full custom flow, still high performance

Black box testing

Testing, either functional or non-functional, without reference to the internal structure of the component or system. test doesn't know what will break it • Independent of implementation we like this one for vhdl :)

calculating external hold times

Thd,sys = Thd,FF + Tpd,clk(max) - Tpd,DIN(min) -worst case hold time for DIN occurs when clock is delayed, requiring DIN to hold its value longer

T plh vs Tphl ~propagation delay stuff ~

Tplh - time between a change in an input and a low-to-high change on the output Tphl- time between a change in an input and a high-to-low change on the output

true or false : the process statement is sequential

True, outside of the process statement though VHDL is not sequential

calculating external setup times

Tsu,sys = Tsu,FF + Tpd,DIN(max) - Tpd,clk(min)

validation vs. verification

Validation: Are we building the right product? -Simulating device functionality -what we do when we (try to) create a test bench Verification: Are we building the product right? - Formally proving properties of the design

how do we satisfy hold time?

add buffers to the shortest lines to "beef" it up....aka make it take long, why did he have to say it like that?

gate arrays - ASIC technology

all gate array devices have identical lower layers which leads to faster production time and cheaper fabrication lowest transistor density -transistors are pre-placed and fixed in size

2-1 mux VHDL with process

architecture behavior of mux2to1 is begin process (w0,w1,s) begin if s = '0' then f <= w0; else f <= w1; end if; end process; end behavior;

D latch with enable

as long as Enable = 1, the latch will change according to the value of D.

behavioral vs. structural VHDL

behavior= describes behavior of the circuit without worrying about specifics of implementation structural = telling system exactly how you want if to be implemented

Combinational vs. sequential systems

combinational = output only depends on the input values sequential = output depends on current inputs and current state of the network via clock signal.

how to find latency of a system

count the number of DFFs between the input and the output

2-4 binary decoder VHDL

entity dec2to4 is port (w : in std_logic_vector(1 downto 0); en : in std_logic; y : out std_logic_vector(0 to 3)); end dec2to4; architecture behavior of dec2to4 is signal enw : std_logic_vector(2 downto 0); begin with enw <= en & w; y <= "1000" when "100", "0100" when "101", "0010" when "110", "0001" when "111", "0000" when others; end behavior;

D flip-flop with enable input

entity flipflop is port (en,d,clk : in std_logic; q : out std_logic); end flipflop; architecture behavior of flipflop is begin process (clk) begin if en = '0' then null; elsif rising_edge(clk) then q <= d; end if; end process; end behavior;

single-bit full adder VHDL

entity fulladd is port (cin,x,y : in std_logic; s,cout : out std_logic); end fulladd; architecture logicfunc of fulladd is begin s <= x xor y xor cin; cout <= (x and y) or (cin and x) or (cin and y); end logicfunc;

4-1 multiplexor VHDL

entity mux4to1 is port (w : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); f : out std_logic); end mux4to1; architecture behavior of mux4to1 is begin with s select f <= w(0) when "00", w(1) when "01", w(2) when "10", w(3) when others; end behavior;

system on a programmable chip

includes large number of logic gates, memory on the device, intellectual property (IP) processor core basic premise = have all components on a single chip

what does it mean to be a "transparent" latch? how to fix?

level-sensitive: when the latch is enable, the output will follow the input fix by splitting the input and output so they are independent.

counters --- 4 bit up-counter VHDL example

library ieee; use ieee.std_logic_1164.all; -- use numeric_std to include -- signed and unsigned data types use ieee.numeric_std.all; entity upcount is port (clk,reset_n,en : in std_logic; q : out std_logic); end upcount; architecture behavior of upcount is signal count : unsigned(3 downto 0); begin process (clk,reset_n) begin if reset_n = '0' then count <= "0000"; elsif (clock'event and clock = '1') then if en = '1' then count <= count + 1; else count <= count; end if; end if; end process; q <= count; end behavior;

higher temperatures mean _______ delays

longer

register to register delay

longest combinational path from Q DFF output to D DFF input Delay = Tc2q + Tpd,max + Tsu

Synchronous vs. asynchronous input

• Synchronous: the output will change after an active clock edge, safe • Asynchronous: the output will change independent of the clock, can introduce glitches in your system