ELEN 333 Midterm

FFs can be synchronously or asynchronously resettable

-Synchronously resettable FFs reset themselves only on rising edge of CLK -Asynchronously resettable FFs reset themselves as soon as RESET is TRUE

AD Converter Ranges

0 -> Vil = LOW Vih -> Vdd = HIGH Forbidden Zone: Vil -> Vih = unpredictable

Gates

1. Concurrent signal assignment statement Ex: [out <= (in0 OR in1)] 2. Statement - complete command Ex: [out <= a NAND b);] Expression: combination of operators and operands

Parts of VHDL

1. Library use clause 2. Entity Declaration: lists module name and I/O 3. Architecture Body: defines module's tasks TIP: I/O signals need type declaration Digital Signals - STD_LOGIC

Number Types

1. Unsigned: int is pos 2. Signed: int can be pos or neg 3. Sign-magnitude: Sign is indicated by msb or (+ or -) Ex: [-4]base10, [1000]bas2 [+4]bas10, [11000]base2 4. Two's Complement: Process: invert bits, then add 1 +2bas10=0010bas2 -2bas10=(1101)bas2 + 1bas10 -2bas10 = (1110)

rules of bubble pushing

1. begin at output and work towards inputs 2. push an output bubble back, putting a bubble on all inputs 3. if there is an input and output bubble on same line, they cancel 4. bubble pushing switches AND gates to ORs and OR gates to ANDs

minterm/maxterm

1. minterm is a product involving all inputs corresponding to a 1 output: ABC (SOP) 2. maxterm is a sum involving all inputs corresponding to a zero output: A+B+C (POS)

rules of finding implicants in K-map

1. must be all 1's 2. must use fewest, largest circles possible 3. each circle must span a rectangular block that is a power of 2 (1, 2, 4) 4. circles can wrap around 5. a 1 can be circled multiple times

D Latch

2 inputs, D & CLK, and 2 outputs, Q & Q ̅

Binary weights

2^0 = 1 2^1 = 2 2^2 = 4 2^3 = 8 2^4 = 16 2^5 = 32 2^6 = 64 2^7 = 128

Nibble

4 bits

measuring delay

50% point of the input signal to the 50% point of the output

byte

8 bits

<= and :=

<= is a non-blocking assignment, evaluated concurrently, made to outputs and signals := is a blocking assignment evaluated in the order that appear in the code, made to variables (used in full adder, but p and g must be declared as variable and not signal)

Gray Code

A and B combinations in the top row are in a peculiar order: 00, 01, 11, 10

Techniques for Managing Complexity

Abstraction Discipline 3-Y's hierarchy modularity regularity

Bitwise Operator

Acts on a signal or bus Examples: binary logical operators (&, |, ^) binary shift operators (<<, >>, >>>)

Styles of Functionality

Behvioral: describes module's tasks Structural: describes modularity

Module

Block of hardware with I/O

logic gates are built from:

CMOS transistors, which behave as electrically controlled switches

Complement

Complement - inverse of the variable (A')

amount of information measured in bits

D = log(base 2)N bits

HDL

Hardware Description Language VHDL & Verilog

regularity

Managing Complexity: ensuring uniformity among modules so that common modules can be reused many times

modularity

Managing Complexity: giving modules well-defined functions and interfaces, so that they connect together easily without side effects

abstraction

Managing Complexity: hiding details when they are not important

discipline

Managing Complexity: intentionally restricting your design choices so you can work more productively at a higher level of abstraction

decoder

N inputs and 2^N outputs

dynamic power

P = 1/2CV^2f

static power

P = I * V

full adder equation

S = (A XOR B) XOR Cin Cout = AB + ACin + BCin

asynchronous

Sequential circuits that are not synchronous are called

Parts of Vivado

Simulation: catches bugs Synthesis: transforms text description into logic gates Idioms: specific ways of describing classes of logic

Word

The size of a memory location expressed in bytes. The exact number varies by CPU model. Ex: [32-bit Arch]

AD Converter Key

Voh = Logic High Output Range Vol = Logic Low Output Range NMh = Noise Margin High NMl = Noise Margin Low Vih = Logic High Input Range Vil = Logic Low Input Range Vdd = Supply Voltage

NOT, AND, and OR gates

[NOT] inverts (input != output) : Y=A ̅ [AND] - if(both == 1) : Y=AB [OR] - if(either == 1) : Y=A+B

XOR, NAND, NOR, XNOR gates

[XOR] if(odd value) : Y = A ⊕ B [NAND] inverts AND : Y=(AB) ̅ [NOR] inverts OR : Y=(A+B) ̅ [XNOR] inverts XOR : Y=(A⊕B) ̅

delay

a <= (b and (not c)) after 4 ns;

:= appears in the process statement

a blocking assignment

illegal value x

a circuit node has an unknown or illegal value represented by x usually happens when a node is being pushed to high and low at the same time

bit swizzling

a collection of operations used to operate on a subset of a bus or to join together busses

resettable flip-flop

adds another input called RESET

enabled flip-flop

adds another input, EN or ENABLE, to determine if data is loaded on the clock edge

prime implicants

an implicant that cannot be combined with any other implicants to form a new implicant with fewer literals the implicants in a minimal equation must be all prime implicants

why do we use gray code?

because it allows adjacent entries to only differ in one variable

case statements

begin process (input variable) begin case data is when X"0" => output <= "11111110"; ... end case; end process; end;

if statements

begin process (input variable) begin if input(3) = '1' then output <= "11111110"; elsif input(2) = '1' then output <= "11111011"; ...else output <= "0000000"; end if; end process; end;

how to use an output as an input in VHDL

buffer v : buffer STD_LOGIC;

bus

bundle of multiple signals

multiplexer

chooses an output from several inputs based on value of a select signal 2^N-1 mux size: N = number of inputs(a,b,c = 3)

CMOS

complementary metal-oxide semiconductor provide both types of transistors, and are used to build the majority of all transistors fabricated today nMOS - if('1') turn ON pMOS - if('0') turn ON

SR Latch

composed of 2 cross-coupled NOR gates -2 inputs, S & R -2 outputs, Q & Q ̅

State variables

contain all information about the past necessary to explain future circuit behavior

critical path & short path

critical: the longest path; slowest determines expected circuit duration short: shortest path and fastest with least gates

structural modeling

describes how module built from different pieces: application of hierarchy

schematic

diagram of a digital circuit showing the elements and wires that connect them together

digital compared to analog

digital: all values in the system represented by a series of digits analog: represents data by measurement of a continuous physical variable, as voltage or pressure

hierarchy

dividing a system into modules, then further subdividing each of these modules until the pieces are easy to understand

powers of 2

find greatest 10th power, then find the constant with the remaining: 2^36 => 2^30 = billion 2^6 = 64 THEREFORE 64 billion

bistable element

has 2 stable states, is the fundamental building block of memory

complex systems are designed

hierarchically

digital

implies that values in the system are fully represented by a series of digits

don't cares

indicated by x in a truth table can be either 0 or 1 output value is unimportant allow for more logic minimization

floating value z

indicates the circuit node is being driven neither high nor low node is said to be floating, high impedance, or high z not the same as logic 0

product of sums

look for 0's in final column (maxterm)

sum of products

look for 1's on final column (minterm)

cyclic paths

loops in which outputs are fed directly back to inputs

Inverters are cross-coupled

meaning that I1's input is I2's output & vice-versa

behavioral modeling

models that describe what a module does

<= in the process statement is called

non-blocking assignment

Sequential logic

output values depend on both current and prior input values -sequential logic has memory

calculating propagation and contamination

propagation: sum of prop. delay time x number of gates contamination: sum of cont. delay time x number of gates

process (a)

reevaluates the statements inside the begin/end process block any time a changes

static discipline

requires that, given logically valid inputs, every circuit element will produce logically valid outputs

rising/falling edge

rising - transition from low to high falling - transition from high to low

Synchronous sequential circuit composition

rules show that a circuit is synchronous sequential if it consists of interconnected elements s.t.:

VHDL process statements are used to describe __________________because they remember the old state when no new state prescribed

sequential circuits

Functional

specification details

bitstream generation

stages of digital design that the description of HDL module is transformed into logic gates

contamination delay

tcd, minimum time from when an input changes until any output starts to change value

race condition

that causes it to fail when certain gates are slower than others

product/implicant

the AND of >=1 literals

noise margin

the amount of noise that could be added to a worst case output such that the signal can be a valid input / how much noise it can tolerate 1st gate <= driver; 2nd gate <= receiver NMl = Vil - Vol NMh = Voh-Vih Vol < Vil Voh > Vih

True Form

the variable's original form (A)

simulation

to catch bugs / human mistakes

X values

to indicate an uninitialized value

propagation delay

tpd, maximum time from when an input changes until the outputs reach their final value

synthesis

transforms textual description of an HDL module into logic gates

using a signal

use before begin in architecture signal p : STD_LOGIC;

Literal

variable or its complement

glitches

when a single input transition causes multiple output transitions can avoid glitch by adding another gate, circle another overlapping implicant in k-map

unity gain points

where the slope of V(Y)/V(A) = -1

synchronous sequential circuit

•(SSC) has a clock input, whose rising edges indicate a sequence of times at which state transitions occur

tristate buffer

•3 possible output states: HIGH (1), LOW (0), and floating (Z)

Timing specification consists of

•An upper bound, tpcq, & a lower bound, tccq, on time from rising edge of clock until output changes

testbench

•HDL module that is used to test another module •Tested module is called device under test (DUT) or unit under test (UUT)

Karnaugh Maps (K maps)

•are a graphical method for simplifying Boolean equations

Structural modeling

•describes a module in terms of how it is composed of simpler modules

complex systems are designed _______

•hierarchically