Intro To Systems LC-3 Assembly Notes

You are in the process of debugging a program you've written. You decideto focus your debugging on the following segment of code by setting a breakpoint at xA400. You run the code up to the breakpoint, clear the registers, and step through the code starting at that point. 0xA400: THIS1 LEA R0, THIS1 0xA401: THIS2 LD R1, THIS2 0xA402: THIS3 LDI R2, THIS5 0xA403: THIS4 LDR R3, R0, #2 0xA404: THIS5 .FILL xA400 What is the the value in register R2 when .FILL at location 0xA404 is reached?Give your answer in hex and omit the leading x or X.

E1FF

The interface between the CPU and an I/O device is the

I/O controller

The register that is used to synchronize the transfer of data between the LC-3 CPU and the keyboard is the

KBSR

Consider the multiplexer that selects the input value for the MDR in figure 8.4. Name an LC-3 instruction (assembly opcode only) that will cause the multiplexer to select its rightmost input.

LD

Consider the following incomplete LC-3 assembly program: ; load missing HERE .FILL THERE THERE.FILL x4444 Which of the following loads will cause x4444 to be loaded into R0?

LDI R0, HERE

What instruction is executed that causes the an interrupt service routine to be exited and control to return to the interrupted process?

RTI

Consider the multiplexer that selects the input value for the MDR in figure 8.4. Name an LC-3 instruction (assembly opcode only) that will cause the multiplexer to select its leftmost input.

STI

The mechanism by which a user program invokes and executes a system service routine is the

TRAP

What values are stored in the Processor Status Register (PSR)?

The priority of the processor, A value indicating whether the program is running in user mode or supervisor mode, The values of the condition codes

Consider the following possible implementation of the statement:for (R1 = 0; R1 < 5; R1++) R2 = R2 + R1; (Of course, normally we don't have register names appear in high level code. We would instead have variables that are then allocated to certain registers by the compiler. By this, I'm showing both the use of the variables and the allocation.) The implementation: AND R3, R3, 0 ADD R3, R3, 5 NOT R3, R3 ADD R3, R3, 1 AND R1, R1, 0 TOP: ADD R4, R1, R3 BRZ DONE ADD R2, R2, R1 ADD R1, R1, 1 BRNZP TOP DONE

This implementation is correct (always produces correct result) and matches what a compiler would likely generate.

Consider the following possible implementation of the statement:while (R1 > R2) R1 = R1 - 1; The implementation: NOT R3, R2 ADD R3, R3, 1 TOP: ADD R4, R1, R3 BRNZ DONE ADD R1, R1, -1 BRNZP TOP DONE

This implementation is correct (always produces correct result) and matches what would be generated by a compiler.

Consider the following possible implementation of the statement:if (R1 == 0) R1 = R1 + 1 else R1 = R2 ; The implementation ADD R1, R1, 0 BRz then BRnp else then: ADD R1, R1, 1 BRnzp join else: ADD R1, R2, 0 BRnzp join join

This implementation is correct (always produces correct result) but doesn't match what would be generated by the compiler.

Consider the following possible implementation of the statement:while (R1 > R2) R1 = R1 - 1; The implementation: NOT R3, R2 ADD R3, R3, 1 TOP: ADD R1, R1, -1 ADD R4, R1, R3 BRP TOP DONE

This implementation is not correct (won't always produce correct result).

When the processor is interrupted, it is supplied with an interrupt vector. What is the interrupt vector?

an index into the Interrupt Vector Table

A trap vector is

an index into the system control block

If communication between the CPU and an I/O device is synchronized via control signals (for example, the device uses a ready signal to indicate to the CPU the data is ready to be read), then the transfer timing mechanism is known as

asynchronous

What things must be true in order for the currently running program to be interrupted:

both the ready bit and the interrupt enable bit of the device's status register are set, the INT signal has been asserted, the device that asserted the interrupt has higher priority

One way to uncover a logic error is to use a debugger to stop execution before the statement where the error is thought to occur. This allows the programmer to then look at values in registers and memory (or variables for high-level language debuggers) and step through the program statement by statement starting at the point where the execution stopped. Stopping execution like this is caused by setting a

breakpoint

If a called routine saves the registers it will use when the routine is called and restores the registers right before the called routine is exited then it is using a mechanism known as

callee save

If a calling routine saves registers right before a routine is called and restores registers after the called routine is exited then it is using a mechanism known as

caller save

If the I/O device controller sends a signal to the CPU to indicate new data has arrived (for a read operation) or to indicate the device is ready for new data (for a write operation), then I/O is being performed using a technique known as

interrrupt-driven

The purpose of the signal labeled MEM.EN in figure 8.2

it controls whether memory should respond to a request

When I get home from work, I start cooking dinner right away. My kids also start asking me every few minutes if dinner is ready. Relating this to I/O polling, who is the processor, mom, kids or dad (who is sitting on the couch reading Time magazine)?

kids

If a program runs to completion but produces the wrong result then it contains a

logic error

If I/O device controller registers are assigned memory addresses than I/O will be performed using a technique known as

memory-mapped I/O

I/O on the LC-3 is performed (at least according to chapter 8) using the following strategies [which indicate a) how device registers are specified b) how the transfer of data is timed c) who controls the transfer - CPU or I/O device]

memory-mapped, asynchronous, polling

When a program is interrupted, where is the state of that program saved?

on the supervisor stack

If the CPU continuously examines an I/O device controller status register to determine whether the device is ready to receive new data (for a write operation) or the device data register contains new data (for a read operation), then I/O is being performed using a technique known as

polling

If I/O devices registers are given an address space that is separate from the address space of memory than the I/O is performed using a technique

port-mapped I/O

A value passed out of a subroutine is called a(n)

return value

An operating system routine that can be called by a user program to perform low-level, privileged operation is a

service routine

If an I/O device controller provides data to the CPU at a fixed rate (or the CPU provides data to be written to the I/O device controller at a fixed rate), usually controlled by a shared clock, then the transfer timing is known as

synchronous

A type of error identified by an assembler (or compiler) is a

syntax error

The LC-3 CPU can tell that a character is available to be read when

the KBSR is negative

What parts of a program's state are stored when the program is interrupted?

the PC, the condition codes, the PSR

What is the difference between the LC-3 RTI and RET instruction?

the RTI restores the values of condition codes and the RET does not, the RTI gets the return address from the Supervisor Stack instead of R7, the RTI restores the value of the PSR and the RET does not

When would you want to use a JSRR instead of a JSR?

when the subroutine is located in a different file

Consider the following lc-3 assembly code: ld r0, num1 ld r1, num2 top: not r2, r1 add r2, r2, 1 add r2, r0, r2 brnz done add r1, r1, 1 brnzp top done: halt num1 .fill x39 num2 .fill x30 Below is an incomplete symbol table for the code above: Symbol - Address top - x3002 done - num1 - num2 - What is the encoding for the instruction brnz done?Give your answer in hex. (Omit the leading x or X.)

0C02

Consider the following lc-3 assembly code: ld r0, num1 ld r1, num2 top: not r2, r1 add r2, r2, 1 add r2, r0, r2 brnz done add r1, r1, 1 brnzp top done: halt num1 .fill x39 num2 .fill x30 Below is an incomplete symbol table for the code above: Symbol - Address top - x3002 done - num1 - num2 - What is the encoding for the instruction brnzp top?Give your answer in hex. (Omit the leading x or X.)

0FFA

Assume the data represented by the .fill below will be loaded into memory location x4020. What will be in memory location x4021? here .fill x4050 ld r1, here Give your answer in hex. (Omit leading x or X.)

23FE

You are in the process of debugging a program you've written. You decideto focus your debugging on the following segment of code by setting a breakpoint at xA400. You run the code up to the breakpoint, clear the registers, and step through the code starting at that point. 0xA400: THIS1 LEA R0, THIS1 0xA401: THIS2 LD R1, THIS2 0xA402: THIS3 LDI R2, THIS5 0xA403: THIS4 LDR R3, R0, #2 0xA404: THIS5 .FILL xA400 What is the the value in register R1 when .FILL at location 0xA404 is reached?Give your answer in hex and omit the leading x or X.

23FF

Consider the following lc-3 assembly code: ld r0, num1 ld r1, num2 top: not r2, r1 add r2, r2, 1 add r2, r0, r2 brnz done add r1, r1, 1 brnzp top done: halt num1 .fill x39 num2 .fill x30 Below is an incomplete symbol table for the code above: Symbol - Address top - x3002 done - num1 - num2 - What should be the address stored in the table for the symbol num2? Give your answer in hex. (Omit the leading x or X.)

300A

You are in the process of debugging a program you've written. You decideto focus your debugging on the following segment of code by setting a breakpoint at xA400. You run the code up to the breakpoint, clear the registers, and step through the code starting at that point. 0xA400: THIS1 LEA R0, THIS1 0xA401: THIS2 LD R1, THIS2 0xA402: THIS3 LDI R2, THIS5 0xA403: THIS4 LDR R3, R0, #2 0xA404: THIS5 .FILL xA400 What is the the value in register R0 when .FILL at location 0xA404 is reached?Give your answer in hex and omit the leading x or X.

A400

You are in the process of debugging a program you've written. You decideto focus your debugging on the following segment of code by setting a breakpoint at xA400. You run the code up to the breakpoint, clear the registers, and step through the code starting at that point. 0xA400: THIS1 LEA R0, THIS1 0xA401: THIS2 LD R1, THIS2 0xA402: THIS3 LDI R2, THIS5 0xA403: THIS4 LDR R3, R0, #2 0xA404: THIS5 .FILL xA400 What is the the value in register R3 when .FILL at location 0xA404 is reached?Give your answer in hex and omit the leading x or X.

A401