IT 225 - Computer Organization - Final Exam

If I attempt to access the L1 cache 24 times and get 18 hits, the hit rate of the L1 cache is __ %.

(18 / 24) = 0.75 = 75%

Convert .712 base 10 to base 5 using the division method. Show your work for full credit.

.56 * 5 = 2.8 .8 * 5 = 4 .324_5

For the attached picture showing the control (P_0 - 5) and bus lines connected to MARIE's MBR, fill in a "0" or "1" value for each control line so that the PC sends its current value to the MBR. The bus address for the MBR is 3, and the bus address for the PC is 2.

0, 1, 0, 1, 1, 0 011 is 3 010 is 2 P_0 - 2 are for placing data onto the bus P_3 - 5 are for taking data off the bus

Write the number positive 5 in 8 bit two's complement (base 2). Convert the number to its negative complement. Afterward, convert the number back to its positive complement (same number 5 we started with). Show your work for full credit.

00000101 (5) 11111010 (flip bits) 11111011 (add binary 1, -5) 11111011 (-5) 11111010 (subtract binary 1) 00000101 (flip bits, 5)

Multiply the following 4 bit unsigned integers using standard binary multiplication: 0100 and 0101.

0101 x0100 ------ 0000 0000 0101 0000 --------- 0010100

Write the numbers 98 and 20 in 8 bit base 2 two's complement. Add them together using binary arithmetic. Is the final answer correct? Why or why not?

01100010 (98) +00010100 (20) =01110110 (118) We didn't overflow and got the correct result.

I have a five input gate. How many rows exist in the gate's truth table (header not counted)?

32 (2^5)

Convert 41 in base 10 to base 2 using the subtraction method. Express your answer using a byte's worth of digits. Show all work for full credit.

41 - 32(2^5) = 9 - (2^3) = 1 - 1(2^0) = 0 00101001

A single full adder circuit is pictured. What will be the sum of the circuit for the following inputs: A = 1, B = 1, Carry-In = 0 A. 0 B. Unknown C. 1

A. 0

When expressing a number in hex, the positional weight of the digit three to the left of the radix point (decimal point in base10) is... A. 16^2 B. 16^0 C. 16^1 D. 16^3

A. 16^2

Base64 is best represented with how many bits per digit? A. 6 B. 8 C. 4 D. 16

A. 6

Which of the following components of a bus is most likely to transmit interrupts and error flags? A. Control Line B. Data Line C. Address Line D. Power Line

A. Control Line

A non-inverting buffer with a control line value of 0 and a data in of 1 will output A. Disconnect B. 0 C. 1

A. Disconnect

Which of the following levels in a multilevel machine is the "true machine language" that can be run by hardware? A. ISA/Machine Level B. OS/SS Level C. Digital Logic Level D. Control/Microarchitecture Level

A. ISA/Machine Level

I have an old mainframe system located in the United States. You are writing code to pass this mainframe alphanumeric string data. Which character code is most likely to be compatible with this system? A. Latin-1 ASCII B. Binary coded decimal C. UTF-8 D. Packed binary coded decimal

A. Latin-1 ASCII

Which of the following is the least likely to be found inside a computer's CPU? A. Main memory B. Buses C. Registers D. Control Unit E. ALU

A. Main memory

Which gates can be used to represent any other gate or circuit? (select many) A. NAND B. NOR C. AND D. NOT E. OR

A. NAND B. NOR

A CS value of 1, RD value of 1, and an OE value of 0 would cause what operation? A. Neither B. Write C. Read D. Both read and write

A. Neither

If I divided the two's complement binary number 11000010 in half using a right binary shift, would I overflow? Would I get a perfectly correct answer? A. No overflow, perfectly correct answer B. Overflow, perfectly correct answer C. No overflow, not perfectly correct answer D. Overflow, not perfectly correct answer

A. No overflow, perfectly correct answer

The graphics processing unit in your computer is most likely this type of processor A. SIMD B. MISD C. SISD D. MIMD

A. SIMD

Bus arbitration schemes (as with everything) are all about tradeoffs. Which statement below is NOT an advantage daisy chain arbitration could have over centralized parallel arbitration? A. You may give multiple devices the same priority level. B. You only need one bus request line. C. You don't need an arbiter. D. You can almost always construct the bus with fewer wires.

A. You may give multiple devices the same priority level.

Copy the "chart" between the lines below into your answer box. Then, replace each "#" sign with a 0, 1, or "Does Not Matter" such that the memory circuit will write the values stored in Word Line 2.

A_0 = 0 A_1 = 1 CS = 1 RD = 0 OE = Does Not Matter

What are two advantages a CISC computer has over a RISC computer? Elaborate on each advantage.

Add fixes - You can patch software later after production to fix issues. Add instructions - You can patch software later after production to extend the instruction set. Efficient development and testing - Software is easier than hardware to develop, test, and manufacture. Memory-efficient - CISC computers perform more work with less instructions than RISC, therefore needing less memory. Backwards compatibility - CISC systems can maintain the same instruction set longer and lend themselves to backwards compatibility.

Which of the following is an acceptable schema for a 32 bit signed floating bit number? A. 6 exponent bits, 26 significand bits B. 1 sign bit, 5 exponent bits, 26 significand bits C. 1 sign bit, 6 exponent bits, 26 significant bits D. 2 sign bits, 12 exponent bits, 18 significand bits

B. 1 sign bit, 5 exponent bits, 26 significand bits

The 5 steps of the Fetch-Decode-Execute cycle are below. Which number is the Data Path cycle? 1. Fetch the next instruction from memory into the instruction register using the program counter, then increment the program counter. 2. Decode the instruction. 3. Fetch data operands from memory into CPU registers. 4. The ALU executes the instruction and stores the result in registers or memory. A. 3 B. 4 C. 1 D. 2

B. 4

In MARIE, the indirect addressing instruction JUMP would contain a memory address in the instruction. What does the memory address point to in main memory? A. The operand to be used in instruction execution B. A pointer to the next instruction C. The next instruction D. A pointer to the operand to be used in instruction execution

B. A pointer to the next instruction

The register transfer notation below could be used for what operation? MAR <- X MBR <- M[MAR] MAR >- MBR MBR >- M[MAR] AC <- AC + MBR A. JnS B. ADD| X C. STORE| D. LOAD| X

B. ADD| X

Which of the following are the components of an instruction in MARIE's architecture? A. Instruction Register B. Address C. Memory contents D. Opcode

B. Address D. Opcode

If memory is 8 bits wide, changing from byte-addressed memory to word-addressed memory in a 32 bit word-length architecture will A. Quadruple the number of required addresses B. Divide the number of required addresses by 4 C. Double the number of required addresses D. Halve the number of required addresses

B. Divide the number of required addresses by 4

Which of the following is an example of conditional branching in MARIE's architecture? A. JUMP B. SKIPCOND C. ADD D. LOAD

B. SKIPCOND

Splitting instructions and data is common in registers and CPU caches because... A. Access to instructions needs to occur significantly faster than access to data B. Simultaneous access to instructions and data is common C. Access to data needs to occur significantly faster than access to instructions

B. Simultaneous access to instructions and data is common

Which of the following is NOT an example of a loosely coupled multiprocessor design? A. Two computers on a network working together on a common task. B. Three processors in the same computer that share memory. C. Four computers on a network that share a single operating system.

B. Three processors in the same computer that share memory.

If I wanted to halve a number, I could use A. a double right binary shift B. a right binary shift C. a left binary shift D. a double left binary shift

B. a right binary shift

Which of the following is the most likely to be stored in Read Only Memory (ROM)? A. Control Unit Microprogram Store B. Control Unit Registers C. Firmware recovery partition D. Main Memory Data

C. Firmware recovery partition

The number of clock cycles from when an interrupt is generated to when the process routine starts is the A. Hardware Interrupt Clock Time B. Hardware Interrupt Clock Speed C. Interrupt Latency D. Software Interrupt Clock Time

C. Interrupt Latency

Which of the following is NOT true as you move from the top of the memory hierarchy to the bottom? A. You can store more data B. Cost per bit generally goes down C. Latency generally goes down D. You can store more bits

C. Latency generally goes down

Which of the following types of parallelism is NOT instruction-level parallelism? A. Pipelining B. Superscalar processing C. Multiprocessors D. Vector processing

C. Multiprocessors

The primary benefit of a clocked D flip-flop over a clocked SR latch is the ability to A. Implement a clock to control the circuit B. Utilize an enable line to control when state can change C. Prevent the metastable state

C. Prevent the metastable state

ISU pays many vendors to host and support applications on our behalf. Which of the following does this example best describe? A. Compute as a Service B. Platform as a Service C. Software as a Service D. Infrastructure as a Service

C. Software as a Service

I have a circuit that validates whether the bits in two words are equal. What gate is most efficient at comparing if two inputs are equal? A. NAND B. NOR C. XOR D. NOT E. AND F. OR

C. XOR

A 1 bit ALU is pictured. Which function is selected by the decoder, and what is the value of the output bits? F_0 = 1, F_1 = 1, ENA = 1, ENB = 1, A = 1, B = 1, INVA = 0, Carry_in = 1 A. AND, Output = 0 B. AND, Output = 1 C. OR, Output = 0 D. OR, Output = 1 E. NOT B, Output = 0 F. NOT B, Output = 1 G. ADD, Output = 0, Carry Out = 0 H. ADD, Output = 1, Carry Out = 0 I. ADD, Output = 0, Carry Out = 1 J. ADD, Output = 1, Carry Out = 1

J. ADD, Output = 1, Carry Out = 1

One security feature of a modern operating system is the use of user mode and kernel mode. First, explain the difference between the two modes. Then, provide an example of an action user-mode might not be able to complete.

Kernel mode is the privileged mode with all instructions and memory addresses allowed in instructions. User mode will have restrictions to specific memory locations and instructions. Many examples are acceptable including unlisted ones: - process flow opcodes/instructions off limits - cannot access kernel memory - cannot access memory of other processes - cannot escalate to kernel mode without permission (if even supported)

For the Pentium processor discussed in class, state whether the L1 cache and L2 cache are Unified or Harvard designs. Explain why they are designed this way.

L1 - Harvard L2 - Unified L1 cache prioritizes performance over almost everything else, so Harvard cache is chosen to give better performance. The L2 cache is further and has a higher latency - so Unified is considered acceptable performance for the cost.

I can write the output of the ___ gate with inputs A and B as F(A, B) = A'B'.

NOR

What is the purpose of normalizing floating point numbers?

Normalization ensures that we only have one correct way to store each floating point number. Otherwise, we might have multiple ways to store each number.

I give you eight hard disks. I ask you to configure them in a reliable RAID configuration that can tolerate at least two drive failures. Which RAID configuration do you utilize? Justify your answer.

RAID 1 technically works. RAID 6. Many nested RAIDS, like 10, 50, or 60.

Explain the difference between sequential and parallel access to cache and main memory.

Sequential access starts at the L1 cache and works its way down the memory hierarchy (including higher level caches and main memory) until it finds the data it needs. Parallel access will request all levels of cache and main memory at the same time, use the first response it gets, and discard the data arriving later.

What data would the memory address register (MAR) hold in MARIE? Where would data in the MAR be sent after being written into the register?

The MAR holds a memory address. The address is always sent via a direct connection to main memory when reading or writing main memory.

Explain the purpose of an arbiter in centralized parallel bus arbitration.

The arbiter grants access to the bus. With centralized parallel arbitration, all bus-connected devices will have a request line to the arbiter, and the arbiter will have a mechanism for determining priority. Grants to the bus will flow over grant lines.

What does following program do (MARIE architecture)? LOAD 100 STORE 200 LOAD 300 STORE 400 ADD 200 HALT

The program moved a stored value from 100 to 200, then moves a stored value from 300 to 400. Afterward, it adds the stored value at 200 to the AC value (300/400) and halts.

Explain the individual purposes of the tag, block, and offset fields in the address for a direct mapped cache.

The tag field holds a value symbolizing an associated block of main memory where the data come from or goes to. The block field is the block number in the cache. The offset field is where the data is located within the cache block.

Why does transfer time for a hard disk take significantly longer than an SSD?

There are many reasons, and you could cover any of the following or more: - No mechanical moving parts - Seek time - Rotational delay - Better parallelization

(T/F) Real-time systems are very useful for systems with low latency requirements, such as process control.

True

(T/F) SR flip-flop states are named for the value of Q.

True

(T/F) The Program Counter keeps track of the next instruction to be fetched.

True

(T/F) Unmaskable interrupts cannot be interrupted by other interrupts.

True

(T/F) When performing a left shift, the value of the lowest order bit after the shift is always 0.

True

The ______ is the core of a modern operating system - responsible for scheduling and memory management.

kernel

Explain how and why an SIMD processor is more efficient for bitcoin mining than your computer's CPU.

Because bitcoin mining is a large number of simultaneous math operations, the ALUs in SIMD processors are very efficient when running the same instruction on multiple data elements simultaneously. A traditional processor would need to consume multiple clock cycles with multiple instructions to perform the same operations to mine bitcoin.

Explain what allowing the block transfer of multiple words on a bus means. What advantages are gained by allowing the block transfer of multiple words on a bus?

Block transfer of words means that a device can advertise how many words needs to be sent, and it can request bus access for multiple sequential cycles. Connected devices need to request the bus less frequently if multiple words needs to be sent.

With both the set and reset values set to 1, an SR flip-flop will have a Q value of A. 0 or 1 depending on the last powered set or reset line B. Unknown C. 0 D. 1

C. 0

Which of the following buses most commonly interconnects other buses? A. I/O bus B. Process-memory bus C. Backplane bus

C. Backplane bus

Which of the following is the accurate "binary contents" representation of the instruction "JUMP 200" in MARIE? (Hint: JUMP is instruction 9) A. 1001000100000000 B. 1001000100000100 C. 0001001000000000 D. 1001001000000000

D. 1001001000000000

The INPUT instruction during execution will change the value stored in which location(s) (multiple answers possible)? A. IR B. MBR C. MAR D. AC

D. AC

A circuit evaluates the equality of two strings. Which circuit is best suited for this purpose? A. Decoder B. Multiplexer C. Demultiplexer D. Comparator

D. Comparator

A CS value of 0, RD value of 1, and an OE value of 1 would cause what operation? A. Read B. Both read and write C. Write D. Neither

D. Neither

Interrupts that cannot be interrupted once interrupt processing are what classification? A. Maskable B. Synchronous C. Asynchronous D. Nonmaskable

D. Nonmaskable

Which of the following scheduling strategies would close out processes or jobs the quickest? A. First come, first served B. Round robin C. Priority scheduling D. Shortest job first

D. Shortest job first

Which of the following CPU components is responsible for performing math operations on operands? A. The Program Counter B. The Control Unit C. The Instruction Register D. The ALU

D. The ALU

A 1 bit ALU is pictured. Which function is selected by the decoder, and what is the value of the output bits? F_0 = 1, F_1 = 0, ENA = 1, ENB = 1, A = 1, B = 1, INVA = 0, Carry In = 1 A. AND, Output = 0 B. AND, Output = 1 C. OR, Output = 0 D. OR, Output = 1 E. NOT B, Output = 0 F. NOT B, Output = 1 G. ADD, Output = 0, Carry Out = 0 H. ADD, Output = 1, Carry Out = 0 I. ADD, Output = 0, Carry Out = 1 J. ADD, Output = 1, Carry Out = 1

E. NOT B, Output = 0

What is one reason why MARIE's microprogram statements have room for two microop codes? Why is the jump bit only one bit in MARIE's microprogram statements?

Examples are: - allowing an IF statement in MicroOp 1 to compare to data in MicroOp 2 - allow issuance of more than one microop code if both microop codes can be completed in a single clock cycle. The JUMP bit is only one bit because there are only two options: jump or don't jump. 1 bit can store both possible options.

Write the following function using the method discussed in class (hint: the out rows where you have 1):

F(A, B, C) = A'B'C + AB'C + ABC' + ABC

(T/F) A NAND gate has inputs A, B, and C. All inputs are high. The output of the gate will be high voltage.

False

(T/F) A powerful server is better than a disposable computer.

False

(T/F) A pulse generator connected to a D flip-flop limits the flip flop changing state to when no pulse is present on the enable line.

False

(T/F) Dynamic RAM is best used in CPU caches due to its density.

False

(T/F) Immediately writing from the cache to update main memory for every dirty block (write-through write policy) significantly impacts cache performance.

False

(T/F) NOT, NAND, and NOR gates will all output high voltage when all of their input voltages are high.

False

(T/F) On a virtual machine host system with a controlling program, the kernel of a HOSTED virtual machine runs in kernel mode of the host system.

False

(T/F) Short term operating system scheduling is responsible for determining which processes get admitted to the system.

False