Logic Design

Propagation Delay

A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur. Four categories of propagation delay times are important in the operation of a flip-flop: 1. Propagation delay tPLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output. 2. Propagation delay tPHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output. 3. Propagation delay tPLH as measured from the leading edge of the preset input to the LOW-to-HIGH transition of the output. 4. Propagation delay tPHL as measured from the leading edge of the clear input to the HIGH-to-LOW transition of the output.

Comparator

Compares the magnitudes of two binary quantities to determine the relationship of those quantities. In its simplest form, a comparator circuit determines whether two numbers are equal.

BCD-to-decimal decoder

Converts each BCD code into one of ten possible decimal digit indications. It is frequently referred as a 4-line-to-10-line decoder or a 1-of-10 decoder.

Serial In/Parallel Out Shift Registers

Data bits are entered serially (least-significant bit first) into a serial in/parallel out shift register in the same manner as in serial in/serial out registers. The difference is the way in which the data bits are taken out of the register; in the parallel output register, the out- put of each stage is available. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously, rather than on a bit-by-bit basis as with the serial output.

Stage

Each stage (flip-flop) in a shift register represents one bit of storage capacity; therefore, the number of stages in a register determines its storage capacity.

Synchronous

The output changes state only at a specified point (leading or trailing edge) on the triggering input called the clock (CLK), which is designated as a control input, C; that is, changes in the output occur in synchronization with the clock.

Power Dissipation

The power dissipation of any digital circuit is the total power consumption of the device. For example, if the flip-flop operates on a +5 V dc source and draws 5 mA of current, the power dissipation is P=VCC *ICC =5V*5mA=25mW The power dissipation is very important in most applications in which the capacity of the dc supply is a concern.

Determining an inequality of binary numbers

A and B, you first examine the highest- order bit in each number. The following conditions are possible: 1. If A3 = 1 and B3 = 0, number A is greater than number B. 2. If A3 = 0 and B3 = 1, number A is less than number B. 3. If A3 = B3, then you must examine the next lower bit position for an inequality.

Bidirectional shift register

A bidirectional shift register is one in which the data can be shifted either left or right. It can be implemented by using gating logic that enables the transfer of a data bit from one stage to the next stage to the right or to the left, depending on the level of a control line. A HIGH on the RIGHT/LEFT control input allows data bits inside the register to be shifted to the right, and a LOW enables data bits inside the register to be shifted to the left. An examination of the gating logic will make the operation apparent.

Encoder

A combinational logic circuit that essentially performs a "reverse" decoder function. An encoder accepts an active level on one of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded output, such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters.

Parallel Data Storage

A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flops. This operation is illustrated in Figure 7-35(a) using four flip-flops. Each of the four parallel data lines is connected to the D input of a flip-flop. The clock inputs of the flip-flops are connected together, so that each flip-flop is triggered by the same clock pulse.

Multiplexer (MUX)

A device that allows digital information from several sources to be routed onto a single line for transmission over that line to a common destination. The basic multiplexer has several data-input lines and a single output line. It also has data-select inputs, which permit digital data on any one of the inputs to be switched to the output line. Multiplexers are also known as data selectors.

Register

A digital circuit with two basic functions: data storage and data movement. The storage capability of a register makes it an important type of memory device. Figure 8-1 illustrates the concept of storing a 1 or a 0 in a D flip-flop. A 1 is applied to the data input as shown, and a clock pulse is applied that stores the 1 by setting the flip-flop. When the 1 on the input is removed, the flip-flop remains in the SET state, thereby storing the 1. A similar procedure applies to the storage of a 0 by resetting the flip-flop, as also illustrated in Figure 8-1.

Gated S-R Latch

A gated latch requires an enable input, EN (G is also used to designate an enable input). The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input. The latch will not change until EN is HIGH; but as long as it remains HIGH, the output is controlled by the state of the S and R inputs. The gated latch is a level-sensitive device. In this circuit, the invalid state occurs when both S and R are simultaneously HIGH and EN is also HIGH.

Latch

A latch is a type of bistable logic device or multivibrator.

Decimal-to-BCD priority encoder

A priority encoder also offers additional flexibility in that it can be used in applications that require priority detection. The priority function means that the encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will ignore any other lower-order active inputs.

Logic Function Generator

A useful application of the data selector/multiplexer is in the generation of combinational logic functions in sum-of-products form. When used in this way, the device can replace discrete gates, can often greatly reduce the number of ICs, and can make design changes much easier. To illustrate, a 74HC151 8-input data selector/multiplexer can be used to implement any specified 3-variable logic function if the variables are connected to the data-select inputs and each data input is set to the logic level required in the truth table for that function.

Preset and Clr

An active level on the preset input will set the flip-flop, and an active level on the clear input will reset it.

S-R (SET-RESET) Latch

An active-HIGH input S-R (SET-RESET) latch is formed with two cross-coupled NOR gates, an active-LOW input SR latch is formed with two cross-coupled NAND gates. Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback that is characteristic of all latches and flip-flops.

Asynchronous counter

An asynchronous counter is one in which the flip-flops (FF) within the counter do not change states at exactly the same time because they do not have a common clock pulse.

Frequency Division

Another application of a flip-flop is dividing (reducing) the frequency of a periodic wave- form. When a pulse waveform is applied to the clock input of a D or J-K flip-flop that is connected to toggle (D = Q or J = K = 1), the Q output is a square wave with one-half the frequency of the clock input.

Propagation delay (Async. Count.)

Asynchronous counters are commonly referred to as ripple counters for the following reason: The effect of the input clock pulse is first "felt" by FF0. This effect cannot get to FF1 immediately because of the propagation delay through FF0. Then there is the propagation delay through FF1 before FF2 can be triggered. Thus, the effect of an input clock pulse "ripples" through the counter, taking some time, due to propagation delays, to reach the last flip-flop.

Edge-triggered flip-flop

Changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.

Decoder

Digital circuit that detects the presence of a specified combination of bits (code) on its inputs and indicates the presence of that code by a specified output level. In its general form, a decoder has n input lines to handle n bits and from one to 2n output lines to indicate the presence of one or more n-bit combinations.

Parallel In/Serial Out Shift Registers

For a register with parallel data inputs, the bits are entered simultaneously into their respec- tive stages on parallel lines rather than on a bit-by-bit basis on one line as with serial data inputs. The serial output is the same as in serial in/serial out shift registers, once the data are completely stored in the register.

4-Bit Decoder cont.

If an active-LOW output is required for each decoded number, the entire decoder can be implemented with NAND gates and inverters. In order to decode each of the sixteen binary codes, sixteen NAND gates are required (AND gates can be used to produce active-HIGH outputs).

Logic Function Example

If the function is a 1 when the variable combination is A2A1A0, the 2 input (selected by 010) is connected to a HIGH. This HIGH is passed through to the output when this particular combination of variables occurs on the data-select lines.

4-Bit Decoder

In order to decode all possible combinations of four bits, sixteen decoding gates are required (24 = 16). This type of decoder is commonly called either a 4-line-to-16-line decoder because there are four inputs and sixteen outputs or a 1-of-16 decoder because for any given code on the inputs, one of the sixteen outputs is activated.

Gated D Latch

It differs from the S-R latch because it has only one input in addition to EN. When the D input is HIGH and the EN input is HIGH, the latch will set. When the D input is LOW and EN is HIGH, the latch will reset. Stated another way, the output Q follows the input D when EN is HIGH.

Pulse Widths

Minimum pulse widths (tW) for reliable operation are usually specified by the manufacturer for the clock, preset, and clear inputs. Typically, the clock is specified by its minimum HIGH time and its minimum LOW time.

Asynchronous inputs

Most integrated circuit flip-flops also have asynchronous inputs. These are inputs that affect the state of the flip-flop independent of the clock. They are normally labeled preset (PRE) and clear (CLR), or direct set (SD) and direct reset (RD) by some manufacturers.

2-Bit Asynchronous Binary Counter

Notice that the clock (CLK) is applied to the clock input (C) of only the first flip-flop, FF0, which is always the least significant bit (LSB). The second flip-flop, FF1, is triggered by the Q0 output of FF0. FF0 changes state at the positive-going edge of each clock pulse, but FF1 changes only when triggered by a positive-going transition of the Q0 output of FF0. Because of the inherent propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a transition of the Q0 output of FF0 can never occur at exactly the same time. Therefore, the two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.

Parallel In/Parallel Out Shift Registers

Parallel entry and parallel output of data have been discussed. The parallel in/parallel out register employs both methods. Immediately following the simultaneous entry of all data bits, the bits appear on the parallel outputs.

Flip-flops

Synchronous bistable devices, also known as bistable multivibrators. Flip-flops are edge-triggered or edge-sensitive whereas gated latches are level-sensitive.

BCD-to-7-Segment Decoder

The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive 7-segment display devices to produce a decimal readout.

D Flip-Flop

The D input of the D flip-flop is a synchronous input because data on the input are transferred to the flip-flop's output only on the triggering edge of the clock pulse.

J-K Flip-Flop

The J and K inputs of the J-K flip-flop are synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse.

BCD-to-Binary Conversion

The basic conversion process is as follows: 1. The value, or weight, of each bit in the BCD number is represented by a binary number. 2. All of the binary representations of the weights of bits that are 1s in the BCD number are added. 3. The result of this addition is the binary equivalent of the BCD number. The binary numbers representing the weights of the BCD bits are summed to produce the total binary number.

Remember (D)

The flip-flop cannot change state except on the triggering edge of a clock pulse. The D input can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output. Just remember, Q follows D at the triggering edge of the clock.

Remember (J-K)

The flip-flop cannot change state except on the triggering edge of a clock pulse. The J and K inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output.

Zero Suppression

The highest-order digit position (left-most) is always blanked if a zero code is on its BCD inputs because the RBI of the most-significant decoder is made LOW by connecting it to ground. The RBO of each decoder is connected to the RBI of the next lowest-order decoder so that all zeros to the left of the first nonzero digit are blanked.

Hold Time

The hold time (th) is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Maximum Clock Frequency

The maximum clock frequency (fmax) is the highest rate at which a flip-flop can be reliably triggered. At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough, and its operation would be impaired.

Serial In/Serial Out Shift Registers

The serial in/serial out shift register accepts data serially—that is, one bit at a time on a single line. It produces the stored information on its output also in serial form.

Set-up Time

The set-up time (ts) is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Shift capability

The shift capability of a register permits the movement of data from stage to stage within the register or into or out of the register upon application of clock pulses.

Storage capacity

The storage capacity of a register is the total number of bits (1s and 0s) of digital data it can retain.

Decimal-to-BCD Encoder

This type of encoder has ten inputs—one for each decimal digit—and four outputs corresponding to the BCD code. This is a basic 10-line-to-4-line encoder.

SET D Flip-Flop

When D is HIGH, the Q output goes HIGH on the triggering edge of the clock pulse, and the flip-flop is SET.

RESET D Flip-Flop

When D is LOW, the Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop is RESET.

SET J-K Flip-Flop

When J is HIGH and K is LOW, the Q output goes HIGH on the triggering edge of the clock pulse, and the flip-flop is SET.

RESET J-K Flip-Flop

When J is LOW and K is HIGH, the Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop is RESET.

Normal Operations of a Latch

When Q is HIGH, Q1 is LOW, and when Q is LOW, Q1 is HIGH.

Toggle mode

When both J and K are LOW, the output does not change from its prior state. When J and K are both HIGH, the flip-flop changes state.

SET state

When the Q output is HIGH, it will remain in this state indefinitely until a LOW is temporarily applied to the R input.

RESET state

When the Q output is LOW, the latch is in the RESET state. Now the latch remains indefinitely in the RESET state until a momentary LOW is applied to the S input.

Bidirectional shift operation

When the RIGHT/LEFT control input is HIGH, gates G1 through G4 are enabled, and the state of the Q output of each flip-flop is passed through to the D input of the following flip-flop. When a clock pulse occurs, the data bits are shifted one place to the right. When the RIGHT/LEFT control input is LOW, gates G5 through G8 are enabled, and the Q output of each flip-flop is passed through to the D input of the preceding flip-flop. When a clock pulse occurs, the data bits are then shifted one place to the left.