OSFinal

Consider a paging system with the page table stored in memory. (a) If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? (b) If we add associative registers, and 75% of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.)

*400 nanoseconds. 200 ns to access the page table plus 200 ns to access the word in memory. *250 nanoseconds. 75% of the time it's 200 ns, and the other 25% of the time it's 400ns, so the equation is: e.a. = (.75*200)+(.25*400) Try this, too: What if the time to access the associative registers is actually 2 ns -- how does your answer change? e.a. = 2 + (.75*200)+(.25*400) Remember that you *always* have to perform the TLB lookup, whether or not the page is found there.

Assume that we have a demand-paged memory. The page table is held in registers. It takes 8 milliseconds to service a page fault if an empty frame is available or if the replaced page is not modified and 20 milliseconds if the replaced page is modified. Memory-access time is 100 nanoseconds. Assume that the page to be replaced is modified 70 percent of the time. What is the maximum acceptable page-fault rate for an effective access time of no more than 200 nanoseconds?

200 ns = (1 − P) × 100 ns + (0.30P) × 8 millisec + (0.70P) × 20 millisec 200 ns = (1 − P) × 100 ns + (0.30P) × 8 × 10 6 + (0.70P) × 20 × 10 6 100 = −100P + 2.4 × 10 6 P + 14 × 10 6 P 1 = 16,4 × 10 4 P P = 0.000006

Consider a computer system with a 32-bit logical address of 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following?

2^(11)< 4000 < 2^(12), so we need 12 out of 32 bit logical address for the offset. Then we have 32 12 20 bits left for the page number. There are, therefore, 2^(20) = 1048576 entries in a conventional single-level page table.

A certain computer provides its users with a virtual-memory space of 2^(32) bytes. The computer has 2^(18) bytes of physical memory. The virtual memory is implemented by paging, and the page size is 4096 bytes. A user process generates the virtual address 11123456. Explain how the system establishes the corresponding physical location. Distinguish between software and hardware operations.

A certain computer provides its users with a virtual-memory space of 232 bytes. The computer has 218 bytes of physical memory. The virtual memory is implemented by paging, and the page size is 4096 bytes. A user process generates the virtual address 11123456. Explain how the system establishes the corresponding physical location. Distinguish between software and hardware operations. or The virtual address in binary form is 0001 0001 0001 0010 0011 0100 0101 0110 Since the page size is 2**12, the page table size is 2**20. Therefore, the low-order 12 bits (0100 0101 0110) are used as the displacement into the page, while the remaining 20 bits (0001 0001 0001 0010 0011) are used as the displacement in the page table. Consider the operations that are needed (a) for DAT, and (b) for page fault servicing. All the DAT operations are carried out in hardware. But of the list of operations for page faults, on pp. 297-298, *at*least* steps 2, 4, 5, 6, 8, 10, and 12 involve software operations.

Under what circumstances do page faults occur? Describe the actions taken by the operating system when a page fault occurs.

A page fault occurs when an access to a page that has not been brought into main memory takes place. The operating system verifies the memory access, aborting the program if it is invalid. If it is valid, a free frame is located and I/O is requested to read the needed page into the free frame. Upon completion of I/O, the process table and page table are updated and the instruction is restarted.

What is the copy-on-write feature and under what circumstances is it beneficial to use this feature? What is the hardware support required to implement this feature?

Copy on Write allows processes to share pages rather than each having a separate copy of the pages. However, when one process tried to write to a shared page, then a trap is generated and the OS makes a separate copy of the page for each process. This is commonly used in a fork() operation where the child is supposed to have a complete copy of the parent address space. Rather than create a separate copy, the OS allows the parent and child to share the parent's pages. However, since each is supposed to have its own private copy of the pages, the pages are copied when one of them attemps a write. The hardware support required to implement is simply the following: on each memory access, the page table needs to be consulted to checkwhether the page iswrite-protected. If it is indeedwrite-protected, a trap would occur and the operating system could resolve the issue.

Suppose that a disk drive has 5,000 cylinders, numbered 0 to 4,999. The drive is currently serving a request at cylinder 2,150, and the previous request was at cylinder 1,805. The queue of pending requests, in FIFO order, is: 2,069, 1,212, 2,296, 2,800, 544, 1,618, 356, 1,523, 4,965, 3681 Starting from the current head position, what is the total distance (in cylinders) that the disk arm moves to satisfy all the pending requests for each of the following diskscheduling algorithms? a. FCFS b. SSTF c. SCAN d. LOOK

FCFS: 2150-> 2069-> 1212-> 2296 -> 2800 -> 544 -> 1618 -> 356 1523 4965 3681 = 81+857+1084+504+2256+1074+1262+1167+3442+1284 = 13011 SSTF: 2150 2069 2296 2800 3681 4965 1618 1523 1212544 356 = 81+227+504+881+1284+3347+95+311+668+188 = 7586 SCAN: 2150 2296 2800 3681 4965 4999 2069 1618 1523 1212 544 356 = 2849+4643=7492 LOOK: 2150 2296 2800 3681 4965 2069 1618 1523 1212 544 356 = 2815+4609=7424

Discuss the hardware support required to support demand paging.

For every memory-access operation, the page table needs to be consulted to check whether the corresponding page is resident or not and whether the program has read or write privileges for accessing the page. These checks have to be performed in hardware. A TLB could serve as a cache and improve the performance of the lookup operation.

What is the purpose of paging the page tables?

In certain situations the page tables could becomelarge enough that by paging the page tables, one could simplify the memory allocation problem (by ensuring that everything is allocated as fixed-size pages as opposed to variable-sized chunks) and also enable the swapping of portions of page table that are not currently used.

Consider the following page reference string: 7, 2, 3, 1, 2, 5, 3, 4, 6, 7, 7, 1, 0, 5, 4, 6, 2, 3, 0 , 1. Assuming demand paging with three frames, how many page faults would occur for the following replacement algorithms?

LRU replacement 7 7 7 1 1 3 3 3 7 7 7 5 5 5 2 2 2 1 2 2 2 2 2 4 4 4 1 1 1 4 4 4 3 3 3 3 3 5 5 5 6 6 6 0 0 0 6 6 6 0 0 FIFO replacement 7 7 7 1 1 1 6 6 6 0 0 0 6 6 6 0 0 2 2 2 5 5 5 7 7 7 5 5 5 2 2 2 1 3 3 3 4 4 4 1 1 1 4 4 4 3 3 3 Optimal replacement 7 7 7 1 1 1 1 1 1 1 1 1 1 2 2 2 5 5 5 5 5 4 6 2 3 3 3 3 4 6 7 0 0 0 0 0

Why is rotational latency usually not considered in disk scheduling? How would you modify SSTF, SCAN, and C-SCAN to include latency optimization?

Most disks do not export their rotational position information to the host. Even if they did, the time for this information to reach the scheduler would be subject to imprecision and the time consumed by the scheduler is variable, so the rotational position information would become incorrect. Further, the disk requests are usually given in terms of logical block numbers, and the mapping between logical blocks and physical locations is very complex.

Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. How many page faults would occur for the following replacement algorithms, assuming one, two, three, four, five, six, or seven frames? Remember all frames are initially empty, so your first unique pages will all cost one fault each. • LRU replacement • FIFO replacement • Optimal replacement

Number of frames LRU FIFO Optimal 1 20 20 20 2 18 18 15 3 15 16 11 4 10 14 8 5 8 10 7 6 7 10 7 7 7 7 7

Explain why SSTF scheduling tends to favor middle cylinders over the innermost and outermost cylinders.

The center of the disk is the location having the smallest average distance to all other tracks. Thus the disk head tends to move away from the edges of the disk. Here is another way to think of it. The current location of the head divides the cylinders into two groups. If the head is not in the center of the disk and a new request arrives, the new request is more likely to be in the group that includes the center of the disk; thus, the head is more likely to move in that direction.

A simplified view of thread states is Ready, Running, and Blocked, where a thread is either ready and waiting to be scheduled, is running on the processor, or is blocked (i.e. is waiting for I/O). This is illustrated in the following figure. Assuming a thread is in the Running state, answer the following questions (Be sure to explain your answer). a) Will the thread change state if it incurs a page fault? If so, to what new state? b)Will the thread change state if it generates a TLB miss that is resolved in the page table? If so, to what new state? c)Will the thread change state if an address reference is resolved in the page table? If so, to what new state?

a) Yes, a tread changes from the Running state to the Blocked state when a page fault occurs. b) Not necessarily. If a page table entry is not found in the TLB (TLB miss), the page number is used to index and process the page table. If the page is already in main memory, then TLB is updated to include the new page entry, while the process execution continues since there is no I/O operation needed. If the page is not in the main memory, a page fault is generated. In this case, the process needs to change to the Blocked state and wait for I/O to access the disk. This is the same procedure as in the first question. c) No, because no I/O operation is needed is the address reference is resolved in the page table, which indicates the page needed is loaded in the main memory already.

Consider the following segment table: Segment Base Length 0 219 600 1 2300 14 2 90 100 3 1327 580 4 1952 96 What are the physical addresses for the following logical addresses? a. 0,430 b. 1,10 c. 2,500 d. 3,400 e. 4,112

a. 219 + 430 = 649 b. 2300 + 10 = 2310 c. illegal reference, trap to operating system d. 1327 + 400 = 1727 e. illegal reference, trap to operating system

Consider the two-dimensional array A: int A[][] = new int[100][100]; where A[0][0] is at location 200 in a paged memory system with pages of size 200. A small process that manipulates the matrix resides in page 0 (locations 0 to 199). Thus, every instruction fetch will be from page 0. For three page frames, how many page faults are generated by the following array-initialization loops, using LRU replacement and assuming that page frame 1 contains the process and the other two are initially empty? a. for (int j = 0; j < 100; j++) for (int i = 0; i < 100; i++) A[i][j] = 0; b. for (int i = 0; i < 100; i++) for (int j = 0; j < 100; j++) A[i][j] = 0;

a. 5,000 b. 50

Consider a demand-paged computer system where the degree of multiprogramming is currently fixed at four. The system was recently measured to determine utilization of CPU and the paging disk. The results are one of the following alternatives. For each case, what is happening? Can the degree of multiprogramming be increased to increase the CPU utilization? Is the paging helping? a. CPU utilization 13 percent; disk utilization 97 percent b. CPU utilization 87 percent; disk utilization 3 percent c. CPU utilization 13 percent; disk utilization 3 percent

a. Thrashing is occurring. b. CPU utilization is sufficiently high to leave things alone, and increase degree of multiprogramming. c. Increase the degree of multiprogramming.

Assume that you have a page-reference string for a process with m frames (initially all empty). The page-reference string has length p; n distinct page numbers occur in it. Answer these questions for any page-replacement algorithms: a. What is a lower bound on the number of page faults? b. What is an upper bound on the number of page faults?

a. n b. p

An operating system supports a paged virtual memory, using a central processor with a cycle time of 1 microsecond. It costs an additional 1 microsecond to access a page other than the current one. Pages have 1000 words, and the paging device is a drum that rotates at 3000 revolutions per minute and transfers 1 million words per second. The following statistical measurements were obtained from the system: • 1 percent of all instructions executed accessed a page other than the current page. • Of the instructions that accessed another page, 80 percent accessed a page already in memory. Practice Exercises 31 • When a new page was required, the replaced page was modified 50 percent of the time. Calculate the effective instruction time on this system, assuming that the system is running one process only and that the processor is idle during drum transfers.

effective access time = 0.99 × (1 sec + 0.008 × (2 sec) + 0.002 × (10,000 sec + 1,000 sec) + 0.001 × (10,000 sec + 1,000 sec) = (0.99 + 0.016 + 22.0 + 11.0) sec = 34.0 microsec

Consider the page table shown in Figure 9.30 for a system with 12-bit virtual and physical addresses and with 256-byte pages. The list of free page frames is D, E, F (that is, D is at the head of the list, E is second, and F is last). Convert the following virtual addresses to their equivalent physical addresses in hexadecimal. All numbers are given in hexadecimal. (A dash for a page frame indicates that the page is not in memory.) • 9EF • 111 • 700 • 0FF

• 9E F - 0E F • 111 - 211 • 700 - D00 • 0F F - EFF