System Integration and Performance Questions
Under direct memory access, a device called a ____ is attached to the bus and to main memory.
DMA controller
____________________ ports enable the CPU and bus to interact with a keyboard in the same way they interact with a disk drive or video display.
I/O
A(n) ____ is a communication pathway from the CPU to a peripheral device.
I/O port
A PC usually transmits data one bit at a time over a wireless connection, and a laser printer prints an entire page at once.
True
A system bus can be conceptually or physically divided into specialized subsets, including the data, address, control, and power buses.
True
A system bus connects computer system components, including the CPU, memory, storage, and I/O devices.
True
Both multicore and multiple-processor architectures are examples of scaling up because they increase the power of a single computer system.
True
Data written to a cache during a write operation isn't automatically removed from the cache after it's written to the underlying storage device.
True
Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes.
True
Disk caching is common in modern computer systems, particularly in file and database servers.
True
During a write operation, a cache acts similarly to a buffer.
True
MP3 compresses the audio data stream by discarding information about masked sounds or representing them with fewer bits.
True
People routinely download megabytes or gigabytes of data via the Internet and store gigabytes of data on handheld devices, terabytes on desktop computers, and petabytes to exabytes in corporate and government data centers.
True
Serial channels in buses are more reliable than parallel channels at very high speeds.
True
The OS is the best source of file access information because it updates information dynamically as its services file access requests.
True
The memory bus has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and (in most computers) large number of parallel communication lines.
True
Until the 1990s, scaling up was almost always a more cost-effective strategy to increase available computer power because communication between computers was extremely slow compared with communication between a single computer's components.
True
Using data compression alters the balance of processor resources and communication or storage resources in a computer system.
True
When multiple processors occupy a single motherboard, they share primary storage and a single system bus.
True
Zip files and archives are examples of lossless compression.
True
A cache miss requires performing a(n) ____________________ to or from the storage device.
cache swap
_____ is a technique that reduces the number of bits used to encode data, such as a file or a stream of video images transmitted across the Internet.
compression
____________________ is incorporated into all modern videoconferencing standards to reduce use of available data transfer capacity.
compression
A ____ is a mathematical compression technique implemented as a program
compression algorithm
The term ____ describes the ratio of data size in bits or bytes before and after compression.
compression ratio
Computer system components coordinate their activities by sending signals over the ____________________.
control bus
The ____ carries commands, command responses, status codes, and similar messages.
control bus
If the CPU is idle while a device completes an access request, the CPU cycles that could have been (but weren't) devoted to instruction execution are called ____.
I/O wait states
The ratio of cache hits to read accesses is called the cache's ____.
hit ratio
The main goal of buffering and caching is to ____.
improve overall system performance
Mismatches in data transfer rate and data transfer unit size are addressed in part by ____________________, which consumes substantial CPU resources.
interrupt processing
A portion of the CPU, separate from the components that fetch and execute instructions, monitors the bus continuously for interrupt signals and copies them to a(n) ____________________.
interrupt register
Data, address, and command bits are transmitted across PCI bus line subsets called "____".
lanes
The ____ states that when multiple resources are required to produce something useful, adding more of a single resource produces fewer benefits.
law of diminishing returns
When three cache levels are in use, the cache closest to the CPU is called a ____ cache.
level one
When three cache levels are in use, the cache farthest from the CPU is called a ____ cache.
level three
With ____ compression, any data input that's compressed and then decompressed is exactly the same as the original input.
lossless
____________________ compression is required in many applications, such as accounting records, executable programs, and most stored documents.
lossless
With ____ compression, data inputs that are compressed and then decompressed are different from, but still similar to, the original input.
lossy
____________________ compression is usually applied only to audio and video data because the human brain tolerates missing audio and video data and can usually "fill in the blanks."
lossy
In most computers, an I/O port is a ____.
memory address
The ____ connects only the CPU and memory.
memory bus
The latest trend in high-performance CPU design embeds multiple CPUs and cache memory on a single chip—an approach called ____.
multicore architecture
____ is a cost-effective approach to computer system design when a single computer runs many different application programs or services.
multiple-processor architecture
____________________ is a more traditional approach to multiprocessing that uses two or more processors on a single motherboard or set of interconnected motherboards.
multiple-processor architecture
In a ____, any device can assume control of the bus or act as a bus master for transfers to any other device.
peer-to-peer bus
____ is a family of bus standards found in nearly all small and midrange computers and many larger ones.
peripheral component interconnect
There are typically multiple storage and I/O devices connected to a computer, collectively referred to as ____.
peripheral devices
One task performed by a storage device controller is translating logical write operations into ____ write operations.
physical
The ____________________ distributes electrical power to directly attached devices or their device controllers.
power bus
Most performance benefits of a cache occur during ____.
read operations
_____ is an approach that partitions processing and other tasks among multiple computer systems.
scaling out
The phrase ____ describes approaches to increasing processing and other computer system power by using larger and more powerful computers.
scaling up
As single bits are transferred over the wireless connection, they're added to the buffer in ____________________ order.
sequential
A ____ is a reserved area of main memory accessed on a last-in, first-out (LIFO) basis.
stack
A special-purpose register called the ____________________ always points to the next empty address in the stack and is incremented or decremented automatically each time the stack is pushed or popped.
stack pointer
A ____ connects secondary storage devices to the system bus.
storage bus
____________________ buses connect a subset of computer components and are specialized for these components' characteristics and communication between them.
subsidiary
When the CPU detects an interrupt, it executes a master interrupt handler program called the ____________________.
supervisor
The ____________________ bus improves computer system performance by removing video traffic from the system bus and providing a high-capacity one-way communication channel optimized for video data.
video
As buffer size increases above ____ bytes, CPU cycle consumption decreases at a linear rate.
8
Lossy compression of audio and video can achieve compression ratios up to ____.
50:1
In traditional computer architecture, the ____________________ is the focus of all computer activity.
CPU
A buffer for an I/O device is typically implemented on the sending computer.
False
A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors.
False
Lossless compression ratios higher than 50:1 is difficult or impossible to achieve with audio and video data.
False
Multiple-processor architecture is not common in workstations.
False
One way to limit wait states is to use an SDRAM cache between the CPU and SRAM primary storage.
False
Peer-to-peer bus protocols are substantially less complex but more expensive than master-slave bus protocols.
False
Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.
False
Reducing the size of stored or transmitted data can improve performance whenever there's a dearth of processing power.
False
Secondary storage devices are much faster than the system bus.
False
The CPU communicates with a peripheral device by moving data to or from an I/O port's dedicated bus.
False
The largest computational problems, such as those encountered in modeling three-dimensional physical phenomena, can be solved by a single computer as long as it has enough computing resources.
False
Until the 2000s, system buses were always constructed with serial electrical lines.
False
With serial communication lines in a bus, each line carries only one bit value or signal at a time, and many lines are required to carry data, address, and control bits.
False
A(n) ____________________ can improve system performance when two devices have different data transfer rates, as when copying music files from a PC to an iPod via a USB 2.0 connection.
buffer
A(n) ____________________ is a small reserved area of main memory (usually DRAM or SRAM) that holds data in transit from one device to another and is required to resolve differences in data transfer unit size.
buffer
If a buffer isn't large enough to hold and entire unit of data transfer, an error called a ____ occurs.
buffer overflow
A ____ is a shared electrical or optical channel that connects two or more devices.
bus
In the simplest sense, a(n) ____________________ is just a set of communication lines.
bus
A ____ is a simple processor attached to a peer-to-peer bus that decides which devices must wait when multiple devices want to become a bus master.
bus arbitration unit
Devices attached to a system bus coordinate and synchronize their activities with a common ____.
bus clock
When the CPU is the focus of all computer activity, it's also the ____.
bus master
The ____ governs the format, content, and timing of data, memory addresses, and control messages sent across the bus.
bus protocol
When the CPU is the focus of all computer activity, all other devices are ____.
bus slaves
Like a buffer, a(n) ____________________ is a reserved area of high-speed memory (usually RAM) that improves system performance.
cache
A ____ is a processor that guesses what data will be requested in the near future and loads this data from the storage device into the cache before it's actually requested.
cache controller
When a read operation accesses data already contained in the cache, the access is called a(n) ____________________.
cache hit
When the data needed isn't in the cache, the access is called a ____.
cache miss
The ____________________ transmits data between computer system components.
data bus
Most compression algorithms have a corresponding ____________________ algorithm that restores compressed data to its original or nearly original state.
decompression
Storage and I/O devices are normally connected to the system bus or a subsidiary bus through a(n) ____________________.
device controller
A(n) ____________________ bus, such as a Universal serial Bus, connects one or more external devices to the system bus.
external I/O
Many computer system designers rely on ____ to implement disk caching.
the OS
